[ac7d5ef0] | 1 | /* Clock_init() |
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| 2 | * |
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| 3 | * This routine initializes the Z80386 1 on the MVME136 board. |
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| 4 | * The tick frequency is 1 millisecond. |
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| 5 | * |
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| 6 | * Input parameters: NONE |
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| 7 | * |
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| 8 | * Output parameters: NONE |
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| 9 | * |
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| 10 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * All rights assigned to U.S. Government, 1994. |
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| 13 | * |
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| 14 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 15 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 16 | * notice must appear in all copies of this file and its derivatives. |
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| 17 | * |
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| 18 | * $Id$ |
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| 19 | */ |
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| 20 | |
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| 21 | #include <stdlib.h> |
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| 22 | |
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| 23 | #include <bsp.h> |
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[3a4ae6c] | 24 | #include <rtems/libio.h> |
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[ac7d5ef0] | 25 | #include <z8036.h> |
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| 26 | |
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| 27 | #define MICRVAL 0xe2 /* disable lower chain, no vec */ |
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| 28 | /* set right justified addr */ |
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| 29 | /* and master int enable */ |
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| 30 | #define MCCRVAL 0xc4 /* enable T1 and port B */ |
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| 31 | /* timers independent */ |
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| 32 | #define MS_COUNT 0x07d0 /* T1's countdown constant (1 ms) */ |
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| 33 | #define T1MSRVAL 0x80 /* T1 cont. cycle/pulse output */ |
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| 34 | #define T1CSRVAL 0xc6 /* enable interrupt, allow and */ |
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| 35 | /* and trigger countdown */ |
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| 36 | |
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[3a4ae6c] | 37 | #define TIMER 0xfffb0000 |
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| 38 | #define RELOAD 0x24 /* clr IP & IUS,allow countdown */ |
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| 39 | |
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| 40 | #define CLOCK_VECTOR 66 |
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| 41 | |
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[ac7d5ef0] | 42 | rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ |
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[3a4ae6c] | 43 | |
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| 44 | volatile rtems_unsigned32 Clock_driver_ticks; /* ticks since initialization */ |
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| 45 | |
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[ac7d5ef0] | 46 | rtems_isr_entry Old_ticker; |
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| 47 | |
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[3a4ae6c] | 48 | void Clock_exit( void ); |
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[ac7d5ef0] | 49 | |
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[3a4ae6c] | 50 | /* |
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| 51 | * These are set by clock driver during its init |
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| 52 | */ |
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| 53 | |
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| 54 | rtems_device_major_number rtems_clock_major = ~0; |
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| 55 | rtems_device_minor_number rtems_clock_minor; |
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| 56 | |
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| 57 | /* |
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| 58 | * ISR Handler |
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| 59 | */ |
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| 60 | |
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| 61 | rtems_isr Clock_isr( |
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| 62 | rtems_vector_number vector |
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[ac7d5ef0] | 63 | ) |
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| 64 | { |
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[3a4ae6c] | 65 | Clock_driver_ticks += 1; |
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| 66 | ((volatile struct z8036_map *) TIMER)->CT1_CMD_STATUS = RELOAD; |
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[ac7d5ef0] | 67 | |
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[3a4ae6c] | 68 | if ( Clock_isrs == 1 ) { |
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| 69 | rtems_clock_tick(); |
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| 70 | Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; |
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| 71 | } |
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| 72 | else |
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| 73 | Clock_isrs -= 1; |
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[ac7d5ef0] | 74 | } |
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| 75 | |
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| 76 | void Install_clock( |
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| 77 | rtems_isr_entry clock_isr |
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| 78 | ) |
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| 79 | { |
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| 80 | volatile struct z8036_map *timer; |
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| 81 | |
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| 82 | Clock_driver_ticks = 0; |
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| 83 | Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; |
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| 84 | |
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| 85 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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[3a4ae6c] | 86 | Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); |
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[ac7d5ef0] | 87 | timer = (struct z8036_map *) 0xfffb0000; |
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| 88 | timer->MASTER_INTR = MICRVAL; |
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| 89 | timer->CT1_MODE_SPEC = T1MSRVAL; |
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| 90 | |
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[3a4ae6c] | 91 | *((rtems_unsigned16 *)0xfffb0016) = MS_COUNT; /* write countdown value */ |
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| 92 | |
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| 93 | /* |
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| 94 | * timer->CT1_TIME_CONST_MSB = (MS_COUNT >> 8); |
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| 95 | * timer->CT1_TIME_CONST_LSB = (MS_COUNT & 0xff); |
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| 96 | */ |
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| 97 | |
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[ac7d5ef0] | 98 | timer->MASTER_CFG = MCCRVAL; |
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| 99 | timer->CT1_CMD_STATUS = T1CSRVAL; |
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| 100 | |
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[3a4ae6c] | 101 | /* |
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| 102 | * Enable interrupt via VME interrupt mask register |
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| 103 | */ |
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[ac7d5ef0] | 104 | (*(rtems_unsigned8 *)0xfffb0038) &= 0xfd; |
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| 105 | |
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| 106 | atexit( Clock_exit ); |
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| 107 | } |
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| 108 | |
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| 109 | } |
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| 110 | |
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[3a4ae6c] | 111 | void ReInstall_clock( |
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| 112 | rtems_isr_entry clock_isr |
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| 113 | ) |
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| 114 | { |
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| 115 | rtems_unsigned32 isrlevel; |
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| 116 | |
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| 117 | rtems_interrupt_disable( isrlevel ); |
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| 118 | (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); |
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| 119 | rtems_interrupt_enable( isrlevel ); |
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| 120 | } |
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| 121 | |
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[ac7d5ef0] | 122 | void Clock_exit( void ) |
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| 123 | { |
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| 124 | volatile struct z8036_map *timer; |
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| 125 | |
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| 126 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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| 127 | timer = (struct z8036_map *) 0xfffb0000; |
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| 128 | timer->MASTER_INTR = 0x62; |
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| 129 | timer->CT1_MODE_SPEC = 0x00; |
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| 130 | timer->MASTER_CFG = 0xf4; |
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| 131 | timer->CT1_CMD_STATUS = 0x00; |
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| 132 | /* do not restore old vector */ |
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| 133 | } |
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| 134 | } |
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[3a4ae6c] | 135 | |
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| 136 | rtems_device_driver Clock_initialize( |
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| 137 | rtems_device_major_number major, |
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| 138 | rtems_device_minor_number minor, |
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| 139 | void *pargp |
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| 140 | ) |
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| 141 | { |
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| 142 | Install_clock( Clock_isr ); |
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| 143 | |
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| 144 | /* |
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| 145 | * make major/minor avail to others such as shared memory driver |
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| 146 | */ |
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| 147 | |
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| 148 | rtems_clock_major = major; |
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| 149 | rtems_clock_minor = minor; |
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| 150 | |
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| 151 | return RTEMS_SUCCESSFUL; |
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| 152 | } |
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| 153 | |
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| 154 | rtems_device_driver Clock_control( |
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| 155 | rtems_device_major_number major, |
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| 156 | rtems_device_minor_number minor, |
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| 157 | void *pargp |
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| 158 | ) |
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| 159 | { |
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| 160 | rtems_libio_ioctl_args_t *args = pargp; |
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| 161 | |
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| 162 | if (args == 0) |
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| 163 | goto done; |
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| 164 | |
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| 165 | /* |
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| 166 | * This is hokey, but until we get a defined interface |
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| 167 | * to do this, it will just be this simple... |
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| 168 | */ |
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| 169 | |
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| 170 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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| 171 | { |
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| 172 | Clock_isr(CLOCK_VECTOR); |
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| 173 | } |
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| 174 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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| 175 | { |
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| 176 | ReInstall_clock(args->buffer); |
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| 177 | } |
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| 178 | |
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| 179 | done: |
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| 180 | return RTEMS_SUCCESSFUL; |
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| 181 | } |
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| 182 | |
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