1 | /* |
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2 | * $Id |
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3 | */ |
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4 | |
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5 | #include <mrm332.h> |
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6 | #include <rtems/m68k/sim.h> |
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7 | #define __START_C__ |
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8 | #include "bsp.h" |
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9 | |
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10 | rtems_isr_entry M68Kvec[256]; |
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11 | rtems_isr_entry vectors[256]; |
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12 | |
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13 | void boot_card(const char *cmdline); |
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14 | |
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15 | /* |
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16 | * This prototype really should have the noreturn attribute but |
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17 | * that causes a warning. Not sure how to fix that. |
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18 | */ |
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19 | /* void dumby_start () __attribute__ ((noreturn)); */ |
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20 | void start_c(void); |
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21 | |
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22 | void start_c(void) { |
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23 | |
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24 | /* Synthesizer Control Register */ |
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25 | /* see section(s) 4.8 */ |
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26 | /* end include in ram_init.S */ |
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27 | *SYNCR = (unsigned short int) |
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28 | ( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) ); |
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29 | while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */ |
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30 | /* include in ram_init.S */ |
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31 | *SYNCR = (unsigned short int) |
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32 | ( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) ); |
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33 | |
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34 | /* System Protection Control Register */ |
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35 | /* !!! can only write to once after reset !!! */ |
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36 | /* see section 3.8.4 of the SIM Reference Manual */ |
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37 | *SYPCR = (unsigned char)( HME | BME ); |
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38 | |
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39 | /* Periodic Interrupr Control Register */ |
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40 | /* see section 3.8.2 of the SIM Reference Manual */ |
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41 | *PICR = (unsigned short int) |
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42 | ( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) ); |
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43 | /* ^^^ zero disables interrupt, don't enable here or ram_init will |
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44 | be wrong. It's enabled below. */ |
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45 | |
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46 | /* Periodic Interrupt Timer Register */ |
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47 | /* see section 3.8.3 of the SIM Reference Manual */ |
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48 | *PITR = (unsigned short int)( SAM(0x09,0,PITM) ); |
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49 | /* 1.098mS interrupt, assuming 32.768 KHz input clock */ |
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50 | |
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51 | /* Port C Data */ |
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52 | /* load values before enabled */ |
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53 | *PORTC = (unsigned char) 0x0; |
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54 | |
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55 | /* Port E and F Data Register */ |
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56 | /* see section 9 of the SIM Reference Manual */ |
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57 | *PORTE0 = (unsigned char) 0; |
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58 | *PORTF0 = (unsigned char) 0; |
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59 | |
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60 | /* Port E and F Data Direction Register */ |
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61 | /* see section 9 of the SIM Reference Manual */ |
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62 | *DDRE = (unsigned char) 0xff; |
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63 | *DDRF = (unsigned char) 0xfd; |
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64 | |
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65 | /* Port E and F Pin Assignment Register */ |
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66 | /* see section 9 of the SIM Reference Manual */ |
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67 | *PEPAR = (unsigned char) 0; |
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68 | *PFPAR = (unsigned char) 0; |
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69 | |
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70 | /* end of SIM initalization code */ |
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71 | /* end include in ram_init.S */ |
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72 | |
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73 | /* |
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74 | * Initialize RAM by copying the .data section out of ROM (if |
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75 | * needed) and "zero-ing" the .bss section. |
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76 | */ |
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77 | { |
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78 | register char *src = _etext; |
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79 | register char *dst = _copy_start; |
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80 | |
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81 | if (_copy_data_from_rom) |
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82 | /* ROM has data at end of text; copy it. */ |
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83 | while (dst < _edata) |
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84 | *dst++ = *src++; |
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85 | |
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86 | /* Zero bss */ |
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87 | for (dst = _clear_start; dst< end; dst++) |
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88 | { |
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89 | *dst = 0; |
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90 | } |
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91 | } |
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92 | |
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93 | /* |
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94 | * Initialize vector table. |
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95 | */ |
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96 | { |
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97 | rtems_isr_entry *monitors_vector_table; |
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98 | |
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99 | m68k_get_vbr(monitors_vector_table); |
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100 | |
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101 | M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */ |
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102 | M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */ |
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103 | M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */ |
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104 | M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */ |
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105 | M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */ |
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106 | |
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107 | m68k_set_vbr(&M68Kvec); |
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108 | } |
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109 | |
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110 | /* |
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111 | * Initalize the board. |
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112 | */ |
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113 | |
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114 | /* Spurious should be called in the predriver hook */ |
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115 | /* Spurious_Initialize(); */ |
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116 | /*console_init(); */ |
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117 | |
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118 | /* |
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119 | * Execute main with arguments argc and agrv. |
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120 | */ |
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121 | boot_card((void*)0); |
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122 | reboot(); |
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123 | |
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124 | } |
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