1 | /* |
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2 | * $Id |
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3 | */ |
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4 | |
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5 | #include <mrm332.h> |
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6 | #include <sim.h> |
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7 | #define __START_C__ |
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8 | #include "bsp.h" |
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9 | |
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10 | m68k_isr_entry M68Kvec[256]; |
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11 | m68k_isr_entry vectors[256]; |
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12 | char * const __argv[]= {"main", ""}; |
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13 | |
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14 | void boot_card(int argc, char * const argv[]); |
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15 | |
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16 | /* |
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17 | * This prototype really should have the noreturn attribute but |
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18 | * that causes a warning. Not sure how to fix that. |
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19 | */ |
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20 | /* void dumby_start () __attribute__ ((noreturn)); */ |
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21 | void dumby_start (); |
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22 | |
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23 | void dumby_start() { |
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24 | |
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25 | /* Put the header necessary for the modified CPU32bug to automatically |
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26 | start up rtems: */ |
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27 | asm volatile ( ".long 0xbeefbeef ; |
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28 | .long 0 ; |
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29 | .long start"); |
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30 | |
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31 | /* We need to by-pass the link instruction since the RAM chip- |
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32 | select pins are not yet configured. */ |
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33 | asm volatile ( ".global start ; |
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34 | start:"); |
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35 | |
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36 | /* disable interrupts, copy CPU32bug vectors, load stack pointer */ |
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37 | asm volatile ( "oriw #0x0700, %sr; |
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38 | movel #end, %d0; |
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39 | addl #_StackSize,%d0; |
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40 | movel %d0,%sp; |
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41 | movel %d0,%a6" |
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42 | ); |
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43 | |
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44 | /* include in ram_init.S */ |
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45 | /* |
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46 | * Initalize the SIM module. |
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47 | * The stack pointer is not usable until the RAM chip select lines |
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48 | * are configured. The following code must remain inline. |
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49 | */ |
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50 | |
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51 | /* Module Configuration Register */ |
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52 | /* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */ |
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53 | *SIMCR = (unsigned short int) |
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54 | (FRZSW | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB)); |
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55 | |
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56 | /* Synthesizer Control Register */ |
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57 | /* see section(s) 4.8 */ |
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58 | /* end include in ram_init.S */ |
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59 | *SYNCR = (unsigned short int) |
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60 | ( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) ); |
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61 | while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */ |
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62 | /* include in ram_init.S */ |
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63 | *SYNCR = (unsigned short int) |
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64 | ( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) ); |
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65 | |
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66 | /* System Protection Control Register */ |
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67 | /* !!! can only write to once after reset !!! */ |
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68 | /* see section 3.8.4 of the SIM Reference Manual */ |
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69 | *SYPCR = (unsigned char)( HME | BME ); |
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70 | |
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71 | /* Periodic Interrupr Control Register */ |
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72 | /* see section 3.8.2 of the SIM Reference Manual */ |
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73 | *PICR = (unsigned short int) |
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74 | ( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) ); |
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75 | /* ^^^ zero disables interrupt, don't enable here or ram_init will |
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76 | be wrong. It's enabled below. */ |
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77 | |
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78 | /* Periodic Interrupt Timer Register */ |
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79 | /* see section 3.8.3 of the SIM Reference Manual */ |
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80 | *PITR = (unsigned short int)( SAM(0x09,0,PITM) ); |
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81 | /* 1.098mS interrupt, assuming 32.768 KHz input clock */ |
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82 | |
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83 | /* Port C Data */ |
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84 | /* load values before enabled */ |
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85 | *PORTC = (unsigned char) 0x0; |
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86 | |
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87 | #if 0 |
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88 | /* Don't touch these on MRM, they are set up by CPU32bug at boot time. */ |
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89 | |
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90 | /* Chip-Select Base Address Register */ |
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91 | /* see section 7 of the SIM Reference Manual */ |
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92 | *CSBARBT = (unsigned short int) |
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93 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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94 | *CSBAR0 = (unsigned short int) |
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95 | (((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */ |
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96 | *CSBAR1 = (unsigned short int) |
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97 | (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ |
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98 | *CSBAR2 = (unsigned short int) |
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99 | (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ |
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100 | *CSBAR3 = (unsigned short int) |
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101 | (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */ |
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102 | *CSBAR4 = (unsigned short int) |
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103 | (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */ |
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104 | *CSBAR5 = (unsigned short int) |
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105 | (0xfff8 | BS_64K); /* AVEC interrupts */ |
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106 | |
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107 | #if 0 |
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108 | #ifdef EFI332_v040b |
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109 | *CSBAR6 = (unsigned short int) |
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110 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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111 | *CSBAR8 = (unsigned short int) /* PCMCIA IOCS */ |
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112 | (((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */ |
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113 | *CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */ |
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114 | (((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */ |
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115 | #else /* EFI332_v040b */ |
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116 | *CSBAR10 = (unsigned short int) |
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117 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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118 | #endif /* EFI332_v040b */ |
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119 | #endif |
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120 | |
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121 | /* Chip-Select Options Registers */ |
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122 | /* see section 7 of the SIM Reference Manual */ |
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123 | #ifdef FLASHWRITE |
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124 | *CSORBT = (unsigned short int) |
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125 | ( BothBytes | ReadWrite | SyncAS | WaitStates_0 | UserSupSpace ); |
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126 | #else /* FLASHWRITE */ |
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127 | *CSORBT = (unsigned short int) |
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128 | ( BothBytes | ReadOnly | SyncAS | WaitStates_0 | UserSupSpace ); |
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129 | #endif /* FLASHWRITE */ |
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130 | *CSOR0 = (unsigned short int) |
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131 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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132 | *CSOR1 = (unsigned short int) |
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133 | ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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134 | *CSOR2 = (unsigned short int) |
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135 | ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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136 | *CSOR3 = (unsigned short int) |
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137 | ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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138 | *CSOR4 = (unsigned short int) |
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139 | ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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140 | *CSOR5 = (unsigned short int) |
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141 | ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC ); |
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142 | |
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143 | #if 0 |
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144 | #ifdef EFI332_v040b |
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145 | *CSOR6 = (unsigned short int) |
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146 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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147 | *CSOR8 = (unsigned short int) |
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148 | ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); |
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149 | *CSOR9 = (unsigned short int) |
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150 | ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); |
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151 | #else /* EFI332_v040b */ |
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152 | *CSOR10 = (unsigned short int) |
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153 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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154 | #endif /* EFI332_v040b */ |
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155 | #endif |
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156 | |
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157 | /* Chip Select Pin Assignment Register 0 */ |
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158 | /* see section 7 of the SIM Reference Manual */ |
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159 | *CSPAR0 = (unsigned short int)( |
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160 | SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */ |
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161 | SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */ |
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162 | SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */ |
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163 | SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */ |
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164 | SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */ |
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165 | SAM(CS16bit,CS_0,0x000c)| /* W/!R */ |
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166 | SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */ |
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167 | ); |
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168 | |
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169 | /* Chip Select Pin Assignment Register 1 */ |
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170 | /* see section 7 of the SIM Reference Manual */ |
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171 | #ifdef EFI332_v040b |
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172 | *CSPAR1 = (unsigned short int)( |
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173 | SAM(DisOut,CS_10,0x300)| /* ECLK */ |
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174 | SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */ |
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175 | SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */ |
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176 | SAM(DisOut,CS_7,0x00c) | /* PC4 */ |
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177 | SAM(CS16bit,CS_6,0x003) /* ROM !OE */ |
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178 | ); |
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179 | #else /* EFI332_v040b */ |
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180 | *CSPAR1 = (unsigned short int)( |
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181 | SAM(CS16bit,CS_10,0x300)| /* ROM !OE */ |
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182 | SAM(DisOut,CS_9,0x0c0) | /* PC6 */ |
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183 | SAM(DisOut,CS_8,0x030) | /* PC5 */ |
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184 | SAM(DisOut,CS_7,0x00c) | /* PC4 */ |
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185 | SAM(DisOut,CS_6,0x003) /* PC3 */ |
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186 | ); |
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187 | #endif /* EFI332_v040b */ |
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188 | |
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189 | #endif /* Don't touch on MRM */ |
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190 | |
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191 | /* Port E and F Data Register */ |
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192 | /* see section 9 of the SIM Reference Manual */ |
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193 | *PORTE0 = (unsigned char) 0; |
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194 | *PORTF0 = (unsigned char) 0; |
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195 | |
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196 | /* Port E and F Data Direction Register */ |
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197 | /* see section 9 of the SIM Reference Manual */ |
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198 | *DDRE = (unsigned char) 0xff; |
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199 | *DDRF = (unsigned char) 0xfd; |
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200 | |
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201 | /* Port E and F Pin Assignment Register */ |
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202 | /* see section 9 of the SIM Reference Manual */ |
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203 | *PEPAR = (unsigned char) 0; |
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204 | *PFPAR = (unsigned char) 0; |
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205 | |
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206 | /* end of SIM initalization code */ |
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207 | /* end include in ram_init.S */ |
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208 | |
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209 | /* |
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210 | * Initialize RAM by copying the .data section out of ROM (if |
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211 | * needed) and "zero-ing" the .bss section. |
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212 | */ |
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213 | { |
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214 | register char *src = _etext; |
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215 | register char *dst = _copy_start; |
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216 | |
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217 | if (_copy_data_from_rom) |
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218 | /* ROM has data at end of text; copy it. */ |
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219 | while (dst < _edata) |
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220 | *dst++ = *src++; |
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221 | |
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222 | /* Zero bss */ |
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223 | for (dst = _clear_start; dst< end; dst++) |
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224 | { |
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225 | *dst = 0; |
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226 | } |
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227 | } |
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228 | |
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229 | /* |
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230 | * Initialize vector table. |
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231 | */ |
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232 | { |
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233 | m68k_isr_entry *monitors_vector_table; |
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234 | |
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235 | m68k_get_vbr(monitors_vector_table); |
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236 | |
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237 | M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */ |
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238 | M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */ |
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239 | M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */ |
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240 | M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */ |
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241 | M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */ |
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242 | |
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243 | m68k_set_vbr(&M68Kvec); |
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244 | } |
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245 | |
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246 | /* |
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247 | * Initalize the board. |
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248 | */ |
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249 | Spurious_Initialize(); |
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250 | console_init(); |
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251 | |
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252 | /* |
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253 | * Execute main with arguments argc and agrv. |
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254 | */ |
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255 | boot_card(1,__argv); |
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256 | reboot(); |
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257 | |
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258 | } |
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259 | |
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