source: rtems/c/src/lib/libbsp/m68k/mrm332/start/start.S @ 70f5ab38

4.115
Last change on this file since 70f5ab38 was 70f5ab38, checked in by Joel Sherrill <joel.sherrill@…>, on 05/02/12 at 19:12:57

MRM332 - Remove incorrect $Id$ string and correct file header

  • Property mode set to 100644
File size: 3.9 KB
RevLine 
[70f5ab38]1/**
2 *  @file
3 *
4 *  MRM332 Assembly Start Up Code
5 */
6
[274fa77]7/*
[70f5ab38]8 *  COPYRIGHT (c) 2000.
9 *  Matt Cross <profesor@gweep.net>
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
[274fa77]15 */
16
17#include "mrm332.h"
[cb33a86f]18#include <rtems/asm.h>
[e2d51fc4]19#include <rtems/m68k/sim.h>
[274fa77]20
21BEGIN_CODE
22
23  /* Put the header necessary for the modified CPU32bug to automatically
24     start up rtems: */
25#if 0
26.long 0xbeefbeef ;
27#endif
28.long 0 ;
29.long start ;
30
31.global start
32        start:
33
34        oriw   #0x0700,sr
35        movel  #end, d0
36        addl   #_StackSize,d0
37        movel  d0,sp
38        movel  d0,a6
39
40  /* include in ram_init.S */
41  /*
42   * Initalize the SIM module.
43   * The stack pointer is not usable until the RAM chip select lines
44   * are configured. The following code must remain inline.
45   */
46
47  /* Module Configuration Register */
48  /*    see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
49        lea     SIMCR, a0
50        movew   #FRZSW,d0
51        oriw    #SAM(0,8,SHEN),d0
52        oriw    #(MM*SIM_MM),d0
53        oriw    #SAM(SIM_IARB,0,IARB),d0
54        movew   d0, a0@
55
56        jsr     start_c /* Jump to the C startup code */
57
58END_CODE
59
60#if 0
61
62  /* Synthesizer Control Register */
63  /*    see section(s) 4.8 */
64  /* end include in ram_init.S */
65  *SYNCR = (unsigned short int)
66    ( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
67  while (! (*SYNCR & SLOCK));   /* protect from clock overshoot */
68  /* include in ram_init.S */
69  *SYNCR = (unsigned short int)
70    ( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
71
72  /* System Protection Control Register */
73  /*    !!! can only write to once after reset !!! */
74  /*    see section 3.8.4 of the SIM Reference Manual */
75  *SYPCR = (unsigned char)( HME | BME );
76
77  /* Periodic Interrupr Control Register */
78  /*    see section 3.8.2 of the SIM Reference Manual */
79  *PICR = (unsigned short int)
80    ( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
81  /*     ^^^ zero disables interrupt, don't enable here or ram_init will
82         be wrong. It's enabled below. */
83
84  /* Periodic Interrupt Timer Register */
85  /*    see section 3.8.3 of the SIM Reference Manual */
86  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );
87  /*    1.098mS interrupt, assuming 32.768 KHz input clock */
88
89  /* Port C Data */
90  /*    load values before enabled */
91  *PORTC = (unsigned char) 0x0;
92
93  /* Port E and F Data Register */
94  /*    see section 9 of the SIM Reference Manual */
95  *PORTE0 = (unsigned char) 0;
96  *PORTF0 = (unsigned char) 0;
97
98  /* Port E and F Data Direction Register */
99  /*    see section 9 of the SIM Reference Manual */
100  *DDRE = (unsigned char) 0xff;
101  *DDRF = (unsigned char) 0xfd;
[6128a4a]102
[274fa77]103  /* Port E and F Pin Assignment Register */
104  /*    see section 9 of the SIM Reference Manual */
105  *PEPAR = (unsigned char) 0;
106  *PFPAR = (unsigned char) 0;
107
108  /* end of SIM initalization code */
109  /* end include in ram_init.S */
110
111  /*
112   * Initialize RAM by copying the .data section out of ROM (if
113   * needed) and "zero-ing" the .bss section.
114   */
115  {
116    register char *src = _etext;
117    register char *dst = _copy_start;
118
119    if (_copy_data_from_rom)
120      /* ROM has data at end of text; copy it. */
121      while (dst < _edata)
122        *dst++ = *src++;
[6128a4a]123
[274fa77]124    /* Zero bss */
125    for (dst = _clear_start; dst< end; dst++)
126      {
127        *dst = 0;
128      }
129  }
130
131  /*
132   * Initialize vector table.
133   */
134  {
[1fec9e0]135    rtems_isr_entry *monitors_vector_table;
[274fa77]136
137    m68k_get_vbr(monitors_vector_table);
138
139    M68Kvec[  4 ] = monitors_vector_table[  4 ];   /* breakpoints vector */
140    M68Kvec[  9 ] = monitors_vector_table[  9 ];   /* trace vector */
141    M68Kvec[ 31 ] = monitors_vector_table[ 31 ];   /* level 7 interrupt */
142    M68Kvec[ 47 ] = monitors_vector_table[ 47 ];   /* system call vector */
143    M68Kvec[ 66 ] = monitors_vector_table[ 66 ];   /* user defined */
[6128a4a]144
[274fa77]145    m68k_set_vbr(&M68Kvec);
146  }
147
148  /*
149   * Initalize the board.
150   */
151  Spurious_Initialize();
152  console_init();
153
154  /*
155   * Execute main with arguments argc and agrv.
156   */
[820d1ab0]157  boot_card((void*)0);
[274fa77]158  reboot();
159
160}
161
162#endif
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