[70f5ab38] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * MRM332 Assembly Start Up Code |
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| 5 | */ |
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| 6 | |
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[274fa77] | 7 | /* |
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[70f5ab38] | 8 | * COPYRIGHT (c) 2000. |
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| 9 | * Matt Cross <profesor@gweep.net> |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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| 13 | * http://www.rtems.com/license/LICENSE. |
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| 14 | * |
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[274fa77] | 15 | */ |
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| 16 | |
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| 17 | #include "mrm332.h" |
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[cb33a86f] | 18 | #include <rtems/asm.h> |
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[e2d51fc4] | 19 | #include <rtems/m68k/sim.h> |
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[274fa77] | 20 | |
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| 21 | BEGIN_CODE |
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| 22 | |
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| 23 | /* Put the header necessary for the modified CPU32bug to automatically |
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| 24 | start up rtems: */ |
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| 25 | #if 0 |
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| 26 | .long 0xbeefbeef ; |
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| 27 | #endif |
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| 28 | .long 0 ; |
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| 29 | .long start ; |
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| 30 | |
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| 31 | .global start |
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| 32 | start: |
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| 33 | |
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| 34 | oriw #0x0700,sr |
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| 35 | movel #end, d0 |
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| 36 | addl #_StackSize,d0 |
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| 37 | movel d0,sp |
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| 38 | movel d0,a6 |
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| 39 | |
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| 40 | /* include in ram_init.S */ |
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| 41 | /* |
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| 42 | * Initalize the SIM module. |
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| 43 | * The stack pointer is not usable until the RAM chip select lines |
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| 44 | * are configured. The following code must remain inline. |
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| 45 | */ |
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| 46 | |
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| 47 | /* Module Configuration Register */ |
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| 48 | /* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */ |
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| 49 | lea SIMCR, a0 |
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| 50 | movew #FRZSW,d0 |
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| 51 | oriw #SAM(0,8,SHEN),d0 |
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| 52 | oriw #(MM*SIM_MM),d0 |
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| 53 | oriw #SAM(SIM_IARB,0,IARB),d0 |
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| 54 | movew d0, a0@ |
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| 55 | |
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| 56 | jsr start_c /* Jump to the C startup code */ |
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| 57 | |
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| 58 | END_CODE |
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| 59 | |
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| 60 | #if 0 |
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| 61 | |
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| 62 | /* Synthesizer Control Register */ |
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| 63 | /* see section(s) 4.8 */ |
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| 64 | /* end include in ram_init.S */ |
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| 65 | *SYNCR = (unsigned short int) |
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| 66 | ( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) ); |
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| 67 | while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */ |
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| 68 | /* include in ram_init.S */ |
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| 69 | *SYNCR = (unsigned short int) |
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| 70 | ( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) ); |
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| 71 | |
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| 72 | /* System Protection Control Register */ |
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| 73 | /* !!! can only write to once after reset !!! */ |
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| 74 | /* see section 3.8.4 of the SIM Reference Manual */ |
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| 75 | *SYPCR = (unsigned char)( HME | BME ); |
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| 76 | |
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| 77 | /* Periodic Interrupr Control Register */ |
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| 78 | /* see section 3.8.2 of the SIM Reference Manual */ |
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| 79 | *PICR = (unsigned short int) |
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| 80 | ( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) ); |
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| 81 | /* ^^^ zero disables interrupt, don't enable here or ram_init will |
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| 82 | be wrong. It's enabled below. */ |
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| 83 | |
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| 84 | /* Periodic Interrupt Timer Register */ |
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| 85 | /* see section 3.8.3 of the SIM Reference Manual */ |
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| 86 | *PITR = (unsigned short int)( SAM(0x09,0,PITM) ); |
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| 87 | /* 1.098mS interrupt, assuming 32.768 KHz input clock */ |
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| 88 | |
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| 89 | /* Port C Data */ |
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| 90 | /* load values before enabled */ |
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| 91 | *PORTC = (unsigned char) 0x0; |
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| 92 | |
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| 93 | /* Port E and F Data Register */ |
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| 94 | /* see section 9 of the SIM Reference Manual */ |
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| 95 | *PORTE0 = (unsigned char) 0; |
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| 96 | *PORTF0 = (unsigned char) 0; |
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| 97 | |
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| 98 | /* Port E and F Data Direction Register */ |
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| 99 | /* see section 9 of the SIM Reference Manual */ |
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| 100 | *DDRE = (unsigned char) 0xff; |
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| 101 | *DDRF = (unsigned char) 0xfd; |
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[6128a4a] | 102 | |
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[274fa77] | 103 | /* Port E and F Pin Assignment Register */ |
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| 104 | /* see section 9 of the SIM Reference Manual */ |
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| 105 | *PEPAR = (unsigned char) 0; |
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| 106 | *PFPAR = (unsigned char) 0; |
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| 107 | |
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| 108 | /* end of SIM initalization code */ |
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| 109 | /* end include in ram_init.S */ |
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| 110 | |
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| 111 | /* |
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| 112 | * Initialize RAM by copying the .data section out of ROM (if |
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| 113 | * needed) and "zero-ing" the .bss section. |
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| 114 | */ |
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| 115 | { |
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| 116 | register char *src = _etext; |
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| 117 | register char *dst = _copy_start; |
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| 118 | |
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| 119 | if (_copy_data_from_rom) |
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| 120 | /* ROM has data at end of text; copy it. */ |
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| 121 | while (dst < _edata) |
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| 122 | *dst++ = *src++; |
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[6128a4a] | 123 | |
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[274fa77] | 124 | /* Zero bss */ |
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| 125 | for (dst = _clear_start; dst< end; dst++) |
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| 126 | { |
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| 127 | *dst = 0; |
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| 128 | } |
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| 129 | } |
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| 130 | |
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| 131 | /* |
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| 132 | * Initialize vector table. |
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| 133 | */ |
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| 134 | { |
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[1fec9e0] | 135 | rtems_isr_entry *monitors_vector_table; |
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[274fa77] | 136 | |
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| 137 | m68k_get_vbr(monitors_vector_table); |
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| 138 | |
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| 139 | M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */ |
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| 140 | M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */ |
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| 141 | M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */ |
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| 142 | M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */ |
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| 143 | M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */ |
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[6128a4a] | 144 | |
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[274fa77] | 145 | m68k_set_vbr(&M68Kvec); |
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| 146 | } |
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| 147 | |
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| 148 | /* |
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| 149 | * Initalize the board. |
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| 150 | */ |
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| 151 | Spurious_Initialize(); |
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| 152 | console_init(); |
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| 153 | |
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| 154 | /* |
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| 155 | * Execute main with arguments argc and agrv. |
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| 156 | */ |
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[820d1ab0] | 157 | boot_card((void*)0); |
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[274fa77] | 158 | reboot(); |
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| 159 | |
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| 160 | } |
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| 161 | |
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| 162 | #endif |
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