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source: rtems/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c @ d4b4664b

4.104.115

Last change on this file since d4b4664b was d4b4664b, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/29/09 at 14:59:41
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1
2	/*********************************************************************
3	* Initialisation Code for ColdFire MCF5329 Processor *
4	**********************************************************************
5	Generated by ColdFire Initialisation Utility 2.10.8
6	Wed Jul 02 14:26:25 2008
7
8	MicroAPL Ltd makes no warranties in respect of the suitability
9	of this code for any particular purpose, and accepts
10	no liability for any loss arising out of its use. The person or
11	persons making use of this file must make the final evaluation
12	as to its suitability and correctness for a particular application.
13
14	$Id$
15
16	*/
17
18	/* External reference frequency is 16.0000 MHz
19	Internal bus clock frequency = 80.00 MHz
20	Processor core frequency = 240.00 MHz
21	*/
22
23	#include <bsp.h>
24
25	/* eDMA Transfer Control Descriptor definitions */
26	#define MCF_EDMA_TCD_W0(channel) ((vuint32 )(0xFC045000+((channel)0x20))) / Transfer Control Descriptor Word 0 */
27	#define MCF_EDMA_TCD_W1(channel) ((vuint32 )(0xFC045004+((channel)0x20))) / Transfer Control Descriptor Word 1 */
28	#define MCF_EDMA_TCD_W2(channel) ((vuint32 )(0xFC045008+((channel)0x20))) / Transfer Control Descriptor Word 2 */
29	#define MCF_EDMA_TCD_W3(channel) ((vuint32 )(0xFC04500C+((channel)0x20))) / Transfer Control Descriptor Word 3 */
30	#define MCF_EDMA_TCD_W4(channel) ((vuint32 )(0xFC045010+((channel)0x20))) / Transfer Control Descriptor Word 4 */
31	#define MCF_EDMA_TCD_W5(channel) ((vuint32 )(0xFC045014+((channel)0x20))) / Transfer Control Descriptor Word 5 */
32	#define MCF_EDMA_TCD_W6(channel) ((vuint32 )(0xFC045018+((channel)0x20))) / Transfer Control Descriptor Word 6 */
33	#define MCF_EDMA_TCD_W7(channel) ((vuint32 )(0xFC04501C+((channel)0x20))) / Transfer Control Descriptor Word 7 */
34
35	/* Function prototypes */
36	void init_main(void);
37	static void disable_interrupts(void);
38	static void disable_watchdog_timer(void);
39	static void disable_cache(void);
40	extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
41	static void init_cache(void);
42	static void init_crossbar(void);
43	extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
44	static void init_eport(void);
45	static void init_flexcan(void);
46	static void init_dma_timers(void);
47	static void init_interrupt_timers(void);
48	static void init_real_time_clock(void);
49	static void init_watchdog_timers(void);
50	static void init_edma(void);
51	static void init_pin_assignments(void);
52	extern void init_sdram_controller(void)
53	__attribute__ ((section(".ram_code")));
54	static void init_interrupt_controller(void);
55
56	/*********************************************************************
57	* init_main - Main entry point for initialisation code *
58	**********************************************************************/
59	void init_main(void)
60	{
61	init_clock_config();
62
63	/* Disable interrupts, watchdog timer, cache */
64	disable_interrupts();
65	disable_watchdog_timer();
66	disable_cache();
67
68	/* Initialise individual modules */
69	init_cache();
70	init_crossbar();
71	init_chip_selects();
72	init_eport();
73	init_flexcan();
74	init_dma_timers();
75	init_interrupt_timers();
76	init_real_time_clock();
77	init_watchdog_timers();
78	init_edma();
79	init_pin_assignments();
80
81	/* Initialise SDRAM controller (must be done after pin assignments) */
82	init_sdram_controller();
83
84	/* Initialise interrupt controller */
85	init_interrupt_controller();
86	}
87
88	/*********************************************************************
89	* disable_interrupts - Disable all interrupt sources *
90	**********************************************************************/
91	static void disable_interrupts(void)
92	{
93	vuint8 *p;
94	int i;
95
96	/* Set ICR001-ICR063 to 0x0 */
97	p = (vuint8 *) & MCF_INTC0_ICR1;
98	for (i = 1; i <= 63; i++)
99	*p++ = 0x0;
100
101	/* Set ICR100-ICR163 to 0x0 */
102	p = (vuint8 *) & MCF_INTC1_ICR0;
103	for (i = 100; i <= 163; i++)
104	*p++ = 0x0;
105	}
106
107	/*********************************************************************
108	* disable_watchdog_timer - Disable system watchdog timer *
109	**********************************************************************/
110	static void disable_watchdog_timer(void)
111	{
112	/* Disable Core Watchdog Timer */
113	MCF_SCM_CWCR = 0;
114	}
115
116	/*********************************************************************
117	* disable_cache - Disable and invalidate cache *
118	**********************************************************************/
119	static void disable_cache(void)
120	{
121	asm("move.l #0x01000000,%d0");
122	asm("movec %d0,%CACR");
123	}
124
125	/*********************************************************************
126	* init_clock_config - Clock Module *
127	**********************************************************************/
128	void init_clock_config(void)
129	{
130	/* Clock module uses normal PLL mode with 16.0000 MHz external reference
131	Bus clock frequency = 80.00 MHz
132	Processor clock frequency = 3 x bus clock = 240.00 MHz
133	Dithering disabled
134	*/
135
136	/* Check to see if the SDRAM has already been initialized
137	by a run control tool. If it has, put SDRAM into self-refresh mode before
138	initializing the PLL
139	*/
140	if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
141	MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
142
143	/* Temporarily switch to LIMP mode
144	NOTE: Ensure that this code is not executing from SDRAM, since the
145	SDRAM Controller is disabled in LIMP mode
146	*/
147	MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) \| MCF_CCM_CDR_LPDIV(0x2);
148	MCF_CCM_MISCCR \|= MCF_CCM_MISCCR_LIMP;
149
150	/* Configure the PLL settings */
151	MCF_PLL_PODR = MCF_PLL_PODR_CPUDIV(0x2) \| MCF_PLL_PODR_BUSDIV(0x6);
152	MCF_PLL_PFDR = MCF_PLL_PFDR_MFD(0x78);
153	MCF_PLL_PLLCR = 0;
154	MCF_PLL_PMDR = 0;
155
156	/* Enable PLL and wait for lock */
157	MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP;
158	while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
159
160	/* From the Device Errata:
161
162	"After exiting LIMP mode, the value of 0x40000000 should be written
163	to address 0xFC0B8080 before attempting to initialize the SDRAMC
164	or exit the SDRAM from self-refresh mode."
165	*/
166	(vuint32 ) 0xfc0b8080 = 0x40000000;
167
168	/* If we put the SDRAM into self-refresh mode earlier, restore mode now */
169	if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
170	MCF_SDRAMC_SDCR \|= MCF_SDRAMC_SDCR_CKE;
171	}
172
173	/*********************************************************************
174	* init_cache - Unified (Instruction and Data) Cache *
175	**********************************************************************/
176	static void init_cache(void)
177	{
178	/* ACR0: Cache accesses to 32 MB memory region at address $40000000
179	CACR: Don't cache accesses to the rest of memory
180	*/
181	/*
182	* Cache is enabled in bspstart.c
183	*/
184	#if 0
185	asm("move.l #0xa0000600,%d0");
186	asm("movec %d0,%CACR");
187	#endif
188	asm("move.l #0x4001c020,%d0");
189	asm("movec %d0,%ACR0");
190	asm("move.l #0x00000000,%d0");
191	asm("movec %d0,%ACR1");
192	}
193
194	/*********************************************************************
195	* init_crossbar - Cross-Bar Switch (XBS) Module *
196	**********************************************************************/
197	static void init_crossbar(void)
198	{
199	/* XBS settings for FlexBus/SDRAM Controller slave:
200	Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
201	*/
202	MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) \|
203	MCF_XBS_PRS_M5(0x4) \|
204	MCF_XBS_PRS_M4(0x1) \| MCF_XBS_PRS_M2(0x3) \| MCF_XBS_PRS_M1(0x2);
205	MCF_XBS_CRS1 = 0;
206
207	/* XBS settings for SRAM Backdoor slave:
208	Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
209	*/
210	MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) \|
211	MCF_XBS_PRS_M5(0x4) \|
212	MCF_XBS_PRS_M4(0x3) \| MCF_XBS_PRS_M2(0x2) \| MCF_XBS_PRS_M1(0x1);
213	MCF_XBS_CRS4 = 0;
214
215	/* XBS settings for Cryptography Modules slave:
216	Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
217	*/
218	MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) \|
219	MCF_XBS_PRS_M5(0x4) \|
220	MCF_XBS_PRS_M4(0x3) \| MCF_XBS_PRS_M2(0x2) \| MCF_XBS_PRS_M1(0x1);
221	MCF_XBS_CRS6 = 0;
222
223	/* XBS settings for On-chip Peripherals slave:
224	Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
225	*/
226	MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) \|
227	MCF_XBS_PRS_M5(0x4) \|
228	MCF_XBS_PRS_M4(0x3) \| MCF_XBS_PRS_M2(0x2) \| MCF_XBS_PRS_M1(0x1);
229	MCF_XBS_CRS7 = 0;
230	}
231
232	/*********************************************************************
233	* init_chip_selects - Chip Select Module (FlexBus) *
234	**********************************************************************/
235	void init_chip_selects(void)
236	{
237	/* Chip Select 1 disabled (CSMR1[V] = 0) */
238	MCF_FBCS1_CSMR = 0;
239
240	/* Chip Select 2 disabled (CSMR2[V] = 0) */
241	MCF_FBCS2_CSMR = 0;
242
243	/* Chip Select 3 disabled (CSMR3[V] = 0) */
244	MCF_FBCS3_CSMR = 0;
245
246	/* Chip Select 4 disabled (CSMR4[V] = 0) */
247	MCF_FBCS4_CSMR = 0;
248
249	/* Chip Select 5 disabled (CSMR5[V] = 0) */
250	MCF_FBCS5_CSMR = 0;
251
252	/* Chip Select 0: 2 MB of Flash at base address $00000000
253	Port size = 16 bits
254	Assert chip select on first rising clock edge after address is asserted
255	Generate internal transfer acknowledge after 7 wait states
256	Address is held for 1 clock at end of read and write cycles
257	*/
258	MCF_FBCS0_CSAR = 0;
259	MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) \|
260	(0x1 << 9) \| MCF_FBCS_CSCR_AA \| MCF_FBCS_CSCR_PS(0x2) \| MCF_FBCS_CSCR_BEM;
261	MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) \| MCF_FBCS_CSMR_V;
262	}
263
264	/*********************************************************************
265	* init_eport - Edge Port Module (EPORT) *
266	**********************************************************************/
267	static void init_eport(void)
268	{
269	/* Pins 1-7 configured as GPIO inputs */
270	MCF_EPORT_EPPAR = 0;
271	MCF_EPORT_EPDDR = 0;
272	MCF_EPORT_EPIER = 0;
273	}
274
275	/*********************************************************************
276	* init_flexcan - FlexCAN Module *
277	**********************************************************************/
278	static void init_flexcan(void)
279	{
280	/* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
281	MCF_CAN_IMASK = 0;
282	MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
283	MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
284	MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
285	MCF_CAN_CANCTRL = 0;
286	MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS \|
287	MCF_CAN_CANMCR_FRZ \|
288	MCF_CAN_CANMCR_HALT \| MCF_CAN_CANMCR_SUPV \| MCF_CAN_CANMCR_MAXMB(0xf);
289	}
290
291	/*********************************************************************
292	* init_sdram_controller - SDRAM Controller *
293	**********************************************************************/
294	void init_sdram_controller(void)
295	{
296	/* Check to see if the SDRAM has already been initialized
297	by a run control tool and skip if so
298	*/
299	if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
300	return;
301
302	/* Ensure that there is a delay from processor reset of the time recommended in
303	the SDRAM data sheet (typically 100-200 microseconds) until the following
304	code so that the SDRAM is ready for commands...
305	*/
306
307	/* SDRAM controller configured for Double-data rate (DDR) SDRAM
308	Bus width = 16 bits
309	SDRAM specification:
310	SDRAM clock frequency = 80.00 MHz
311	CASL = 2.5
312	ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
313	Write recovery time, tWR = 15.0 nanoseconds
314	Precharge comand to ACTV command, tRP = 20.0 nanoseconds
315	Auto refresh command period, tRFC = 75.0 nanoseconds
316	Average periodic refresh interval, tREFI = 7.8 microseconds
317	*/
318
319	/* Memory block 0 enabled - 32 MBytes at address $40000000
320	Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
321	*/
322	MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) \| MCF_SDRAMC_SDCS_CSSZ(0x18);
323
324	/* Memory block 1 disabled */
325	MCF_SDRAMC_SDCS1 = 0;
326
327	/* Initialise SDCFG1 register with delay and timing values
328	SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
329	PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
330	*/
331	MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) \|
332	MCF_SDRAMC_SDCFG1_SWT2RD(0x3) \|
333	MCF_SDRAMC_SDCFG1_RDLAT(0x7) \|
334	MCF_SDRAMC_SDCFG1_ACT2RW(0x2) \|
335	MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) \|
336	MCF_SDRAMC_SDCFG1_REF2ACT(0x6) \| MCF_SDRAMC_SDCFG1_WTLAT(0x3);
337
338	/* Initialise SDCFG2 register with delay and timing values
339	BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
340	*/
341	MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) \|
342	MCF_SDRAMC_SDCFG2_BWT2RW(0x6) \|
343	MCF_SDRAMC_SDCFG2_BRD2WT(0x6) \| MCF_SDRAMC_SDCFG2_BL(0x7);
344
345	/* Issue a Precharge All command */
346	MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_MODE_EN \|
347	MCF_SDRAMC_SDCR_CKE \|
348	MCF_SDRAMC_SDCR_DDR \|
349	MCF_SDRAMC_SDCR_MUX(0x1) \|
350	MCF_SDRAMC_SDCR_RCNT(0x8) \| MCF_SDRAMC_SDCR_PS_16 \| MCF_SDRAMC_SDCR_IPALL;
351
352	/* Write Extended Mode Register */
353	MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LEMR \| MCF_SDRAMC_SDMR_CMD;
354
355	/* Write Mode Register and Reset DLL */
356	MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR \|
357	MCF_SDRAMC_SDMR_AD(0x163) \| MCF_SDRAMC_SDMR_CMD;
358
359	/* Insert code here to pause for DLL lock time specified by memory... */
360
361	/* Issue a second Precharge All command */
362	MCF_SDRAMC_SDCR \|= MCF_SDRAMC_SDCR_IPALL;
363
364	/* Refresh sequence...
365	(check the number of refreshes required by the SDRAM manufacturer)
366	*/
367	MCF_SDRAMC_SDCR \|= MCF_SDRAMC_SDCR_IREF;
368	MCF_SDRAMC_SDCR \|= MCF_SDRAMC_SDCR_IREF;
369
370	/* Write Mode Register and clear the Reset DLL bit */
371	MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR \|
372	MCF_SDRAMC_SDMR_AD(0x63) \| MCF_SDRAMC_SDMR_CMD;
373
374	/* Enable automatic refresh and lock SDMR */
375	MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
376	MCF_SDRAMC_SDCR \|= MCF_SDRAMC_SDCR_REF \|
377	MCF_SDRAMC_SDCR_DQS_OE(0x8) \| MCF_SDRAMC_SDCR_DQS_OE(0x4);
378
379	}
380
381	/*********************************************************************
382	* init_dma_timers - DMA Timers *
383	**********************************************************************/
384	static void init_dma_timers(void)
385	{
386	/* DMA Timer 0 disabled (DTMR0[RST] = 0) */
387	MCF_DTIM0_DTMR = 0;
388	MCF_DTIM0_DTXMR = 0;
389	MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
390
391	/* DMA Timer 1 disabled (DTMR1[RST] = 0) */
392	MCF_DTIM1_DTMR = 0;
393	MCF_DTIM1_DTXMR = 0;
394	MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
395
396	/* DMA Timer 2 disabled (DTMR2[RST] = 0) */
397	MCF_DTIM2_DTMR = 0;
398	MCF_DTIM2_DTXMR = 0;
399	MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
400
401	/* DMA Timer 3 disabled (DTMR3[RST] = 0) */
402	MCF_DTIM3_DTMR = 0;
403	MCF_DTIM3_DTXMR = 0;
404	MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
405	}
406
407	/*********************************************************************
408	* init_interrupt_timers - Programmable Interrupt Timers (PIT) *
409	**********************************************************************/
410	static void init_interrupt_timers(void)
411	{
412	/* PIT0 disabled (PCSR0[EN]=0) */
413	MCF_PIT0_PCSR = 0;
414
415	/* PIT1 disabled (PCSR1[EN]=0) */
416	MCF_PIT1_PCSR = 0;
417
418	/* PIT2 disabled (PCSR2[EN]=0) */
419	MCF_PIT2_PCSR = 0;
420
421	/* PIT3 disabled (PCSR3[EN]=0) */
422	MCF_PIT3_PCSR = 0;
423	}
424
425	/*********************************************************************
426	* init_real_time_clock - Real-Time Clock (RTC) *
427	**********************************************************************/
428	static void init_real_time_clock(void)
429	{
430	/* Disable the RTC */
431	MCF_RTC_CR = 0;
432	}
433
434	/*********************************************************************
435	* init_watchdog_timers - Watchdog Timers *
436	**********************************************************************/
437	static void init_watchdog_timers(void)
438	{
439	/* Watchdog Timer disabled (WCR[EN]=0)
440	NOTE: WCR and WMR cannot be written again until after the
441	processor is reset.
442	*/
443	MCF_WTM_WCR = MCF_WTM_WCR_WAIT \| MCF_WTM_WCR_DOZE \| MCF_WTM_WCR_HALTED;
444	MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
445
446	/* Core watchdog timer disabled */
447	MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
448	}
449
450	/*********************************************************************
451	* init_edma - eDMA Controller *
452	**********************************************************************/
453	static void init_edma(void)
454	{
455	/* Associate eDMA channels 9-12 with SSI signals */
456	MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA;
457
458	/* Configured for round-robin arbitration mode */
459	MCF_EDMA_CR = MCF_EDMA_CR_ERCA;
460
461	/* All error interrupts are disabled */
462	MCF_EDMA_EEI = 0;
463
464	/* All DMA requests from peripherals are masked */
465	MCF_EDMA_ERQ = 0;
466	}
467
468	/*********************************************************************
469	* init_interrupt_controller - Interrupt Controller *
470	**********************************************************************/
471	static void init_interrupt_controller(void)
472	{
473	/* No interrupt sources configured */
474	MCF_INTC1_ICR0 = 0;
475	MCF_INTC1_ICR1 = 0;
476	MCF_INTC1_ICR3 = 0;
477	MCF_INTC1_ICR4 = 0;
478	MCF_INTC1_ICR5 = 0;
479	MCF_INTC1_ICR6 = 0;
480	MCF_INTC1_ICR7 = 0;
481	MCF_INTC1_ICR8 = 0;
482	MCF_INTC1_ICR9 = 0;
483	MCF_INTC1_ICR10 = 0;
484	MCF_INTC1_ICR11 = 0;
485	MCF_INTC1_ICR12 = 0;
486	MCF_INTC1_ICR13 = 0;
487	MCF_INTC1_ICR14 = 0;
488	MCF_INTC1_ICR15 = 0;
489	MCF_INTC1_ICR16 = 0;
490	MCF_INTC1_ICR17 = 0;
491	MCF_INTC1_ICR18 = 0;
492	MCF_INTC1_ICR19 = 0;
493	MCF_INTC1_ICR40 = 0;
494	MCF_INTC1_ICR41 = 0;
495	MCF_INTC1_ICR42 = 0;
496	MCF_INTC1_ICR43 = 0;
497	MCF_INTC1_ICR44 = 0;
498	MCF_INTC1_ICR45 = 0;
499	MCF_INTC1_ICR46 = 0;
500	MCF_INTC1_ICR47 = 0;
501	MCF_INTC1_ICR48 = 0;
502	MCF_INTC1_ICR49 = 0;
503	MCF_INTC1_ICR50 = 0;
504	MCF_INTC1_ICR51 = 0;
505	MCF_INTC1_ICR52 = 0;
506	MCF_INTC1_ICR53 = 0;
507	MCF_INTC0_ICR1 = 0;
508	MCF_INTC0_ICR2 = 0;
509	MCF_INTC0_ICR3 = 0;
510	MCF_INTC0_ICR4 = 0;
511	MCF_INTC0_ICR5 = 0;
512	MCF_INTC0_ICR6 = 0;
513	MCF_INTC0_ICR7 = 0;
514	MCF_INTC0_ICR8 = 0;
515	MCF_INTC0_ICR9 = 0;
516	MCF_INTC0_ICR10 = 0;
517	MCF_INTC0_ICR11 = 0;
518	MCF_INTC0_ICR12 = 0;
519	MCF_INTC0_ICR13 = 0;
520	MCF_INTC0_ICR14 = 0;
521	MCF_INTC0_ICR15 = 0;
522	MCF_INTC0_ICR16 = 0;
523	MCF_INTC0_ICR17 = 0;
524	MCF_INTC0_ICR18 = 0;
525	MCF_INTC0_ICR19 = 0;
526	MCF_INTC0_ICR20 = 0;
527	MCF_INTC0_ICR21 = 0;
528	MCF_INTC0_ICR22 = 0;
529	MCF_INTC0_ICR23 = 0;
530	MCF_INTC0_ICR24 = 0;
531	MCF_INTC0_ICR25 = 0;
532	MCF_INTC0_ICR26 = 0;
533	MCF_INTC0_ICR27 = 0;
534	MCF_INTC0_ICR28 = 0;
535	MCF_INTC0_ICR30 = 0;
536	MCF_INTC0_ICR31 = 0;
537	MCF_INTC0_ICR32 = 0;
538	MCF_INTC0_ICR33 = 0;
539	MCF_INTC0_ICR34 = 0;
540	MCF_INTC0_ICR35 = 0;
541	MCF_INTC0_ICR36 = 0;
542	MCF_INTC0_ICR37 = 0;
543	MCF_INTC0_ICR38 = 0;
544	MCF_INTC0_ICR39 = 0;
545	MCF_INTC0_ICR40 = 0;
546	MCF_INTC0_ICR41 = 0;
547	MCF_INTC0_ICR42 = 0;
548	MCF_INTC0_ICR43 = 0;
549	MCF_INTC0_ICR44 = 0;
550	MCF_INTC0_ICR45 = 0;
551	MCF_INTC0_ICR46 = 0;
552	MCF_INTC0_ICR47 = 0;
553	MCF_INTC0_ICR48 = 0;
554	MCF_INTC0_ICR62 = 0;
555	MCF_INTC0_IMRH = 0xffffffff;
556	MCF_INTC0_IMRL = 0xffffffff;
557	MCF_INTC1_IMRH = 0xffffffff;
558	MCF_INTC1_IMRL = 0xffffffff;
559	}
560
561	/*********************************************************************
562	* init_pin_assignments - Pin Assignment and General Purpose I/O *
563	**********************************************************************/
564	static void init_pin_assignments(void)
565	{
566	/* Pin assignments for port BUSCTL
567	Pin BUSCTL3 : External bus output enable, /OE
568	Pin BUSCTL2 : External bus transfer acknowledge, /TA
569	Pin BUSCTL1 : External bus read/write, R/W
570	Pin BUSCTL0 : External bus transfer start, /TS
571	*/
572	MCF_GPIO_PDDR_BUSCTL = 0;
573	MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE \|
574	MCF_GPIO_PAR_BUSCTL_PAR_TA \|
575	MCF_GPIO_PAR_BUSCTL_PAR_RWB \| MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
576
577	/* Pin assignments for port BE
578	Pin BE3 : External bus byte enable BW/BWE3
579	Pin BE2 : External bus byte enable BW/BWE2
580	Pin BE1 : External bus byte enable BW/BWE1
581	Pin BE0 : External bus byte enable BW/BWE0
582	*/
583	MCF_GPIO_PDDR_BE = 0;
584	MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 \|
585	MCF_GPIO_PAR_BE_PAR_BE2 \|
586	MCF_GPIO_PAR_BE_PAR_BE1 \| MCF_GPIO_PAR_BE_PAR_BE0;
587
588	/* Pin assignments for port CS
589	Pin CS5 : Flex bus chip select /FB_CS5
590	Pin CS4 : Flex bus chip select /FB_CS4
591	Pin CS3 : Flex bus chip select /FB_CS3
592	Pin CS2 : Flex bus chip select /FB_CS2
593	Pin CS1 : Flex bus chip select /FB_CS1
594	*/
595	MCF_GPIO_PDDR_CS = 0;
596	MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 \|
597	MCF_GPIO_PAR_CS_PAR_CS4 \|
598	MCF_GPIO_PAR_CS_PAR_CS3 \|
599	MCF_GPIO_PAR_CS_PAR_CS2 \| MCF_GPIO_PAR_CS_PAR_CS1;
600
601	/* Pin assignments for port FECI2C
602	Pin FECI2C3 : FEC management data clock, FEC_MDC
603	Pin FECI2C2 : FEC management data, FEC_MDIO
604	Pin FECI2C1 : GPIO input
605	Pin FECI2C0 : GPIO input
606	*/
607	MCF_GPIO_PDDR_FECI2C = 0;
608	MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) \|
609	MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
610
611	/* Pin assignments for ports FECH and FECL
612	Pin FECH7 : FEC transmit clock, FEC_TXCLK
613	Pin FECH6 : FEC transmit enable, FEC_TXEN
614	Pin FECH5 : FEC transmit data 0, FEC_TXD0
615	Pin FECH4 : FEC collision, FEC_COL
616	Pin FECH3 : FEC receive clock, FEC_RXCLK
617	Pin FECH2 : FEC receive data valid, FEC_RXDV
618	Pin FECH1 : FEC receive data 0, FEC_RXD0
619	Pin FECH0 : FEC carrier receive sense, FEC_CRS
620	Pin FECL7 : FEC transmit data 3, FEC_TXD3
621	Pin FECL6 : FEC transmit data 2, FEC_TXD2
622	Pin FECL5 : FEC transmit data 1, FEC_TXD1
623	Pin FECL4 : FEC transmit error, FEC_TXER
624	Pin FECL3 : FEC receive data 3, FEX_RXD3
625	Pin FECL2 : FEC receive data 2, FEX_RXD2
626	Pin FECL1 : FEC receive data 1, FEX_RXD1
627	Pin FECL0 : FEC receive error, FEC_RXER
628	*/
629	MCF_GPIO_PDDR_FECH = 0;
630	MCF_GPIO_PDDR_FECL = 0;
631	MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) \|
632	MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
633
634	/* Pin assignments for port IRQ
635	Pins are all used for EdgePort GPIO/IRQ
636	*/
637	MCF_GPIO_PAR_IRQ = 0;
638
639	/* Pin assignments for port LCDDATAH
640	Pins are all GPIO inputs
641	*/
642	MCF_GPIO_PDDR_LCDDATAH = 0;
643	MCF_GPIO_PAR_LCDDATA = 0;
644
645	/* Pin assignments for port LCDDATAM
646	Port LCDDATAM pins are all GPIO inputs
647	*/
648	MCF_GPIO_PDDR_LCDDATAM = 0;
649
650	/* Pin assignments for port LCDDATAL
651	Port LCDDATAL pins are all GPIO inputs
652	*/
653	MCF_GPIO_PDDR_LCDDATAL = 0;
654
655	/* Pin assignments for port LCDCTLH
656	Pins are all GPIO inputs
657	*/
658	MCF_GPIO_PDDR_LCDCTLH = 0;
659	MCF_GPIO_PAR_LCDCTL = 0;
660
661	/* Pin assignments for port LCDCTLL
662	Pins are all GPIO inputs
663	*/
664	MCF_GPIO_PDDR_LCDCTLL = 0;
665
666	/* Pin assignments for port PWM
667	Pins are all GPIO inputs
668	*/
669	MCF_GPIO_PDDR_PWM = 0;
670	MCF_GPIO_PAR_PWM = 0;
671
672	/* Pin assignments for port QSPI
673	Pins are all GPIO inputs
674	*/
675	MCF_GPIO_PDDR_QSPI = 0;
676	MCF_GPIO_PAR_QSPI = 0;
677
678	/* Pin assignments for port SSI
679	Pins are all GPIO inputs
680	*/
681	MCF_GPIO_PDDR_SSI = 0;
682	MCF_GPIO_PAR_SSI = 0;
683
684	/* Pin assignments for port TIMER
685	Pins are all GPIO outputs
686	*/
687	MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 \|
688	MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 \|
689	MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 \| MCF_GPIO_PDDR_TIMER_PDDR_TIMER0;
690	MCF_GPIO_PAR_TIMER = 0;
691
692	/* Pin assignments for port UART
693	Pin UART7 : UART 1 clear-to-send, /U1CTS
694	Pin UART6 : UART 1 request-to-send, /U1RTS
695	Pin UART5 : UART 1 transmit data, U1TXD
696	Pin UART4 : UART 1 receive data, U1RXD
697	Pin UART3 : UART 0 clear-to-send, /U0CTS
698	Pin UART2 : UART 0 request-to-send, /U0RTS
699	Pin UART1 : UART 0 transmit data, U0TXD
700	Pin UART0 : UART 0 receive data, U0RXD
701	*/
702	MCF_GPIO_PDDR_UART = 0;
703	MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) \|
704	MCF_GPIO_PAR_UART_PAR_URTS1(0x3) \|
705	MCF_GPIO_PAR_UART_PAR_URXD1(0x3) \|
706	MCF_GPIO_PAR_UART_PAR_UTXD1(0x3) \|
707	MCF_GPIO_PAR_UART_PAR_UCTS0 \|
708	MCF_GPIO_PAR_UART_PAR_URTS0 \|
709	MCF_GPIO_PAR_UART_PAR_URXD0 \| MCF_GPIO_PAR_UART_PAR_UTXD0;
710	}

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