source: rtems/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c @ 6b56ec3

4.104.114.95
Last change on this file since 6b56ec3 was 6b56ec3, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 20, 2008 at 2:58:34 PM

2008-06-20 Matthew Riek <matthew.riek@…>

  • ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, gdb-init, preinstall.am, clock/clock.c, console/console.c, include/bsp.h, include/bspopts.h.in, include/coverhd.h, include/tm27.h, network/network.c, start/start.S, startup/bspclean.c, startup/bspstart.c, startup/cfinit.c, startup/init5329.c, startup/linkcmds, startup/linkcmdsflash, timer/timer.c: New files.
  • Property mode set to 100644
File size: 15.5 KB
Line 
1
2/*********************************************************************
3* Initialisation Code for ColdFire MCF5329 Processor                 *
4**********************************************************************
5 Generated by ColdFire Initialisation Utility 2.10.8
6 Mon Jun 16 10:41:41 2008
7   
8 MicroAPL Ltd makes no warranties in respect of the suitability
9 of this code for any particular purpose, and accepts
10 no liability for any loss arising out of its use. The person or 
11 persons making use of this file must make the final evaluation
12 as to its suitability and correctness for a particular application.
13   
14 $Id$
15*/
16
17/* External reference frequency is 16.0000 MHz
18 Internal bus clock frequency = 80.00 MHz
19 Processor core frequency = 240.00 MHz
20*/
21
22#include <bsp.h>
23
24/* eDMA Transfer Control Descriptor definitions */
25#define  MCF_EDMA_TCD_W0(channel)            (*(vuint32 *)(0xFC045000+((channel)*0x20)))        /* Transfer Control Descriptor Word 0 */
26#define  MCF_EDMA_TCD_W1(channel)            (*(vuint32 *)(0xFC045004+((channel)*0x20)))        /* Transfer Control Descriptor Word 1 */
27#define  MCF_EDMA_TCD_W2(channel)            (*(vuint32 *)(0xFC045008+((channel)*0x20)))        /* Transfer Control Descriptor Word 2 */
28#define  MCF_EDMA_TCD_W3(channel)            (*(vuint32 *)(0xFC04500C+((channel)*0x20)))        /* Transfer Control Descriptor Word 3 */
29#define  MCF_EDMA_TCD_W4(channel)            (*(vuint32 *)(0xFC045010+((channel)*0x20)))        /* Transfer Control Descriptor Word 4 */
30#define  MCF_EDMA_TCD_W5(channel)            (*(vuint32 *)(0xFC045014+((channel)*0x20)))        /* Transfer Control Descriptor Word 5 */
31#define  MCF_EDMA_TCD_W6(channel)            (*(vuint32 *)(0xFC045018+((channel)*0x20)))        /* Transfer Control Descriptor Word 6 */
32#define  MCF_EDMA_TCD_W7(channel)            (*(vuint32 *)(0xFC04501C+((channel)*0x20)))        /* Transfer Control Descriptor Word 7 */
33
34/* Function prototypes */
35void init_main(void);
36static void disable_interrupts(void);
37static void disable_watchdog_timer(void);
38static void disable_cache(void);
39extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
40extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
41static void init_real_time_clock(void);
42static void init_watchdog_timers(void);
43static void init_pin_assignments(void);
44extern void init_sdram_controller(void)
45  __attribute__ ((section(".ram_code")));
46
47/*********************************************************************
48* init_main - Main entry point for initialisation code               *
49**********************************************************************/
50void init_main(void)
51{
52  /* Mask all interrupts */
53  init_clock_config();
54
55  /* Disable interrupts, watchdog timer, cache */
56  disable_interrupts();
57  disable_watchdog_timer();
58  disable_cache();
59
60  /* Initialise individual modules */
61  init_chip_selects();
62  init_real_time_clock();
63  init_watchdog_timers();
64  init_pin_assignments();
65
66  /* Initialise SDRAM controller (must be done after pin assignments) */
67  init_sdram_controller();
68}
69
70/*********************************************************************
71* disable_interrupts - Disable all interrupt sources                 *
72**********************************************************************/
73static void disable_interrupts(void)
74{
75  vuint8 *p;
76  int i;
77
78  /* Set ICR001-ICR063 to 0x0 */
79  p = (vuint8 *) & MCF_INTC0_ICR1;
80  for (i = 1; i <= 63; i++)
81    *p++ = 0x0;
82
83  /* Set ICR100-ICR163 to 0x0 */
84  p = (vuint8 *) & MCF_INTC1_ICR0;
85  for (i = 100; i <= 163; i++)
86    *p++ = 0x0;
87}
88
89/*********************************************************************
90* disable_watchdog_timer - Disable system watchdog timer             *
91**********************************************************************/
92static void disable_watchdog_timer(void)
93{
94  /* Disable Core Watchdog Timer */
95  MCF_SCM_CWCR = 0;
96}
97
98/*********************************************************************
99* disable_cache - Disable and invalidate cache                       *
100**********************************************************************/
101static void disable_cache(void)
102{
103  asm("move.l   #0x01000000,%d0");
104  asm("movec    %d0,%CACR");
105}
106
107/*********************************************************************
108* init_clock_config - Clock Module                                   *
109**********************************************************************/
110
111void init_clock_config(void)
112{
113  /* Clock module uses normal PLL mode with 16.0000 MHz external reference
114     Bus clock frequency = 80.00 MHz
115     Processor clock frequency = 3 x bus clock = 240.00 MHz
116     Dithering disabled
117   */
118
119  /* Check to see if the SDRAM has already been initialized
120     by a run control tool. If it has, put SDRAM into self-refresh mode before
121     initializing the PLL
122   */
123  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
124    MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
125
126  /* Temporarily switch to LIMP mode
127     NOTE: Ensure that this code is not executing from SDRAM, since the 
128     SDRAM Controller is disabled in LIMP mode 
129   */
130  MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2);
131  MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
132
133  /* Configure the PLL settings */
134  MCF_PLL_PODR = MCF_PLL_PODR_CPUDIV(0x2) | MCF_PLL_PODR_BUSDIV(0x6);
135  MCF_PLL_PFDR = MCF_PLL_PFDR_MFD(0x78);
136  MCF_PLL_PLLCR = 0;
137  MCF_PLL_PMDR = 0;
138
139  /* Enable PLL and wait for lock */
140  MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP;
141  while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
142
143  /* From the Device Errata:
144
145     "After exiting LIMP mode, the value of 0x40000000 should be written
146     to address 0xFC0B8080 before attempting to initialize the SDRAMC
147     or exit the SDRAM from self-refresh mode."
148   */
149  *(vuint32 *) 0xfc0b8080 = 0x40000000;
150
151  /* If we put the SDRAM into self-refresh mode earlier, restore mode now */
152  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
153    MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
154}
155
156/*********************************************************************
157* init_chip_selects - Chip Select Module (FlexBus)                   *
158**********************************************************************/
159void init_chip_selects(void)
160{
161  /* Chip Select 0: 2 MB of Flash at base address $00000000
162     Port size = 16 bits
163     Assert chip select on first rising clock edge after address is asserted
164     Generate internal transfer acknowledge after 7 wait states
165     Address is held for 1 clock at end of read and write cycles
166   */
167  MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
168    (0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
169  MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
170}
171
172/*********************************************************************
173* init_sdram_controller - SDRAM Controller                           *
174**********************************************************************/
175void init_sdram_controller(void)
176{
177  /* Check to see if the SDRAM has already been initialized
178     by a run control tool and skip if so
179   */
180  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
181    return;
182
183  /* Ensure that there is a delay from processor reset of the time recommended in
184     the SDRAM data sheet (typically 100-200 microseconds) until the following 
185     code so that the SDRAM is ready for commands...
186   */
187
188  /* SDRAM controller configured for Double-data rate (DDR) SDRAM
189     Bus width = 16 bits
190     SDRAM specification:
191     SDRAM clock frequency = 80.00 MHz
192     CASL = 2.5
193     ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
194     Write recovery time, tWR = 15.0 nanoseconds
195     Precharge comand to ACTV command, tRP = 20.0 nanoseconds
196     Auto refresh command period, tRFC = 75.0 nanoseconds
197     Average periodic refresh interval, tREFI = 7.8 microseconds
198   */
199
200  /* Memory block 0 enabled - 32 MBytes at address $40000000
201     Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
202   */
203  MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);
204
205  /* Memory block 1 disabled */
206  MCF_SDRAMC_SDCS1 = 0;
207
208  /* Initialise SDCFG1 register with delay and timing values
209     SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
210     PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
211   */
212  MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
213    MCF_SDRAMC_SDCFG1_SWT2RD(0x3) |
214    MCF_SDRAMC_SDCFG1_RDLAT(0x7) |
215    MCF_SDRAMC_SDCFG1_ACT2RW(0x2) |
216    MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) |
217    MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);
218
219  /* Initialise SDCFG2 register with delay and timing values
220     BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
221   */
222  MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
223    MCF_SDRAMC_SDCFG2_BWT2RW(0x6) |
224    MCF_SDRAMC_SDCFG2_BRD2WT(0x6) | MCF_SDRAMC_SDCFG2_BL(0x7);
225
226  /* Issue a Precharge All command */
227  MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_MODE_EN |
228    MCF_SDRAMC_SDCR_CKE |
229    MCF_SDRAMC_SDCR_DDR |
230    MCF_SDRAMC_SDCR_MUX(0x1) |
231    MCF_SDRAMC_SDCR_RCNT(0x8) | MCF_SDRAMC_SDCR_PS_16 | MCF_SDRAMC_SDCR_IPALL;
232
233  /* Write Extended Mode Register */
234  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_CMD;
235
236  /* Write Mode Register and Reset DLL */
237  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
238    MCF_SDRAMC_SDMR_AD(0x163) | MCF_SDRAMC_SDMR_CMD;
239
240  /* Insert code here to pause for DLL lock time specified by memory... */
241
242  /* Issue a second Precharge All command */
243  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
244
245  /* Refresh sequence...
246     (check the number of refreshes required by the SDRAM manufacturer)
247   */
248  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
249  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
250
251  /* Write Mode Register and clear the Reset DLL bit */
252  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
253    MCF_SDRAMC_SDMR_AD(0x63) | MCF_SDRAMC_SDMR_CMD;
254
255  /* Enable automatic refresh and lock SDMR */
256  MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
257  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_REF |
258    MCF_SDRAMC_SDCR_DQS_OE(0x8) | MCF_SDRAMC_SDCR_DQS_OE(0x4);
259
260}
261
262/*********************************************************************
263* init_real_time_clock - Real-Time Clock (RTC)                       *
264**********************************************************************/
265static void init_real_time_clock(void)
266{
267  /* Disable the RTC */
268  MCF_RTC_CR = 0;
269}
270
271/*********************************************************************
272* init_watchdog_timers - Watchdog Timers                             *
273**********************************************************************/
274static void init_watchdog_timers(void)
275{
276  /* Watchdog Timer disabled (WCR[EN]=0)
277     NOTE: WCR and WMR cannot be written again until after the 
278     processor is reset.
279   */
280  MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
281
282  /* Core watchdog timer disabled */
283  MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
284}
285
286/*********************************************************************
287* init_pin_assignments - Pin Assignment and General Purpose I/O      *
288**********************************************************************/
289static void init_pin_assignments(void)
290{
291  /* Pin assignments for port BUSCTL
292     Pin BUSCTL3 : External bus output enable, /OE
293     Pin BUSCTL2 : External bus transfer acknowledge, /TA
294     Pin BUSCTL1 : External bus read/write, R/W
295     Pin BUSCTL0 : External bus transfer start, /TS
296   */
297  MCF_GPIO_PDDR_BUSCTL = 0;
298  MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE |
299    MCF_GPIO_PAR_BUSCTL_PAR_TA |
300    MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
301
302  /* Pin assignments for port BE
303     Pin BE3 : External bus byte enable BW/BWE3
304     Pin BE2 : External bus byte enable BW/BWE2
305     Pin BE1 : External bus byte enable BW/BWE1
306     Pin BE0 : External bus byte enable BW/BWE0
307   */
308  MCF_GPIO_PDDR_BE = 0;
309  MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 |
310    MCF_GPIO_PAR_BE_PAR_BE2 |
311    MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0;
312
313  /* Pin assignments for port CS
314     Pin CS5 : Flex bus chip select /FB_CS5
315     Pin CS4 : Flex bus chip select /FB_CS4
316     Pin CS3 : Flex bus chip select /FB_CS3
317     Pin CS2 : Flex bus chip select /FB_CS2
318     Pin CS1 : Flex bus chip select /FB_CS1
319   */
320  MCF_GPIO_PDDR_CS = 0;
321  MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 |
322    MCF_GPIO_PAR_CS_PAR_CS4 |
323    MCF_GPIO_PAR_CS_PAR_CS3 |
324    MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
325
326  /* Pin assignments for port FECI2C
327     Pin FECI2C3 : FEC management data clock, FEC_MDC
328     Pin FECI2C2 : FEC management data, FEC_MDIO
329     Pin FECI2C1 : GPIO input
330     Pin FECI2C0 : GPIO input
331   */
332  MCF_GPIO_PDDR_FECI2C = 0;
333  MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) |
334    MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
335
336  /* Pin assignments for ports FECH and FECL
337     Pin FECH7 : FEC transmit clock, FEC_TXCLK
338     Pin FECH6 : FEC transmit enable, FEC_TXEN
339     Pin FECH5 : FEC transmit data 0, FEC_TXD0
340     Pin FECH4 : FEC collision, FEC_COL
341     Pin FECH3 : FEC receive clock, FEC_RXCLK
342     Pin FECH2 : FEC receive data valid, FEC_RXDV
343     Pin FECH1 : FEC receive data 0, FEC_RXD0
344     Pin FECH0 : FEC carrier receive sense, FEC_CRS
345     Pin FECL7 : FEC transmit data 3, FEC_TXD3
346     Pin FECL6 : FEC transmit data 2, FEC_TXD2
347     Pin FECL5 : FEC transmit data 1, FEC_TXD1
348     Pin FECL4 : FEC transmit error, FEC_TXER
349     Pin FECL3 : FEC receive data 3, FEX_RXD3
350     Pin FECL2 : FEC receive data 2, FEX_RXD2
351     Pin FECL1 : FEC receive data 1, FEX_RXD1
352     Pin FECL0 : FEC receive error, FEC_RXER
353   */
354  MCF_GPIO_PDDR_FECH = 0;
355  MCF_GPIO_PDDR_FECL = 0;
356  MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) |
357    MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
358
359  /* Pin assignments for port IRQ
360     Pins are all used for EdgePort GPIO/IRQ
361   */
362  MCF_GPIO_PAR_IRQ = 0;
363
364  /* Pin assignments for port LCDDATAH
365     Pins are all GPIO inputs
366   */
367  MCF_GPIO_PDDR_LCDDATAH = 0;
368  MCF_GPIO_PAR_LCDDATA = 0;
369
370  /* Pin assignments for port LCDDATAM
371     Port LCDDATAM pins are all GPIO inputs
372   */
373  MCF_GPIO_PDDR_LCDDATAM = 0;
374
375  /* Pin assignments for port LCDDATAL
376     Port LCDDATAL pins are all GPIO inputs
377   */
378  MCF_GPIO_PDDR_LCDDATAL = 0;
379
380  /* Pin assignments for port LCDCTLH
381     Pins are all GPIO inputs
382   */
383  MCF_GPIO_PDDR_LCDCTLH = 0;
384  MCF_GPIO_PAR_LCDCTL = 0;
385
386  /* Pin assignments for port LCDCTLL
387     Pins are all GPIO inputs
388   */
389  MCF_GPIO_PDDR_LCDCTLL = 0;
390
391  /* Pin assignments for port PWM
392     Pins are all GPIO inputs
393   */
394  MCF_GPIO_PDDR_PWM = 0;
395  MCF_GPIO_PAR_PWM = 0;
396
397  /* Pin assignments for port QSPI
398     Pins are all GPIO inputs
399   */
400  MCF_GPIO_PDDR_QSPI = 0;
401  MCF_GPIO_PAR_QSPI = 0;
402
403  /* Pin assignments for port SSI
404     Pins are all GPIO inputs
405   */
406  MCF_GPIO_PDDR_SSI = 0;
407  MCF_GPIO_PAR_SSI = 0;
408
409  /* Pin assignments for port TIMER
410     Pins are all GPIO outputs
411   */
412  MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 |
413    MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 |
414    MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER0;
415  MCF_GPIO_PAR_TIMER = 0;
416
417  /* Pin assignments for port UART
418     Pin UART7 : UART 1 clear-to-send, /U1CTS
419     Pin UART6 : UART 1 request-to-send, /U1RTS
420     Pin UART5 : UART 1 transmit data, U1TXD
421     Pin UART4 : UART 1 receive data, U1RXD
422     Pin UART3 : UART 0 clear-to-send, /U0CTS
423     Pin UART2 : UART 0 request-to-send, /U0RTS
424     Pin UART1 : UART 0 transmit data, U0TXD
425     Pin UART0 : UART 0 receive data, U0RXD
426   */
427  MCF_GPIO_PDDR_UART = 0;
428  MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) |
429    MCF_GPIO_PAR_UART_PAR_URTS1(0x3) |
430    MCF_GPIO_PAR_UART_PAR_URXD1(0x3) |
431    MCF_GPIO_PAR_UART_PAR_UTXD1(0x3) |
432    MCF_GPIO_PAR_UART_PAR_UCTS0 |
433    MCF_GPIO_PAR_UART_PAR_URTS0 |
434    MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0;
435}
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