source: rtems/c/src/lib/libbsp/m68k/mcf5329/gdb-init @ a840853

4.104.114.95
Last change on this file since a840853 was 6b56ec3, checked in by Joel Sherrill <joel.sherrill@…>, on 06/20/08 at 14:58:34

2008-06-20 Matthew Riek <matthew.riek@…>

  • ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, gdb-init, preinstall.am, clock/clock.c, console/console.c, include/bsp.h, include/bspopts.h.in, include/coverhd.h, include/tm27.h, network/network.c, start/start.S, startup/bspclean.c, startup/bspstart.c, startup/cfinit.c, startup/init5329.c, startup/linkcmds, startup/linkcmdsflash, timer/timer.c: New files.
  • Property mode set to 100644
File size: 2.7 KB
Line 
1#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 -v -d
2target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0
3
4#monitor set remote-debug 1
5#monitor set debug 1
6monitor bdm-reset
7
8#
9# Show the exception stack frame.
10#
11define show-exception-sframe
12 set $frsr = *(unsigned short *)((unsigned long)$sp + 2)
13 set $frpc = *(unsigned long *)((unsigned long)$sp + 4)
14 set $frfvo = *(unsigned short *)((unsigned long)$sp + 0)
15 set $frcode = $frfvo >> 12
16 set $frvect = ($frfvo & 0xFFF) >> 2
17 set $frstatus = ((($frfvo >> 10) & 3) << 2) | ($frfvo & 3)
18 printf "EXCEPTION -- SR:0x%X  PC:0x%X  FRAME:0x%x  VECTOR:%d  STATUS:%d\n", $frsr, $frpc, $frcode, $frvect, $frstatus
19 if $frstatus == 4
20  printf " Fault Type: Error on instruction fetch"
21 end
22 if $frstatus == 8
23  printf " Fault Type: Error on operand write"
24 end
25 if $frstatus == 12
26  printf " Fault Type: Error on operand read"
27 end
28 if $frstatus == 9
29  printf " Fault Type: Attempted write to write-protected space"
30 end
31end
32
33# I have to do this as there seems to be a problem with me setting up the
34# chip selects.  As far as I can tell, gdb is probing whats at the program
35# counter.  It issues a 2 byte read (smallest instruction) followed by a
36# 4 byte read (depending on the result of the 2 byte read).  gdb issues these
37# reads after each and every write that the .gdbinit script issues.  This means
38# that as I'm initializing the chip selects the gdb reads can happen in an
39# invalid memory address and this causes a target bus error.  For now I'm just
40# setting pc to 0, which seems to stop gdb from probing around to read
41# assembler.  This lets me setup chip selects without error.
42
43set $pc = 0x00000000
44
45# Turn on RAMBAR1 at address 80000000
46monitor bdm-ctl-set 0x0C05 0x80000221
47
48# Set VBR to the beginning of what will be SDRAM
49# VBR is an absolute CPU register
50monitor bdm-ctl-set 0x0801 0x40000000
51
52# Disable watchdog timer
53set *((short*) 0xFC098000) = 0x0000
54
55#Init CS0
56set *((long*) 0xFC008000) = 0x00000000
57set *((long*) 0xFC008008) = 0x00001FA0
58set *((long*) 0xFC008004) = 0x001F0001
59
60# SDRAM Initialization
61
62monitor delay-ms 100
63
64# SDCS0
65set *((long*) 0xFC0B8110) = 0x40000018
66# SDCFG1
67set *((long*) 0xFC0B8008) = 0x53722730
68# SDCFG2
69set *((long*) 0xFC0B800C) = 0x56670000
70
71# Issue PALL
72# SDCR
73set *((long*) 0xFC0B8004) = 0xE1092002
74
75# Issue LEMR
76# SDMR
77set *((long*) 0xFC0B8000) = 0x40010000
78
79# Write mode register
80# SDMR
81set *((long*) 0xFC0B8000) = 0x058D0000
82
83# Wait a bit
84monitor delay-ms 600
85
86# Issue PALL
87# SDCR
88set *((long*) 0xFC0B8004) = 0xE1092002
89
90# Perform two refresh cycles
91# SDCR
92set *((long*) 0xFC0B8004) = 0xE1092004
93# SDCR
94set *((long*) 0xFC0B8004) = 0xE1092004
95
96# SDMR
97set *((long*) 0xFC0B8000) = 0x018D0000
98# SDCR
99set *((long*) 0xFC0B8004) = 0x71092C00
100
101# Wait a bit
102monitor delay-ms 100
103
104load
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