1 | #target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 -v -d |
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2 | target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 |
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3 | |
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4 | #monitor set remote-debug 1 |
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5 | #monitor set debug 1 |
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6 | monitor bdm-reset |
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7 | |
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8 | # |
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9 | # Show the exception stack frame. |
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10 | # |
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11 | define show-exception-sframe |
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12 | set $frsr = *(unsigned short *)((unsigned long)$sp + 2) |
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13 | set $frpc = *(unsigned long *)((unsigned long)$sp + 4) |
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14 | set $frfvo = *(unsigned short *)((unsigned long)$sp + 0) |
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15 | set $frcode = $frfvo >> 12 |
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16 | set $frvect = ($frfvo & 0xFFF) >> 2 |
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17 | set $frstatus = ((($frfvo >> 10) & 3) << 2) | ($frfvo & 3) |
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18 | printf "EXCEPTION -- SR:0x%X PC:0x%X FRAME:0x%x VECTOR:%d STATUS:%d\n", $frsr, $frpc, $frcode, $frvect, $frstatus |
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19 | if $frstatus == 4 |
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20 | printf " Fault Type: Error on instruction fetch" |
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21 | end |
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22 | if $frstatus == 8 |
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23 | printf " Fault Type: Error on operand write" |
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24 | end |
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25 | if $frstatus == 12 |
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26 | printf " Fault Type: Error on operand read" |
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27 | end |
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28 | if $frstatus == 9 |
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29 | printf " Fault Type: Attempted write to write-protected space" |
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30 | end |
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31 | end |
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32 | |
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33 | # I have to do this as there seems to be a problem with me setting up the |
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34 | # chip selects. As far as I can tell, gdb is probing whats at the program |
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35 | # counter. It issues a 2 byte read (smallest instruction) followed by a |
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36 | # 4 byte read (depending on the result of the 2 byte read). gdb issues these |
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37 | # reads after each and every write that the .gdbinit script issues. This means |
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38 | # that as I'm initializing the chip selects the gdb reads can happen in an |
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39 | # invalid memory address and this causes a target bus error. For now I'm just |
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40 | # setting pc to 0, which seems to stop gdb from probing around to read |
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41 | # assembler. This lets me setup chip selects without error. |
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42 | |
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43 | set $pc = 0x00000000 |
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44 | |
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45 | # Turn on RAMBAR1 at address 80000000 |
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46 | monitor bdm-ctl-set 0x0C05 0x80000221 |
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47 | |
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48 | # Set VBR to the beginning of what will be SDRAM |
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49 | # VBR is an absolute CPU register |
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50 | monitor bdm-ctl-set 0x0801 0x40000000 |
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51 | |
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52 | # Disable watchdog timer |
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53 | set *((short*) 0xFC098000) = 0x0000 |
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54 | |
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55 | #Init CS0 |
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56 | set *((long*) 0xFC008000) = 0x00000000 |
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57 | set *((long*) 0xFC008008) = 0x00001FA0 |
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58 | set *((long*) 0xFC008004) = 0x001F0001 |
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59 | |
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60 | # SDRAM Initialization |
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61 | |
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62 | monitor delay-ms 100 |
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63 | |
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64 | # SDCS0 |
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65 | set *((long*) 0xFC0B8110) = 0x40000018 |
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66 | # SDCFG1 |
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67 | set *((long*) 0xFC0B8008) = 0x53722730 |
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68 | # SDCFG2 |
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69 | set *((long*) 0xFC0B800C) = 0x56670000 |
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70 | |
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71 | # Issue PALL |
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72 | # SDCR |
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73 | set *((long*) 0xFC0B8004) = 0xE1092002 |
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74 | |
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75 | # Issue LEMR |
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76 | # SDMR |
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77 | set *((long*) 0xFC0B8000) = 0x40010000 |
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78 | |
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79 | # Write mode register |
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80 | # SDMR |
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81 | set *((long*) 0xFC0B8000) = 0x058D0000 |
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82 | |
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83 | # Wait a bit |
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84 | monitor delay-ms 600 |
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85 | |
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86 | # Issue PALL |
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87 | # SDCR |
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88 | set *((long*) 0xFC0B8004) = 0xE1092002 |
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89 | |
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90 | # Perform two refresh cycles |
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91 | # SDCR |
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92 | set *((long*) 0xFC0B8004) = 0xE1092004 |
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93 | # SDCR |
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94 | set *((long*) 0xFC0B8004) = 0xE1092004 |
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95 | |
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96 | # SDMR |
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97 | set *((long*) 0xFC0B8000) = 0x018D0000 |
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98 | # SDCR |
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99 | set *((long*) 0xFC0B8004) = 0x71092C00 |
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100 | |
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101 | # Wait a bit |
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102 | monitor delay-ms 100 |
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103 | |
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104 | load |
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