source: rtems/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c @ b1ded240

4.104.11
Last change on this file since b1ded240 was b1ded240, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 16, 2008 at 7:03:28 PM

2008-09-16 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, configure.ac, startup/bspstart.c, startup/linkcmds, startup/linkcmdsflash, startup/linkcmdsram: Add use of bsp_get_work_area() in its own file and rely on BSP Framework to perform more initialization. Remove unnecessary includes of rtems/libio.h and rtems/libcsupport.h.
  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <bsp.h>
25 
26/*
27 * Cacheable areas
28 */
29#define SDRAM_BASE      0
30#define SDRAM_SIZE      (16*1024*1024)
31
32/*
33 * CPU-space access
34 */
35#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
36#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
37#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
38
39/*
40 * Read/write copy of common cache
41 *   Split I/D cache
42 *   Allow CPUSHL to invalidate a cache line
43 *   Enable buffered writes
44 *   No burst transfers on non-cacheable accesses
45 *   Default cache mode is *disabled* (cache only ACRx areas)
46 */
47static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
48                              MCF5XXX_CACR_DBWE |
49                              MCF5XXX_CACR_DCM;
50/*
51 * Cannot be frozen
52 */
53void _CPU_cache_freeze_data(void) {}
54void _CPU_cache_unfreeze_data(void) {}
55void _CPU_cache_freeze_instruction(void) {}
56void _CPU_cache_unfreeze_instruction(void) {}
57
58/*
59 * Write-through data cache -- flushes are unnecessary
60 */
61void _CPU_cache_flush_1_data_line(const void *d_addr) {}
62void _CPU_cache_flush_entire_data(void) {}
63
64void _CPU_cache_enable_instruction(void)
65{
66    rtems_interrupt_level level;
67
68    rtems_interrupt_disable(level);
69    cacr_mode &= ~MCF5XXX_CACR_DIDI;
70    m68k_set_cacr(cacr_mode);
71    rtems_interrupt_enable(level);
72}
73
74void _CPU_cache_disable_instruction(void)
75{
76    rtems_interrupt_level level;
77
78    rtems_interrupt_disable(level);
79    cacr_mode |= MCF5XXX_CACR_DIDI;
80    m68k_set_cacr(cacr_mode);
81    rtems_interrupt_enable(level);
82}
83
84void _CPU_cache_invalidate_entire_instruction(void)
85{
86    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
87}
88
89void _CPU_cache_invalidate_1_instruction_line(const void *addr)
90{
91    /*
92     * Top half of cache is I-space
93     */
94    addr = (void *)((int)addr | 0x400);
95    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
96}
97
98void _CPU_cache_enable_data(void)
99{
100    rtems_interrupt_level level;
101
102    rtems_interrupt_disable(level);
103    cacr_mode &= ~MCF5XXX_CACR_DISD;
104    m68k_set_cacr(cacr_mode);
105    rtems_interrupt_enable(level);
106}
107
108void _CPU_cache_disable_data(void)
109{
110    rtems_interrupt_level level;
111
112    rtems_interrupt_disable(level);
113    cacr_mode |= MCF5XXX_CACR_DISD;
114    m68k_set_cacr(cacr_mode);
115    rtems_interrupt_enable(level);
116}
117
118void _CPU_cache_invalidate_entire_data(void)
119{
120    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
121}
122
123void _CPU_cache_invalidate_1_data_line(const void *addr)
124{
125    /*
126     * Bottom half of cache is D-space
127     */
128    addr = (void *)((int)addr & ~0x400);
129    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
130}
131
132/*
133 *  bsp_start
134 *
135 *  This routine does the bulk of the system initialisation.
136 */
137void bsp_start( void )
138{
139  /*
140   * Invalidate the cache and disable it
141   */
142  m68k_set_acr0(0);
143  m68k_set_acr1(0);
144  m68k_set_cacr(MCF5XXX_CACR_CINV);
145
146  /*
147   * Cache SDRAM
148   */
149  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
150                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
151                MCF5XXX_ACR_EN                |
152                MCF5XXX_ACR_BWE               |
153                MCF5XXX_ACR_SM_IGNORE);
154
155  /*
156   * Enable the cache
157   */
158  m68k_set_cacr(cacr_mode);
159}
160
161extern char _CPUClockSpeed[];
162
163uint32_t get_CPU_clock_speed(void)
164{
165  return( (uint32_t)_CPUClockSpeed);
166}
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