source: rtems/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c @ a474e3c

4.104.114.84.9
Last change on this file since a474e3c was a474e3c, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 12, 2007 at 11:18:19 AM

2007-03-12 Joel Sherrill <joel@…>

  • include/coverhd.h, start/start.S, startup/bspclean.c, startup/bspstart.c, startup/linkcmds, startup/linkcmdsflash, startup/linkcmdsram: Correct license URL and/or fix mistake in copyright notice. Both of these mistakes appear to be from code submitted after these changes were made previously.
  • Property mode set to 100644
File size: 5.5 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <bsp.h>
25#include <rtems/libio.h>
26#include <rtems/libcsupport.h>
27#include <string.h>
28 
29/*
30 *  The original table from the application and our copy of it with
31 *  some changes.
32 */
33extern rtems_configuration_table Configuration;
34rtems_configuration_table  BSP_Configuration;
35rtems_cpu_table Cpu_table;
36char *rtems_progname;
37
38
39/*
40 * Cacheable areas
41 */
42#define SDRAM_BASE      0
43#define SDRAM_SIZE      (16*1024*1024)
44
45/*
46 * CPU-space access
47 */
48#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
49#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
50#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
51
52/*
53 * Read/write copy of common cache
54 *   Split I/D cache
55 *   Allow CPUSHL to invalidate a cache line
56 *   Enable buffered writes
57 *   No burst transfers on non-cacheable accesses
58 *   Default cache mode is *disabled* (cache only ACRx areas)
59 */
60static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
61                              MCF5XXX_CACR_DBWE |
62                              MCF5XXX_CACR_DCM;
63/*
64 * Cannot be frozen
65 */
66void _CPU_cache_freeze_data(void) {}
67void _CPU_cache_unfreeze_data(void) {}
68void _CPU_cache_freeze_instruction(void) {}
69void _CPU_cache_unfreeze_instruction(void) {}
70
71/*
72 * Write-through data cache -- flushes are unnecessary
73 */
74void _CPU_cache_flush_1_data_line(const void *d_addr) {}
75void _CPU_cache_flush_entire_data(void) {}
76
77void _CPU_cache_enable_instruction(void)
78{
79    rtems_interrupt_level level;
80
81    rtems_interrupt_disable(level);
82    cacr_mode &= ~MCF5XXX_CACR_DIDI;
83    m68k_set_cacr(cacr_mode);
84    rtems_interrupt_enable(level);
85}
86
87void _CPU_cache_disable_instruction(void)
88{
89    rtems_interrupt_level level;
90
91    rtems_interrupt_disable(level);
92    cacr_mode |= MCF5XXX_CACR_DIDI;
93    m68k_set_cacr(cacr_mode);
94    rtems_interrupt_enable(level);
95}
96
97void _CPU_cache_invalidate_entire_instruction(void)
98{
99    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
100}
101
102void _CPU_cache_invalidate_1_instruction_line(const void *addr)
103{
104    /*
105     * Top half of cache is I-space
106     */
107    addr = (void *)((int)addr | 0x400);
108    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
109}
110
111void _CPU_cache_enable_data(void)
112{
113    rtems_interrupt_level level;
114
115    rtems_interrupt_disable(level);
116    cacr_mode &= ~MCF5XXX_CACR_DISD;
117    m68k_set_cacr(cacr_mode);
118    rtems_interrupt_enable(level);
119}
120
121void _CPU_cache_disable_data(void)
122{
123    rtems_interrupt_level level;
124
125    rtems_interrupt_disable(level);
126    rtems_interrupt_disable(level);
127    cacr_mode |= MCF5XXX_CACR_DISD;
128    m68k_set_cacr(cacr_mode);
129    rtems_interrupt_enable(level);
130}
131
132void _CPU_cache_invalidate_entire_data(void)
133{
134    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
135}
136
137void _CPU_cache_invalidate_1_data_line(const void *addr)
138{
139    /*
140     * Bottom half of cache is D-space
141     */
142    addr = (void *)((int)addr & ~0x400);
143    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
144}
145
146/*
147 *  Use the shared implementations of the following routines
148 */
149void bsp_postdriver_hook(void);
150void bsp_libc_init( void *, uint32_t, int );
151void bsp_pretasking_hook(void);                 /* m68k version */
152
153/*
154 *  bsp_start
155 *
156 *  This routine does the bulk of the system initialisation.
157 */
158void bsp_start( void )
159{
160  extern char _WorkspaceBase[];
161  extern char _RamSize[];
162  extern unsigned long  _M68k_Ramsize;
163
164  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
165
166  /*
167   *  Allocate the memory for the RTEMS Work Space.  This can come from
168   *  a variety of places: hard coded address, malloc'ed from outside
169   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
170   *  typically done by stock BSPs) by subtracting the required amount
171   *  of work space from the last physical address on the CPU board.
172   */
173
174  /*
175   *  Need to "allocate" the memory for the RTEMS Workspace and
176   *  tell the RTEMS configuration where it is.  This memory is
177   *  not malloc'ed.  It is just "pulled from the air".
178   */
179
180  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
181
182  /*
183   *  initialize the CPU table for this BSP
184   */
185  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
186  Cpu_table.postdriver_hook = bsp_postdriver_hook;
187  Cpu_table.interrupt_stack_size = 4096;
188  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
189
190    /*
191     * Invalidate the cache and disable it
192     */
193    m68k_set_acr0(0);
194    m68k_set_acr1(0);
195    m68k_set_cacr(MCF5XXX_CACR_CINV);
196
197    /*
198     * Cache SDRAM
199     */
200    m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
201                  MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
202                  MCF5XXX_ACR_EN                |
203                  MCF5XXX_ACR_BWE               |
204                  MCF5XXX_ACR_SM_IGNORE);
205
206    /*
207     * Enable the cache
208     */
209    m68k_set_cacr(cacr_mode);
210
211}
212
213uint32_t get_CPU_clock_speed(void)
214{
215    extern char _CPUClockSpeed[];
216    return( (uint32_t)_CPUClockSpeed);
217}
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