source: rtems/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c @ 6ea100c1

4.104.114.9
Last change on this file since 6ea100c1 was 6ea100c1, checked in by Joel Sherrill <joel.sherrill@…>, on May 12, 2008 at 6:43:55 PM

2008-05-12 Joel Sherrill <joel.sherrill@…>

  • startup/bspstart.c: Refactored and renamed initialization routines to rtems_initialize_data_structures, rtems_initialize_before_drivers, rtems_initialize_device_drivers, and rtems_initialize_start_multitasking. This opened the sequence up so that bootcard() could provide a more robust and flexible framework which is easier to explain and understand. This also lays the groundwork for sharing the division of available memory between the RTEMS workspace and heap and the C library initialization across all BSPs.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <bsp.h>
25#include <rtems/libio.h>
26#include <rtems/libcsupport.h>
27#include <string.h>
28 
29/*
30 * Cacheable areas
31 */
32#define SDRAM_BASE      0
33#define SDRAM_SIZE      (16*1024*1024)
34
35/*
36 * CPU-space access
37 */
38#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
39#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
40#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
41
42/*
43 * Read/write copy of common cache
44 *   Split I/D cache
45 *   Allow CPUSHL to invalidate a cache line
46 *   Enable buffered writes
47 *   No burst transfers on non-cacheable accesses
48 *   Default cache mode is *disabled* (cache only ACRx areas)
49 */
50static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
51                              MCF5XXX_CACR_DBWE |
52                              MCF5XXX_CACR_DCM;
53/*
54 * Cannot be frozen
55 */
56void _CPU_cache_freeze_data(void) {}
57void _CPU_cache_unfreeze_data(void) {}
58void _CPU_cache_freeze_instruction(void) {}
59void _CPU_cache_unfreeze_instruction(void) {}
60
61/*
62 * Write-through data cache -- flushes are unnecessary
63 */
64void _CPU_cache_flush_1_data_line(const void *d_addr) {}
65void _CPU_cache_flush_entire_data(void) {}
66
67void _CPU_cache_enable_instruction(void)
68{
69    rtems_interrupt_level level;
70
71    rtems_interrupt_disable(level);
72    cacr_mode &= ~MCF5XXX_CACR_DIDI;
73    m68k_set_cacr(cacr_mode);
74    rtems_interrupt_enable(level);
75}
76
77void _CPU_cache_disable_instruction(void)
78{
79    rtems_interrupt_level level;
80
81    rtems_interrupt_disable(level);
82    cacr_mode |= MCF5XXX_CACR_DIDI;
83    m68k_set_cacr(cacr_mode);
84    rtems_interrupt_enable(level);
85}
86
87void _CPU_cache_invalidate_entire_instruction(void)
88{
89    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
90}
91
92void _CPU_cache_invalidate_1_instruction_line(const void *addr)
93{
94    /*
95     * Top half of cache is I-space
96     */
97    addr = (void *)((int)addr | 0x400);
98    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
99}
100
101void _CPU_cache_enable_data(void)
102{
103    rtems_interrupt_level level;
104
105    rtems_interrupt_disable(level);
106    cacr_mode &= ~MCF5XXX_CACR_DISD;
107    m68k_set_cacr(cacr_mode);
108    rtems_interrupt_enable(level);
109}
110
111void _CPU_cache_disable_data(void)
112{
113    rtems_interrupt_level level;
114
115    rtems_interrupt_disable(level);
116    rtems_interrupt_disable(level);
117    cacr_mode |= MCF5XXX_CACR_DISD;
118    m68k_set_cacr(cacr_mode);
119    rtems_interrupt_enable(level);
120}
121
122void _CPU_cache_invalidate_entire_data(void)
123{
124    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
125}
126
127void _CPU_cache_invalidate_1_data_line(const void *addr)
128{
129    /*
130     * Bottom half of cache is D-space
131     */
132    addr = (void *)((int)addr & ~0x400);
133    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
134}
135
136/*
137 *  Use the shared implementations of the following routines
138 */
139void bsp_libc_init( void *, uint32_t, int );
140void bsp_pretasking_hook(void);                 /* m68k version */
141
142/*
143 *  bsp_start
144 *
145 *  This routine does the bulk of the system initialisation.
146 */
147void bsp_start( void )
148{
149  extern char _WorkspaceBase[];
150  extern char _RamSize[];
151  extern unsigned long  _M68k_Ramsize;
152
153  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
154
155  /*
156   *  Allocate the memory for the RTEMS Work Space.  This can come from
157   *  a variety of places: hard coded address, malloc'ed from outside
158   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
159   *  typically done by stock BSPs) by subtracting the required amount
160   *  of work space from the last physical address on the CPU board.
161   */
162
163  /*
164   *  Need to "allocate" the memory for the RTEMS Workspace and
165   *  tell the RTEMS configuration where it is.  This memory is
166   *  not malloc'ed.  It is just "pulled from the air".
167   */
168
169  Configuration.work_space_start = (void *)_WorkspaceBase;
170
171  /*
172   * Invalidate the cache and disable it
173   */
174  m68k_set_acr0(0);
175  m68k_set_acr1(0);
176  m68k_set_cacr(MCF5XXX_CACR_CINV);
177
178  /*
179   * Cache SDRAM
180   */
181  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
182                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
183                MCF5XXX_ACR_EN                |
184                MCF5XXX_ACR_BWE               |
185                MCF5XXX_ACR_SM_IGNORE);
186
187  /*
188   * Enable the cache
189   */
190  m68k_set_cacr(cacr_mode);
191}
192
193uint32_t get_CPU_clock_speed(void)
194{
195  extern char _CPUClockSpeed[];
196  return( (uint32_t)_CPUClockSpeed);
197}
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