source: rtems/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c @ 1612af0

4.104.114.84.95
Last change on this file since 1612af0 was 1612af0, checked in by Joel Sherrill <joel.sherrill@…>, on 06/17/05 at 14:06:05

2005-06-17 Mike Bertosh <mbertosh@…>

  • .cvsignore, ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, clock/clock.c, console/console.c, include/bsp.h, include/coverhd.h, include/tm27.h, network/network.c, start/start.S, startup/bspclean.c, startup/bspstart.c, startup/init5235.c, startup/linkcmds, startup/linkcmdsflash, startup/linkcmdsram, timer/timer.c: New files.
  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29 
30/*
31 *  The original table from the application and our copy of it with
32 *  some changes.
33 */
34extern rtems_configuration_table Configuration;
35rtems_configuration_table  BSP_Configuration;
36rtems_cpu_table Cpu_table;
37char *rtems_progname;
38
39
40/*
41 * Cacheable areas
42 */
43#define SDRAM_BASE      0
44#define SDRAM_SIZE      (16*1024*1024)
45
46/*
47 * CPU-space access
48 */
49#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
50#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
51#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
52
53/*
54 * Read/write copy of common cache
55 *   Split I/D cache
56 *   Allow CPUSHL to invalidate a cache line
57 *   Enable buffered writes
58 *   No burst transfers on non-cacheable accesses
59 *   Default cache mode is *disabled* (cache only ACRx areas)
60 */
61static unsigned32 cacr_mode = MCF5XXX_CACR_CENB |
62                              MCF5XXX_CACR_DBWE |
63                              MCF5XXX_CACR_DCM;
64/*
65 * Cannot be frozen
66 */
67void _CPU_cache_freeze_data(void) {}
68void _CPU_cache_unfreeze_data(void) {}
69void _CPU_cache_freeze_instruction(void) {}
70void _CPU_cache_unfreeze_instruction(void) {}
71
72/*
73 * Write-through data cache -- flushes are unnecessary
74 */
75void _CPU_cache_flush_1_data_line(const void *d_addr) {}
76void _CPU_cache_flush_entire_data(void) {}
77
78void _CPU_cache_enable_instruction(void)
79{
80    rtems_interrupt_level level;
81
82    rtems_interrupt_disable(level);
83    cacr_mode &= ~MCF5XXX_CACR_DIDI;
84    m68k_set_cacr(cacr_mode);
85    rtems_interrupt_enable(level);
86}
87
88void _CPU_cache_disable_instruction(void)
89{
90    rtems_interrupt_level level;
91
92    rtems_interrupt_disable(level);
93    cacr_mode |= MCF5XXX_CACR_DIDI;
94    m68k_set_cacr(cacr_mode);
95    rtems_interrupt_enable(level);
96}
97
98void _CPU_cache_invalidate_entire_instruction(void)
99{
100    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
101}
102
103void _CPU_cache_invalidate_1_instruction_line(const void *addr)
104{
105    /*
106     * Top half of cache is I-space
107     */
108    addr = (void *)((int)addr | 0x400);
109    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
110}
111
112void _CPU_cache_enable_data(void)
113{
114    rtems_interrupt_level level;
115
116    rtems_interrupt_disable(level);
117    cacr_mode &= ~MCF5XXX_CACR_DISD;
118    m68k_set_cacr(cacr_mode);
119    rtems_interrupt_enable(level);
120}
121
122void _CPU_cache_disable_data(void)
123{
124    rtems_interrupt_level level;
125
126    rtems_interrupt_disable(level);
127    rtems_interrupt_disable(level);
128    cacr_mode |= MCF5XXX_CACR_DISD;
129    m68k_set_cacr(cacr_mode);
130    rtems_interrupt_enable(level);
131}
132
133void _CPU_cache_invalidate_entire_data(void)
134{
135    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
136}
137
138void _CPU_cache_invalidate_1_data_line(const void *addr)
139{
140    /*
141     * Bottom half of cache is D-space
142     */
143    addr = (void *)((int)addr & ~0x400);
144    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
145}
146
147/*
148 *  Use the shared implementations of the following routines
149 */
150void bsp_postdriver_hook(void);
151void bsp_libc_init( void *, unsigned32, int );
152void bsp_pretasking_hook(void);                 /* m68k version */
153
154/*
155 *  bsp_start
156 *
157 *  This routine does the bulk of the system initialisation.
158 */
159void bsp_start( void )
160{
161  extern char _WorkspaceBase[];
162  extern char _RamSize[];
163  extern unsigned long  _M68k_Ramsize;
164
165  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
166
167  /*
168   *  Allocate the memory for the RTEMS Work Space.  This can come from
169   *  a variety of places: hard coded address, malloc'ed from outside
170   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
171   *  typically done by stock BSPs) by subtracting the required amount
172   *  of work space from the last physical address on the CPU board.
173   */
174
175  /*
176   *  Need to "allocate" the memory for the RTEMS Workspace and
177   *  tell the RTEMS configuration where it is.  This memory is
178   *  not malloc'ed.  It is just "pulled from the air".
179   */
180
181  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
182
183  /*
184   *  initialize the CPU table for this BSP
185   */
186  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
187  Cpu_table.postdriver_hook = bsp_postdriver_hook;
188  Cpu_table.do_zero_of_workspace = TRUE;
189  Cpu_table.interrupt_stack_size = 4096;
190
191  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
192
193    /*
194     * Invalidate the cache and disable it
195     */
196    m68k_set_acr0(0);
197    m68k_set_acr1(0);
198    m68k_set_cacr(MCF5XXX_CACR_CINV);
199
200    /*
201     * Cache SDRAM
202     */
203    m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
204                  MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
205                  MCF5XXX_ACR_EN                |
206                  MCF5XXX_ACR_BWE               |
207                  MCF5XXX_ACR_SM_IGNORE);
208
209    /*
210     * Enable the cache
211     */
212    m68k_set_cacr(cacr_mode);
213
214}
215
216unsigned32 get_CPU_clock_speed(void)
217{
218    extern char _CPUClockSpeed[];
219    return( (unsigned32)_CPUClockSpeed);
220}
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