1 | /* |
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2 | * BSP startup |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Author: |
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10 | * David Fiddes, D.J@fiddes.surfaid.org |
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11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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12 | * |
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13 | * COPYRIGHT (c) 1989-1998. |
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14 | * On-Line Applications Research Corporation (OAR). |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.com/license/LICENSE. |
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19 | * |
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20 | * $Id$ |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | |
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25 | /* |
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26 | * Cannot be frozen |
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27 | */ |
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28 | void _CPU_cache_freeze_data(void) {} |
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29 | void _CPU_cache_unfreeze_data(void) {} |
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30 | void _CPU_cache_freeze_instruction(void) {} |
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31 | void _CPU_cache_unfreeze_instruction(void) {} |
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32 | |
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33 | /* |
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34 | * Write-through data cache -- flushes are unnecessary |
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35 | */ |
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36 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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37 | void _CPU_cache_flush_entire_data(void) {} |
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38 | |
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39 | void _CPU_cache_enable_instruction(void) {} |
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40 | void _CPU_cache_disable_instruction(void) {} |
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41 | void _CPU_cache_invalidate_entire_instruction(void) {} |
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42 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) {} |
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43 | |
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44 | void _CPU_cache_enable_data(void) {} |
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45 | void _CPU_cache_disable_data(void) {} |
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46 | void _CPU_cache_invalidate_entire_data(void) {} |
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47 | void _CPU_cache_invalidate_1_data_line(const void *addr) {} |
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48 | |
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49 | /* |
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50 | * bsp_start |
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51 | * |
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52 | * This routine does the bulk of the system initialisation. |
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53 | */ |
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54 | void __attribute__((weak)) bsp_start(void) |
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55 | { |
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56 | } |
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57 | |
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58 | uint32_t __attribute__((weak)) bsp_get_CPU_clock_speed(void) |
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59 | { |
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60 | #define DEF_CLOCK_SPEED 8000000.0F //8.0 MHz |
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61 | #define MCF_MFD0_2_MASK 0x7000U |
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62 | #define MCF_RFD0_2_MASK 0x0700U |
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63 | #define MCF_MFD0_2_OFFSET 4U |
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64 | |
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65 | #define SPEED_BIAS ((((MCF_CLOCK_SYNCR & MCF_MFD0_2_MASK) >> 11) + MCF_MFD0_2_OFFSET) / (float)(((MCF_CLOCK_SYNCR & MCF_RFD0_2_MASK)>>7) ? : 1.0F)) |
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66 | |
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67 | return MCF_CLOCK_SYNCR & MCF_CLOCK_SYNCR_PLLEN ? SPEED_BIAS * DEF_CLOCK_SPEED : DEF_CLOCK_SPEED; |
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68 | } |
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