source: rtems/c/src/lib/libbsp/m68k/mcf5225x/startup/bspstart.c @ 31ca0507

4.115
Last change on this file since 31ca0507 was 31ca0507, checked in by Joel Sherrill <joel.sherrill@…>, on 10/07/14 at 22:23:48

m68k/mcf5225x/startup/bspstart.c: Add include of <bsp/bootcard.h> to fix warning and clean up

  • Property mode set to 100644
File size: 1.7 KB
Line 
1/*
2 *  This routine does the bulk of the system initialisation.
3 */
4
5/*
6 *  Author:
7 *    David Fiddes, D.J@fiddes.surfaid.org
8 *    http://www.calm.hw.ac.uk/davidf/coldfire/
9 *
10 *  COPYRIGHT (c) 1989-1998.
11 *  On-Line Applications Research Corporation (OAR).
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 */
17
18#include <bsp.h>
19#include <bsp/bootcard.h>
20
21/*
22 * Cannot be frozen
23 */
24void _CPU_cache_freeze_data(void) {}
25void _CPU_cache_unfreeze_data(void) {}
26void _CPU_cache_freeze_instruction(void) {}
27void _CPU_cache_unfreeze_instruction(void) {}
28
29/*
30 * Write-through data cache -- flushes are unnecessary
31 */
32void _CPU_cache_flush_1_data_line(const void *d_addr) {}
33void _CPU_cache_flush_entire_data(void) {}
34
35void _CPU_cache_enable_instruction(void) {}
36void _CPU_cache_disable_instruction(void) {}
37void _CPU_cache_invalidate_entire_instruction(void) {}
38void _CPU_cache_invalidate_1_instruction_line(const void *addr) {}
39
40void _CPU_cache_enable_data(void) {}
41void _CPU_cache_disable_data(void) {}
42void _CPU_cache_invalidate_entire_data(void) {}
43void _CPU_cache_invalidate_1_data_line(const void *addr) {}
44
45void __attribute__((weak)) bsp_start(void)
46{
47}
48
49uint32_t  __attribute__((weak)) bsp_get_CPU_clock_speed(void)
50{
51  #define DEF_CLOCK_SPEED 8000000.0F //8.0 MHz
52  #define MCF_MFD0_2_MASK 0x7000U
53  #define MCF_RFD0_2_MASK 0x0700U
54  #define MCF_MFD0_2_OFFSET 4U
55
56  #define SPEED_BIAS  ((((MCF_CLOCK_SYNCR & MCF_MFD0_2_MASK) >> 11) + MCF_MFD0_2_OFFSET) / (float)(((MCF_CLOCK_SYNCR & MCF_RFD0_2_MASK)>>7) ? : 1.0F))
57
58  return MCF_CLOCK_SYNCR & MCF_CLOCK_SYNCR_PLLEN ? SPEED_BIAS * DEF_CLOCK_SPEED : DEF_CLOCK_SPEED;
59}
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