1 | /********************************************************************* |
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2 | * Initialisation Code for ColdFire MCF52235 Processor * |
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3 | ********************************************************************** |
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4 | Generated by ColdFire Initialisation Utility 2.10.8 |
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5 | Fri May 23 14:39:00 2008 |
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6 | |
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7 | MicroAPL Ltd makes no warranties in respect of the suitability |
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8 | of this code for any particular purpose, and accepts |
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9 | no liability for any loss arising out of its use. The person or |
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10 | persons making use of this file must make the final evaluation |
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11 | as to its suitability and correctness for a particular application. |
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12 | |
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13 | */ |
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14 | |
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15 | /* Processor/internal bus clocked at 60.00 MHz */ |
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16 | |
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17 | #include <bsp.h> |
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18 | |
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19 | /* Additional register read/write macros (missing in headers) */ |
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20 | #define MCF_CIM_CCON (*(vuint16*)(void*)(&__IPSBAR[0x00110004])) |
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21 | |
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22 | /* Bit definitions and macros for MCF_CIM_CCON */ |
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23 | #define MCF_CIM_CCON_SZEN (0x00000040) |
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24 | #define MCF_CIM_CCON_PSTEN (0x00000020) |
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25 | #define MCF_CIM_CCON_BME (0x00000008) |
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26 | #define MCF_CIM_CCON_BMT(x) (((x)&0x00000007)<<0) |
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27 | |
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28 | /* Function prototypes */ |
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29 | void init_main(void); |
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30 | static void disable_interrupts(void); |
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31 | static void disable_watchdog_timer(void); |
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32 | static void init_ipsbar(void); |
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33 | static void init_clock_config(void); |
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34 | static void init_sram(void); |
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35 | static void init_flash_controller(void); |
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36 | static void init_eport(void); |
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37 | static void init_flexcan(void); |
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38 | static void init_bus_config(void); |
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39 | static void init_power_management(void); |
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40 | static void init_dma_timers(void); |
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41 | static void init_gp_timer(void); |
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42 | static void init_interrupt_timers(void); |
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43 | static void init_real_time_clock(void); |
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44 | static void init_watchdog_timer(void); |
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45 | static void init_pin_assignments(void); |
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46 | static void init_interrupt_controller(void); |
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47 | |
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48 | /********************************************************************* |
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49 | * init_main - Main entry point for initialisation code * |
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50 | **********************************************************************/ |
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51 | void init_main(void) |
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52 | { |
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53 | /* Mask all interrupts */ |
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54 | asm("move.w #0x2700,%sr"); |
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55 | |
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56 | /* Initialise base address of peripherals, VBR, etc */ |
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57 | init_ipsbar(); |
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58 | init_clock_config(); |
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59 | |
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60 | /* Disable interrupts and watchdog timer */ |
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61 | disable_interrupts(); |
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62 | disable_watchdog_timer(); |
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63 | |
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64 | /* Initialise individual modules */ |
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65 | init_sram(); |
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66 | init_flash_controller(); |
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67 | init_eport(); |
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68 | init_flexcan(); |
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69 | init_bus_config(); |
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70 | init_power_management(); |
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71 | init_dma_timers(); |
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72 | init_gp_timer(); |
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73 | init_interrupt_timers(); |
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74 | init_real_time_clock(); |
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75 | init_watchdog_timer(); |
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76 | init_pin_assignments(); |
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77 | |
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78 | /* Initialise interrupt controller */ |
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79 | init_interrupt_controller(); |
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80 | } |
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81 | |
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82 | /********************************************************************* |
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83 | * disable_interrupts - Disable all interrupt sources * |
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84 | **********************************************************************/ |
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85 | static void disable_interrupts(void) |
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86 | { |
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87 | vuint8 *p; |
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88 | int i; |
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89 | |
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90 | /* Set ICR008-ICR063 to 0x0 */ |
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91 | p = (vuint8 *) & MCF_INTC0_ICR8; |
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92 | for (i = 8; i <= 63; i++) |
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93 | *p++ = 0x0; |
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94 | |
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95 | /* Set ICR108-ICR139 to 0x0 */ |
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96 | p = (vuint8 *) & MCF_INTC1_ICR8; |
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97 | for (i = 108; i <= 139; i++) |
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98 | *p++ = 0x0; |
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99 | } |
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100 | |
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101 | /********************************************************************* |
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102 | * disable_watchdog_timer - Disable system watchdog timer * |
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103 | **********************************************************************/ |
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104 | static void disable_watchdog_timer(void) |
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105 | { |
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106 | /* Disable Core Watchdog Timer */ |
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107 | MCF_SCM_CWCR = 0; |
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108 | } |
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109 | |
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110 | /********************************************************************* |
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111 | * init_clock_config - Clock Module * |
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112 | **********************************************************************/ |
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113 | static void init_clock_config(void) |
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114 | { |
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115 | /* Clock source is 25.0000 MHz external crystal |
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116 | Clock mode: Normal PLL mode |
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117 | Processor/Bus clock frequency = 60.00 MHz |
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118 | Loss of clock detection disabled |
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119 | Reset on loss of lock disabled |
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120 | */ |
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121 | |
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122 | /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */ |
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123 | MCF_CLOCK_CCHR = MCF_CLOCK_CCHR_PFD(0x4); |
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124 | |
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125 | /* Set RFD+1 to avoid frequency overshoot and wait for PLL to lock */ |
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126 | MCF_CLOCK_SYNCR = 0x4103; |
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127 | while ((MCF_CLOCK_SYNSR & 0x08) == 0) ; |
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128 | |
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129 | /* Set desired RFD=0 and MFD=4 and wait for PLL to lock */ |
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130 | MCF_CLOCK_SYNCR = 0x4003; |
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131 | while ((MCF_CLOCK_SYNSR & 0x08) == 0) ; |
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132 | MCF_CLOCK_SYNCR = 0x4007; /* Switch to using PLL */ |
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133 | } |
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134 | |
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135 | /********************************************************************* |
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136 | * init_ipsbar - Internal Peripheral System Base Address (IPSBAR) * |
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137 | **********************************************************************/ |
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138 | static void init_ipsbar(void) |
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139 | { |
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140 | /* Base address of internal peripherals (IPSBAR) = 0x40000000 |
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141 | |
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142 | Note: Processor powers up with IPS base address = 0x40000000 |
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143 | Write to IPS base + 0x00000000 to set new value |
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144 | */ |
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145 | *(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1; /* +1 for Enable */ |
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146 | } |
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147 | |
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148 | /********************************************************************* |
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149 | * init_flash_controller - Flash Module * |
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150 | **********************************************************************/ |
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151 | static void init_flash_controller(void) |
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152 | { |
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153 | /* Internal Flash module enabled, address = $00000000 |
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154 | Flash state machine clock = 197.37 kHz |
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155 | All access types except CPU space/interrupt acknowledge cycle allowed |
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156 | Flash is Write-Protected |
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157 | All interrupts disabled |
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158 | */ |
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159 | MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12); |
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160 | MCF_CFM_CFMMCR = 0; |
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161 | |
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162 | /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation |
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163 | This is a workaround for a hardware problem whereby a speculative |
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164 | access to the Flash occuring at the same time as an SRAM access |
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165 | can return corrupt data. |
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166 | |
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167 | This workaround can result in a 4% - 9% performance penalty. Other workarounds |
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168 | are possible for certain applications. |
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169 | |
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170 | For example, if you know that you will not be using the top 32 KB of the Flash |
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171 | you can place the SRAM base address at 0x20038000 |
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172 | |
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173 | See Device Errata for further details |
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174 | */ |
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175 | asm("move.l #0x00000161,%d0"); |
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176 | asm("movec %d0,%FLASHBAR"); |
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177 | } |
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178 | |
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179 | /********************************************************************* |
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180 | * init_eport - Edge Port Module (EPORT) * |
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181 | **********************************************************************/ |
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182 | static void init_eport(void) |
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183 | { |
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184 | /* Pins 1-15 configured as GPIO inputs */ |
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185 | MCF_EPORT_EPDDR0 = 0; |
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186 | MCF_EPORT_EPDDR1 = 0; |
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187 | MCF_EPORT_EPPAR0 = 0; |
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188 | MCF_EPORT_EPPAR1 = 0; |
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189 | MCF_EPORT_EPIER0 = 0; |
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190 | MCF_EPORT_EPIER1 = 0; |
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191 | } |
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192 | |
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193 | /********************************************************************* |
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194 | * init_flexcan - FlexCAN Module * |
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195 | **********************************************************************/ |
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196 | static void init_flexcan(void) |
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197 | { |
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198 | /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */ |
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199 | MCF_CAN_IMASK = 0; |
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200 | MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff); |
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201 | MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff); |
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202 | MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff); |
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203 | MCF_CAN_CANCTRL = 0; |
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204 | MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS | |
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205 | MCF_CAN_CANMCR_FRZ | |
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206 | MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf); |
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207 | } |
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208 | |
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209 | /********************************************************************* |
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210 | * init_bus_config - Internal Bus Arbitration * |
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211 | **********************************************************************/ |
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212 | static void init_bus_config(void) |
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213 | { |
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214 | /* Use round robin arbitration scheme |
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215 | Assigned priorities (highest first): |
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216 | Ethernet |
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217 | DMA Controller |
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218 | ColdFire Core |
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219 | DMA bandwidth control disabled |
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220 | Park on last active bus master |
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221 | */ |
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222 | MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) | |
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223 | MCF_SCM_MPARK_M2PRTY(0x2) | (0x1 << 16); |
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224 | } |
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225 | |
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226 | /********************************************************************* |
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227 | * init_sram - On-chip SRAM * |
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228 | **********************************************************************/ |
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229 | static void init_sram(void) |
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230 | { |
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231 | /* Internal SRAM module enabled, address = $20000000 |
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232 | DMA access to SRAM block disabled |
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233 | All access types (supervisor and user) allowed |
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234 | */ |
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235 | asm("move.l #0x20000001,%d0"); |
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236 | asm("movec %d0,%RAMBAR"); |
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237 | } |
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238 | |
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239 | /********************************************************************* |
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240 | * init_power_management - Power Management * |
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241 | **********************************************************************/ |
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242 | static void init_power_management(void) |
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243 | { |
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244 | /* On executing STOP instruction, processor enters RUN mode |
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245 | Mode is exited when an interrupt of level 1 or higher is received |
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246 | */ |
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247 | MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP; |
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248 | MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN; |
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249 | } |
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250 | |
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251 | /********************************************************************* |
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252 | * init_dma_timers - DMA Timer Modules * |
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253 | **********************************************************************/ |
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254 | static void init_dma_timers(void) |
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255 | { |
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256 | /* DMA Timer 0 disabled (DTMR0[RST] = 0) */ |
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257 | MCF_DTIM0_DTMR = MCF_DTIM_DTMR_CLK(0x1); |
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258 | MCF_DTIM0_DTXMR = 0; |
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259 | MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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260 | |
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261 | /* DMA Timer 1 disabled (DTMR1[RST] = 0) */ |
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262 | MCF_DTIM1_DTMR = 0; |
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263 | MCF_DTIM1_DTXMR = 0; |
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264 | MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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265 | |
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266 | /* DMA Timer 2 disabled (DTMR2[RST] = 0) */ |
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267 | MCF_DTIM2_DTMR = 0; |
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268 | MCF_DTIM2_DTXMR = 0; |
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269 | MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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270 | |
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271 | /* DMA Timer 3 disabled (DTMR3[RST] = 0) */ |
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272 | MCF_DTIM3_DTMR = MCF_DTIM_DTMR_CLK(0x1); |
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273 | MCF_DTIM3_DTXMR = 0; |
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274 | MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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275 | } |
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276 | |
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277 | /********************************************************************* |
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278 | * init_gp_timer - General Purpose Timer (GPT) Module * |
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279 | **********************************************************************/ |
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280 | static void init_gp_timer(void) |
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281 | { |
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282 | /* |
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283 | GPT disabled (GPTASCR1[GPTEN] = 0) |
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284 | Channel 0 configured as GPIO input |
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285 | Channel 1 configured as GPIO input |
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286 | Channel 2 configured as GPIO input |
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287 | Channel 3 configured as GPIO input |
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288 | */ |
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289 | MCF_GPT_GPTSCR1 = 0; |
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290 | MCF_GPT_GPTDDR = 0; |
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291 | } |
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292 | |
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293 | /********************************************************************** |
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294 | * init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules * |
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295 | ***********************************************************************/ |
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296 | static void init_interrupt_timers(void) |
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297 | { |
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298 | /* PIT0 disabled (PCSR0[EN]=0) */ |
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299 | MCF_PIT0_PCSR = 0; |
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300 | |
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301 | /* PIT1 disabled (PCSR1[EN]=0) */ |
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302 | MCF_PIT1_PCSR = 0; |
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303 | } |
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304 | |
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305 | /********************************************************************* |
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306 | * init_real_time_clock - Real-Time Clock (RTC) * |
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307 | **********************************************************************/ |
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308 | static void init_real_time_clock(void) |
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309 | { |
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310 | /* Disable the RTC */ |
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311 | MCF_RTC_CR = 0; |
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312 | } |
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313 | |
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314 | /********************************************************************* |
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315 | * init_watchdog_timer - Watchdog Timer * |
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316 | **********************************************************************/ |
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317 | static void init_watchdog_timer(void) |
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318 | { |
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319 | /* Core Watchdog Timer disabled (CWCR[CWE]=0) */ |
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320 | MCF_SCM_CWCR = 0; |
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321 | } |
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322 | |
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323 | /********************************************************************* |
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324 | * init_interrupt_controller - Interrupt Controller * |
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325 | **********************************************************************/ |
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326 | static void init_interrupt_controller(void) |
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327 | { |
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328 | /* Configured interrupt sources in order of priority... |
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329 | Level 7: External interrupt /IRQ7, (initially masked) |
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330 | Level 6: External interrupt /IRQ6, (initially masked) |
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331 | Level 5: External interrupt /IRQ5, (initially masked) |
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332 | Level 4: External interrupt /IRQ4, (initially masked) |
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333 | Level 3: External interrupt /IRQ3, (initially masked) |
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334 | Level 2: External interrupt /IRQ2, (initially masked) |
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335 | Level 1: External interrupt /IRQ1, (initially masked) |
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336 | */ |
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337 | MCF_INTC0_ICR1 = 0; |
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338 | MCF_INTC0_ICR2 = 0; |
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339 | MCF_INTC0_ICR3 = 0; |
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340 | MCF_INTC0_ICR4 = 0; |
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341 | MCF_INTC0_ICR5 = 0; |
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342 | MCF_INTC0_ICR6 = 0; |
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343 | MCF_INTC0_ICR7 = 0; |
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344 | MCF_INTC0_ICR8 = 0; |
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345 | MCF_INTC0_ICR9 = 0; |
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346 | MCF_INTC0_ICR10 = 0; |
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347 | MCF_INTC0_ICR11 = 0; |
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348 | MCF_INTC0_ICR12 = 0; |
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349 | MCF_INTC0_ICR13 = 0; |
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350 | MCF_INTC0_ICR14 = 0; |
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351 | MCF_INTC0_ICR15 = 0; |
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352 | MCF_INTC0_ICR17 = 0; |
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353 | MCF_INTC0_ICR18 = 0; |
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354 | MCF_INTC0_ICR19 = 0; |
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355 | MCF_INTC0_ICR20 = 0; |
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356 | MCF_INTC0_ICR21 = 0; |
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357 | MCF_INTC0_ICR22 = 0; |
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358 | MCF_INTC0_ICR23 = 0; |
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359 | MCF_INTC0_ICR24 = 0; |
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360 | MCF_INTC0_ICR25 = 0; |
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361 | MCF_INTC0_ICR26 = 0; |
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362 | MCF_INTC0_ICR27 = 0; |
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363 | MCF_INTC0_ICR28 = 0; |
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364 | MCF_INTC0_ICR29 = 0; |
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365 | MCF_INTC0_ICR30 = 0; |
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366 | MCF_INTC0_ICR31 = 0; |
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367 | MCF_INTC0_ICR32 = 0; |
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368 | MCF_INTC0_ICR33 = 0; |
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369 | MCF_INTC0_ICR34 = 0; |
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370 | MCF_INTC0_ICR35 = 0; |
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371 | MCF_INTC0_ICR36 = 0; |
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372 | MCF_INTC0_ICR41 = 0; |
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373 | MCF_INTC0_ICR42 = 0; |
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374 | MCF_INTC0_ICR43 = 0; |
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375 | MCF_INTC0_ICR44 = 0; |
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376 | MCF_INTC0_ICR45 = 0; |
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377 | MCF_INTC0_ICR46 = 0; |
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378 | MCF_INTC0_ICR47 = 0; |
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379 | MCF_INTC0_ICR48 = 0; |
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380 | MCF_INTC0_ICR49 = 0; |
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381 | MCF_INTC0_ICR50 = 0; |
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382 | MCF_INTC0_ICR51 = 0; |
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383 | MCF_INTC0_ICR52 = 0; |
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384 | MCF_INTC0_ICR53 = 0; |
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385 | MCF_INTC0_ICR55 = 0; |
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386 | MCF_INTC0_ICR56 = 0; |
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387 | MCF_INTC0_ICR59 = 0; |
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388 | MCF_INTC0_ICR60 = 0; |
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389 | MCF_INTC0_ICR61 = 0; |
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390 | MCF_INTC0_ICR62 = 0; |
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391 | MCF_INTC0_ICR63 = 0; |
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392 | MCF_INTC1_ICR8 = 0; |
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393 | MCF_INTC1_ICR9 = 0; |
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394 | MCF_INTC1_ICR10 = 0; |
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395 | MCF_INTC1_ICR11 = 0; |
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396 | MCF_INTC1_ICR12 = 0; |
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397 | MCF_INTC1_ICR13 = 0; |
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398 | MCF_INTC1_ICR14 = 0; |
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399 | MCF_INTC1_ICR15 = 0; |
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400 | MCF_INTC1_ICR16 = 0; |
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401 | MCF_INTC1_ICR17 = 0; |
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402 | MCF_INTC1_ICR18 = 0; |
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403 | MCF_INTC1_ICR19 = 0; |
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404 | MCF_INTC1_ICR20 = 0; |
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405 | MCF_INTC1_ICR21 = 0; |
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406 | MCF_INTC1_ICR22 = 0; |
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407 | MCF_INTC1_ICR23 = 0; |
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408 | MCF_INTC1_ICR24 = 0; |
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409 | MCF_INTC1_ICR25 = 0; |
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410 | MCF_INTC1_ICR32 = 0; |
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411 | MCF_INTC1_ICR33 = 0; |
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412 | MCF_INTC1_ICR34 = 0; |
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413 | MCF_INTC1_ICR35 = 0; |
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414 | MCF_INTC1_ICR36 = 0; |
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415 | MCF_INTC1_ICR37 = 0; |
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416 | MCF_INTC1_ICR38 = 0; |
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417 | MCF_INTC1_ICR39 = 0; |
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418 | MCF_INTC0_IMRH = 0xffffffff; |
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419 | MCF_INTC0_IMRL = 0xfffffffe; |
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420 | MCF_INTC1_IMRH = 0xffffffff; |
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421 | MCF_INTC1_IMRL = 0xfffffffe; |
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422 | } |
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423 | |
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424 | /********************************************************************* |
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425 | * init_pin_assignments - Pin Assignment and General Purpose I/O * |
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426 | **********************************************************************/ |
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427 | static void init_pin_assignments(void) |
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428 | { |
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429 | /* Pin assignments for port NQ |
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430 | Pins NQ7-NQ1 : EdgePort GPIO/IRQ |
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431 | */ |
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432 | MCF_GPIO_DDRNQ = 0; |
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433 | MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) | |
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434 | MCF_GPIO_PNQPAR_PNQPAR6(0x1) | |
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435 | MCF_GPIO_PNQPAR_PNQPAR5(0x1) | |
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436 | MCF_GPIO_PNQPAR_PNQPAR4(0x1) | |
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437 | MCF_GPIO_PNQPAR_PNQPAR3(0x1) | |
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438 | MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1); |
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439 | |
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440 | /* Pin assignments for port GP |
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441 | Pins PG7-PG0 : EdgePort GPIO/IRQ |
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442 | */ |
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443 | MCF_GPIO_DDRGP = 0; |
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444 | MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 | |
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445 | MCF_GPIO_PGPPAR_PGPPAR6 | |
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446 | MCF_GPIO_PGPPAR_PGPPAR5 | |
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447 | MCF_GPIO_PGPPAR_PGPPAR4 | |
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448 | MCF_GPIO_PGPPAR_PGPPAR3 | |
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449 | MCF_GPIO_PGPPAR_PGPPAR2 | |
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450 | MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0; |
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451 | |
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452 | /* Pin assignments for port DD |
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453 | Pin DD7 : DDATA[3] |
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454 | Pin DD6 : DDATA[2] |
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455 | Pin DD5 : DDATA[1] |
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456 | Pin DD4 : DDATA[0] |
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457 | Pin DD3 : PST[3] |
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458 | Pin DD2 : PST[2] |
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459 | Pin DD1 : PST[1] |
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460 | Pin DD0 : PST[0] |
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461 | CCON[PSTEN] = 1 to enable PST/DDATA function |
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462 | */ |
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463 | MCF_GPIO_DDRDD = 0; |
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464 | MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 | |
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465 | MCF_GPIO_PDDPAR_PDDPAR6 | |
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466 | MCF_GPIO_PDDPAR_PDDPAR5 | |
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467 | MCF_GPIO_PDDPAR_PDDPAR4 | |
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468 | MCF_GPIO_PDDPAR_PDDPAR3 | |
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469 | MCF_GPIO_PDDPAR_PDDPAR2 | |
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470 | MCF_GPIO_PDDPAR_PDDPAR1 | MCF_GPIO_PDDPAR_PDDPAR0; |
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471 | MCF_CIM_CCON = 0x0021; |
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472 | |
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473 | /* Pin assignments for port AN |
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474 | Pins are all GPIO inputs |
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475 | */ |
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476 | MCF_GPIO_DDRAN = 0; |
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477 | MCF_GPIO_PANPAR = 0; |
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478 | |
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479 | /* Pin assignments for port AS |
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480 | Pins are all GPIO inputs |
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481 | */ |
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482 | MCF_GPIO_DDRAS = 0; |
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483 | MCF_GPIO_PASPAR = 0; |
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484 | |
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485 | /* Pin assignments for port LD |
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486 | Pins are all GPIO inputs |
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487 | */ |
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488 | MCF_GPIO_DDRLD = 0; |
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489 | MCF_GPIO_PLDPAR = 0; |
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490 | |
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491 | /* Pin assignments for port QS |
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492 | Pins are all GPIO inputs |
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493 | */ |
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494 | MCF_GPIO_DDRQS = 0; |
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495 | MCF_GPIO_PQSPAR = 0; |
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496 | |
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497 | /* Pin assignments for port TA |
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498 | Pins are all GPIO inputs |
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499 | */ |
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500 | MCF_GPIO_DDRTA = 0; |
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501 | MCF_GPIO_PTAPAR = 0; |
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502 | |
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503 | /* Pin assignments for port TC |
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504 | Pins are all GPIO inputs |
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505 | */ |
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506 | MCF_GPIO_DDRTC = 0; |
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507 | MCF_GPIO_PTCPAR = 0; |
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508 | |
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509 | /* Pin assignments for port TD |
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510 | Pins are all GPIO inputs |
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511 | */ |
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512 | MCF_GPIO_DDRTD = 0; |
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513 | MCF_GPIO_PTDPAR = 0; |
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514 | |
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515 | /* Pin assignments for port UA |
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516 | Pin UA3 : UART 0 clear-to-send, UCTS0 |
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517 | Pin UA2 : UART 0 request-to-send, URTS0 |
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518 | Pin UA1 : UART 0 receive data, URXD0 |
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519 | Pin UA0 : UART 0 transmit data, UTXD0 |
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520 | */ |
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521 | MCF_GPIO_DDRUA = 0; |
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522 | MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) | |
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523 | MCF_GPIO_PUAPAR_PUAPAR2(0x1) | |
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524 | MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1); |
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525 | |
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526 | /* Pin assignments for port UB |
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527 | Pin UB3 : UART 1 clear-to-send, UCTS1 |
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528 | Pin UB2 : UART 1 request-to-send, URTS1 |
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529 | Pin UB1 : UART 1 receive data, URXD1 |
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530 | Pin UB0 : UART 1 transmit data, UTXD1 |
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531 | */ |
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532 | MCF_GPIO_DDRUB = 0; |
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533 | MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) | |
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534 | MCF_GPIO_PUBPAR_PUBPAR2(0x1) | |
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535 | MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1); |
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536 | |
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537 | /* Pin assignments for port UC |
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538 | Pin UC3 : UART 2 clear-to-send, UCTS2 |
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539 | Pin UC2 : UART 2 request-to-send, URTS2 |
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540 | Pin UC1 : UART 2 receive data, URXD2 |
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541 | Pin UC0 : UART 2 transmit data, UTXD2 |
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542 | */ |
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543 | MCF_GPIO_DDRUC = 0; |
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544 | MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 | |
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545 | MCF_GPIO_PUCPAR_PUCPAR2 | |
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546 | MCF_GPIO_PUCPAR_PUCPAR1 | MCF_GPIO_PUCPAR_PUCPAR0; |
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547 | |
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548 | /* Configure drive strengths */ |
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549 | MCF_GPIO_PDSRH = 0; |
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550 | MCF_GPIO_PDSRL = 0; |
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551 | |
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552 | /* Configure Wired-OR register */ |
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553 | MCF_GPIO_PWOR = 0; |
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554 | } |
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