source: rtems/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c @ 8d26950

4.104.114.95
Last change on this file since 8d26950 was 8d26950, checked in by Chris Johns <chrisj@…>, on Jun 19, 2008 at 6:27:29 AM

2008-06-19 Matthew Riek <matthew.riek@…>

  • startup/cfinit.c, startup/init52235.c: Missed the last patch.
  • Property mode set to 100644
File size: 17.1 KB
Line 
1/*********************************************************************
2* Initialisation Code for ColdFire MCF52235 Processor                *
3**********************************************************************
4 Generated by ColdFire Initialisation Utility 2.10.8
5 Fri May 23 14:39:00 2008
6   
7 MicroAPL Ltd makes no warranties in respect of the suitability
8 of this code for any particular purpose, and accepts
9 no liability for any loss arising out of its use. The person or 
10 persons making use of this file must make the final evaluation
11 as to its suitability and correctness for a particular application.
12   
13*/
14
15/* Processor/internal bus clocked at 60.00 MHz */
16
17#include <bsp.h>
18
19/* Additional register read/write macros (missing in headers) */
20#define MCF_CIM_CCON                   (*(vuint16*)(void*)(&__IPSBAR[0x00110004]))
21
22/* Bit definitions and macros for MCF_CIM_CCON */
23#define MCF_CIM_CCON_SZEN              (0x00000040)
24#define MCF_CIM_CCON_PSTEN             (0x00000020)
25#define MCF_CIM_CCON_BME               (0x00000008)
26#define MCF_CIM_CCON_BMT(x)            (((x)&0x00000007)<<0)
27
28/* Function prototypes */
29void init_main(void);
30static void disable_interrupts(void);
31static void disable_watchdog_timer(void);
32static void init_ipsbar(void);
33static void init_clock_config(void);
34static void init_sram(void);
35static void init_flash_controller(void);
36static void init_eport(void);
37static void init_flexcan(void);
38static void init_bus_config(void);
39static void init_power_management(void);
40static void init_dma_timers(void);
41static void init_gp_timer(void);
42static void init_interrupt_timers(void);
43static void init_real_time_clock(void);
44static void init_watchdog_timer(void);
45static void init_pin_assignments(void);
46static void init_interrupt_controller(void);
47
48/*********************************************************************
49* init_main - Main entry point for initialisation code               *
50**********************************************************************/
51void init_main(void)
52{
53  /* Mask all interrupts */
54  asm("move.w   #0x2700,%sr");
55
56  /* Initialise base address of peripherals, VBR, etc */
57  init_ipsbar();
58  init_clock_config();
59
60  /* Disable interrupts and watchdog timer */
61  disable_interrupts();
62  disable_watchdog_timer();
63
64  /* Initialise individual modules */
65  init_sram();
66  init_flash_controller();
67  init_eport();
68  init_flexcan();
69  init_bus_config();
70  init_power_management();
71  init_dma_timers();
72  init_gp_timer();
73  init_interrupt_timers();
74  init_real_time_clock();
75  init_watchdog_timer();
76  init_pin_assignments();
77
78  /* Initialise interrupt controller */
79  init_interrupt_controller();
80}
81
82/*********************************************************************
83* disable_interrupts - Disable all interrupt sources                 *
84**********************************************************************/
85static void disable_interrupts(void)
86{
87  vuint8 *p;
88  int i;
89
90  /* Set ICR008-ICR063 to 0x0 */
91  p = (vuint8 *) & MCF_INTC0_ICR8;
92  for (i = 8; i <= 63; i++)
93    *p++ = 0x0;
94
95  /* Set ICR108-ICR139 to 0x0 */
96  p = (vuint8 *) & MCF_INTC1_ICR8;
97  for (i = 108; i <= 139; i++)
98    *p++ = 0x0;
99}
100
101/*********************************************************************
102* disable_watchdog_timer - Disable system watchdog timer             *
103**********************************************************************/
104static void disable_watchdog_timer(void)
105{
106  /* Disable Core Watchdog Timer */
107  MCF_SCM_CWCR = 0;
108}
109
110/*********************************************************************
111* init_clock_config - Clock Module                                   *
112**********************************************************************/
113static void init_clock_config(void)
114{
115  /* Clock source is 25.0000 MHz external crystal
116     Clock mode: Normal PLL mode
117     Processor/Bus clock frequency = 60.00 MHz
118     Loss of clock detection disabled
119     Reset on loss of lock disabled
120   */
121
122  /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */
123  MCF_CLOCK_CCHR = MCF_CLOCK_CCHR_PFD(0x4);
124
125  /* Set RFD+1 to avoid frequency overshoot and wait for PLL to lock */
126  MCF_CLOCK_SYNCR = 0x4103;
127  while ((MCF_CLOCK_SYNSR & 0x08) == 0) ;
128
129  /* Set desired RFD=0 and MFD=4 and wait for PLL to lock */
130  MCF_CLOCK_SYNCR = 0x4003;
131  while ((MCF_CLOCK_SYNSR & 0x08) == 0) ;
132  MCF_CLOCK_SYNCR = 0x4007;                       /* Switch to using PLL */
133}
134
135/*********************************************************************
136* init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
137**********************************************************************/
138static void init_ipsbar(void)
139{
140  /* Base address of internal peripherals (IPSBAR) = 0x40000000
141
142     Note: Processor powers up with IPS base address = 0x40000000
143     Write to IPS base + 0x00000000 to set new value
144   */
145  *(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1;     /* +1 for Enable */
146}
147
148/*********************************************************************
149* init_flash_controller - Flash Module                               *
150**********************************************************************/
151static void init_flash_controller(void)
152{
153  /* Internal Flash module enabled, address = $00000000
154     Flash state machine clock = 197.37 kHz
155     All access types except CPU space/interrupt acknowledge cycle allowed
156     Flash is Write-Protected
157     All interrupts disabled
158   */
159  MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12);
160  MCF_CFM_CFMMCR = 0;
161
162  /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
163     This is a workaround for a hardware problem whereby a speculative
164     access to the Flash occuring at the same time as an SRAM access
165     can return corrupt data.
166
167     This workaround can result in a 4% - 9% performance penalty. Other workarounds
168     are possible for certain applications.
169
170     For example, if you know that you will not be using the top 32 KB of the Flash 
171     you can place the SRAM base address at 0x20038000
172
173     See Device Errata for further details
174   */
175  asm("move.l   #0x00000161,%d0");
176  asm("movec    %d0,%FLASHBAR");
177}
178
179/*********************************************************************
180* init_eport - Edge Port Module (EPORT)                              *
181**********************************************************************/
182static void init_eport(void)
183{
184  /* Pins 1-15 configured as GPIO inputs */
185  MCF_EPORT_EPDDR0 = 0;
186  MCF_EPORT_EPDDR1 = 0;
187  MCF_EPORT_EPPAR0 = 0;
188  MCF_EPORT_EPPAR1 = 0;
189  MCF_EPORT_EPIER0 = 0;
190  MCF_EPORT_EPIER1 = 0;
191}
192
193/*********************************************************************
194* init_flexcan - FlexCAN Module                                      *
195**********************************************************************/
196static void init_flexcan(void)
197{
198  /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
199  MCF_CAN_IMASK = 0;
200  MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
201  MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
202  MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
203  MCF_CAN_CANCTRL = 0;
204  MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
205    MCF_CAN_CANMCR_FRZ |
206    MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
207}
208
209/*********************************************************************
210* init_bus_config - Internal Bus Arbitration                         *
211**********************************************************************/
212static void init_bus_config(void)
213{
214  /* Use round robin arbitration scheme
215     Assigned priorities (highest first):
216     Ethernet
217     DMA Controller
218     ColdFire Core
219     DMA bandwidth control disabled
220     Park on last active bus master
221   */
222  MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
223    MCF_SCM_MPARK_M2PRTY(0x2) | (0x1 << 16);
224}
225
226/*********************************************************************
227* init_sram - On-chip SRAM                                           *
228**********************************************************************/
229static void init_sram(void)
230{
231  /* Internal SRAM module enabled, address = $20000000
232     DMA access to SRAM block disabled
233     All access types (supervisor and user) allowed
234   */
235  asm("move.l   #0x20000001,%d0");
236  asm("movec    %d0,%RAMBAR");
237}
238
239/*********************************************************************
240* init_power_management - Power Management                           *
241**********************************************************************/
242static void init_power_management(void)
243{
244  /* On executing STOP instruction, processor enters RUN mode
245     Mode is exited when an interrupt of level 1 or higher is received
246   */
247  MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
248  MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN;
249}
250
251/*********************************************************************
252* init_dma_timers - DMA Timer Modules                                *
253**********************************************************************/
254static void init_dma_timers(void)
255{
256  /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
257  MCF_DTIM0_DTMR = MCF_DTIM_DTMR_CLK(0x1);
258  MCF_DTIM0_DTXMR = 0;
259  MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
260
261  /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
262  MCF_DTIM1_DTMR = 0;
263  MCF_DTIM1_DTXMR = 0;
264  MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
265
266  /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
267  MCF_DTIM2_DTMR = 0;
268  MCF_DTIM2_DTXMR = 0;
269  MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
270
271  /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
272  MCF_DTIM3_DTMR = MCF_DTIM_DTMR_CLK(0x1);
273  MCF_DTIM3_DTXMR = 0;
274  MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
275}
276
277/*********************************************************************
278* init_gp_timer - General Purpose Timer (GPT) Module                 *
279**********************************************************************/
280static void init_gp_timer(void)
281{
282  /*   
283     GPT disabled (GPTASCR1[GPTEN] = 0)
284     Channel 0 configured as GPIO input
285     Channel 1 configured as GPIO input
286     Channel 2 configured as GPIO input
287     Channel 3 configured as GPIO input
288   */
289  MCF_GPT_GPTSCR1 = 0;
290  MCF_GPT_GPTDDR = 0;
291}
292
293/**********************************************************************
294* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
295***********************************************************************/
296static void init_interrupt_timers(void)
297{
298  /* PIT0 disabled (PCSR0[EN]=0) */
299  MCF_PIT0_PCSR = 0;
300
301  /* PIT1 disabled (PCSR1[EN]=0) */
302  MCF_PIT1_PCSR = 0;
303}
304
305/*********************************************************************
306* init_real_time_clock - Real-Time Clock (RTC)                       *
307**********************************************************************/
308static void init_real_time_clock(void)
309{
310  /* Disable the RTC */
311  MCF_RTC_CR = 0;
312}
313
314/*********************************************************************
315* init_watchdog_timer - Watchdog Timer                               *
316**********************************************************************/
317static void init_watchdog_timer(void)
318{
319  /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
320  MCF_SCM_CWCR = 0;
321}
322
323/*********************************************************************
324* init_interrupt_controller - Interrupt Controller                   *
325**********************************************************************/
326static void init_interrupt_controller(void)
327{
328  /* Configured interrupt sources in order of priority...
329     Level 7:  External interrupt /IRQ7, (initially masked)
330     Level 6:  External interrupt /IRQ6, (initially masked)
331     Level 5:  External interrupt /IRQ5, (initially masked)
332     Level 4:  External interrupt /IRQ4, (initially masked)
333     Level 3:  External interrupt /IRQ3, (initially masked)
334     Level 2:  External interrupt /IRQ2, (initially masked)
335     Level 1:  External interrupt /IRQ1, (initially masked)
336   */
337  MCF_INTC0_ICR1 = 0;
338  MCF_INTC0_ICR2 = 0;
339  MCF_INTC0_ICR3 = 0;
340  MCF_INTC0_ICR4 = 0;
341  MCF_INTC0_ICR5 = 0;
342  MCF_INTC0_ICR6 = 0;
343  MCF_INTC0_ICR7 = 0;
344  MCF_INTC0_ICR8 = 0;
345  MCF_INTC0_ICR9 = 0;
346  MCF_INTC0_ICR10 = 0;
347  MCF_INTC0_ICR11 = 0;
348  MCF_INTC0_ICR12 = 0;
349  MCF_INTC0_ICR13 = 0;
350  MCF_INTC0_ICR14 = 0;
351  MCF_INTC0_ICR15 = 0;
352  MCF_INTC0_ICR17 = 0;
353  MCF_INTC0_ICR18 = 0;
354  MCF_INTC0_ICR19 = 0;
355  MCF_INTC0_ICR20 = 0;
356  MCF_INTC0_ICR21 = 0;
357  MCF_INTC0_ICR22 = 0;
358  MCF_INTC0_ICR23 = 0;
359  MCF_INTC0_ICR24 = 0;
360  MCF_INTC0_ICR25 = 0;
361  MCF_INTC0_ICR26 = 0;
362  MCF_INTC0_ICR27 = 0;
363  MCF_INTC0_ICR28 = 0;
364  MCF_INTC0_ICR29 = 0;
365  MCF_INTC0_ICR30 = 0;
366  MCF_INTC0_ICR31 = 0;
367  MCF_INTC0_ICR32 = 0;
368  MCF_INTC0_ICR33 = 0;
369  MCF_INTC0_ICR34 = 0;
370  MCF_INTC0_ICR35 = 0;
371  MCF_INTC0_ICR36 = 0;
372  MCF_INTC0_ICR41 = 0;
373  MCF_INTC0_ICR42 = 0;
374  MCF_INTC0_ICR43 = 0;
375  MCF_INTC0_ICR44 = 0;
376  MCF_INTC0_ICR45 = 0;
377  MCF_INTC0_ICR46 = 0;
378  MCF_INTC0_ICR47 = 0;
379  MCF_INTC0_ICR48 = 0;
380  MCF_INTC0_ICR49 = 0;
381  MCF_INTC0_ICR50 = 0;
382  MCF_INTC0_ICR51 = 0;
383  MCF_INTC0_ICR52 = 0;
384  MCF_INTC0_ICR53 = 0;
385  MCF_INTC0_ICR55 = 0;
386  MCF_INTC0_ICR56 = 0;
387  MCF_INTC0_ICR59 = 0;
388  MCF_INTC0_ICR60 = 0;
389  MCF_INTC0_ICR61 = 0;
390  MCF_INTC0_ICR62 = 0;
391  MCF_INTC0_ICR63 = 0;
392  MCF_INTC1_ICR8 = 0;
393  MCF_INTC1_ICR9 = 0;
394  MCF_INTC1_ICR10 = 0;
395  MCF_INTC1_ICR11 = 0;
396  MCF_INTC1_ICR12 = 0;
397  MCF_INTC1_ICR13 = 0;
398  MCF_INTC1_ICR14 = 0;
399  MCF_INTC1_ICR15 = 0;
400  MCF_INTC1_ICR16 = 0;
401  MCF_INTC1_ICR17 = 0;
402  MCF_INTC1_ICR18 = 0;
403  MCF_INTC1_ICR19 = 0;
404  MCF_INTC1_ICR20 = 0;
405  MCF_INTC1_ICR21 = 0;
406  MCF_INTC1_ICR22 = 0;
407  MCF_INTC1_ICR23 = 0;
408  MCF_INTC1_ICR24 = 0;
409  MCF_INTC1_ICR25 = 0;
410  MCF_INTC1_ICR32 = 0;
411  MCF_INTC1_ICR33 = 0;
412  MCF_INTC1_ICR34 = 0;
413  MCF_INTC1_ICR35 = 0;
414  MCF_INTC1_ICR36 = 0;
415  MCF_INTC1_ICR37 = 0;
416  MCF_INTC1_ICR38 = 0;
417  MCF_INTC1_ICR39 = 0;
418  MCF_INTC0_IMRH = 0xffffffff;
419  MCF_INTC0_IMRL = 0xfffffffe;
420  MCF_INTC1_IMRH = 0xffffffff;
421  MCF_INTC1_IMRL = 0xfffffffe;
422}
423
424/*********************************************************************
425* init_pin_assignments - Pin Assignment and General Purpose I/O      *
426**********************************************************************/
427static void init_pin_assignments(void)
428{
429  /* Pin assignments for port NQ
430     Pins NQ7-NQ1 : EdgePort GPIO/IRQ
431   */
432  MCF_GPIO_DDRNQ = 0;
433  MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) |
434    MCF_GPIO_PNQPAR_PNQPAR6(0x1) |
435    MCF_GPIO_PNQPAR_PNQPAR5(0x1) |
436    MCF_GPIO_PNQPAR_PNQPAR4(0x1) |
437    MCF_GPIO_PNQPAR_PNQPAR3(0x1) |
438    MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1);
439
440  /* Pin assignments for port GP
441     Pins PG7-PG0 : EdgePort GPIO/IRQ
442   */
443  MCF_GPIO_DDRGP = 0;
444  MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 |
445    MCF_GPIO_PGPPAR_PGPPAR6 |
446    MCF_GPIO_PGPPAR_PGPPAR5 |
447    MCF_GPIO_PGPPAR_PGPPAR4 |
448    MCF_GPIO_PGPPAR_PGPPAR3 |
449    MCF_GPIO_PGPPAR_PGPPAR2 |
450    MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0;
451
452  /* Pin assignments for port DD
453     Pin DD7 : DDATA[3]
454     Pin DD6 : DDATA[2]
455     Pin DD5 : DDATA[1]
456     Pin DD4 : DDATA[0]
457     Pin DD3 : PST[3]
458     Pin DD2 : PST[2]
459     Pin DD1 : PST[1]
460     Pin DD0 : PST[0]
461     CCON[PSTEN] = 1 to enable PST/DDATA function
462   */
463  MCF_GPIO_DDRDD = 0;
464  MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 |
465    MCF_GPIO_PDDPAR_PDDPAR6 |
466    MCF_GPIO_PDDPAR_PDDPAR5 |
467    MCF_GPIO_PDDPAR_PDDPAR4 |
468    MCF_GPIO_PDDPAR_PDDPAR3 |
469    MCF_GPIO_PDDPAR_PDDPAR2 |
470    MCF_GPIO_PDDPAR_PDDPAR1 | MCF_GPIO_PDDPAR_PDDPAR0;
471  MCF_CIM_CCON = 0x0021;
472
473  /* Pin assignments for port AN
474     Pins are all GPIO inputs
475   */
476  MCF_GPIO_DDRAN = 0;
477  MCF_GPIO_PANPAR = 0;
478
479  /* Pin assignments for port AS
480     Pins are all GPIO inputs
481   */
482  MCF_GPIO_DDRAS = 0;
483  MCF_GPIO_PASPAR = 0;
484
485  /* Pin assignments for port LD
486     Pins are all GPIO inputs
487   */
488  MCF_GPIO_DDRLD = 0;
489  MCF_GPIO_PLDPAR = 0;
490
491  /* Pin assignments for port QS
492     Pins are all GPIO inputs
493   */
494  MCF_GPIO_DDRQS = 0;
495  MCF_GPIO_PQSPAR = 0;
496
497  /* Pin assignments for port TA
498     Pins are all GPIO inputs
499   */
500  MCF_GPIO_DDRTA = 0;
501  MCF_GPIO_PTAPAR = 0;
502
503  /* Pin assignments for port TC
504     Pins are all GPIO inputs
505   */
506  MCF_GPIO_DDRTC = 0;
507  MCF_GPIO_PTCPAR = 0;
508
509  /* Pin assignments for port TD
510     Pins are all GPIO inputs
511   */
512  MCF_GPIO_DDRTD = 0;
513  MCF_GPIO_PTDPAR = 0;
514
515  /* Pin assignments for port UA
516     Pin UA3 : UART 0 clear-to-send, UCTS0
517     Pin UA2 : UART 0 request-to-send, URTS0
518     Pin UA1 : UART 0 receive data, URXD0
519     Pin UA0 : UART 0 transmit data, UTXD0
520   */
521  MCF_GPIO_DDRUA = 0;
522  MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) |
523    MCF_GPIO_PUAPAR_PUAPAR2(0x1) |
524    MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1);
525
526  /* Pin assignments for port UB
527     Pin UB3 : UART 1 clear-to-send, UCTS1
528     Pin UB2 : UART 1 request-to-send, URTS1
529     Pin UB1 : UART 1 receive data, URXD1
530     Pin UB0 : UART 1 transmit data, UTXD1
531   */
532  MCF_GPIO_DDRUB = 0;
533  MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) |
534    MCF_GPIO_PUBPAR_PUBPAR2(0x1) |
535    MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1);
536
537  /* Pin assignments for port UC
538     Pin UC3 : UART 2 clear-to-send, UCTS2
539     Pin UC2 : UART 2 request-to-send, URTS2
540     Pin UC1 : UART 2 receive data, URXD2
541     Pin UC0 : UART 2 transmit data, UTXD2
542   */
543  MCF_GPIO_DDRUC = 0;
544  MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 |
545    MCF_GPIO_PUCPAR_PUCPAR2 |
546    MCF_GPIO_PUCPAR_PUCPAR1 | MCF_GPIO_PUCPAR_PUCPAR0;
547
548  /* Configure drive strengths */
549  MCF_GPIO_PDSRH = 0;
550  MCF_GPIO_PDSRL = 0;
551
552  /* Configure Wired-OR register */
553  MCF_GPIO_PWOR = 0;
554}
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