source: rtems/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c @ 3aac2db

4.104.114.95
Last change on this file since 3aac2db was 3aac2db, checked in by Chris Johns <chrisj@…>, on Jun 11, 2008 at 7:59:03 AM

2008-06-10 Matthew Riek <matthew.riek@…>

  • .cvsignore, ChangeLog?, Makefile.am, README, bsp_specs, clock/clock.c, configure.ac, console/console.c, gdb-init, include/bsp.h, include/bspopts.h.in, include/coverhd.h, include/tm27.h, preinstall.am, start/start.S, startup/bspclean.c, startup/bspstart.c, startup/cfinit.c, startup/init52235.c, startup/linkcmds, timer/timer.c: New.
  • Property mode set to 100644
File size: 19.2 KB
Line 
1/*********************************************************************
2* Initialisation Code for ColdFire MCF52235 Processor                *
3**********************************************************************
4 Generated by ColdFire Initialisation Utility 2.10.8
5 Fri May 23 14:39:00 2008
6   
7 MicroAPL Ltd makes no warranties in respect of the suitability
8 of this code for any particular purpose, and accepts
9 no liability for any loss arising out of its use. The person or 
10 persons making use of this file must make the final evaluation
11 as to its suitability and correctness for a particular application.
12   
13*/
14
15/* Processor/internal bus clocked at 60.00 MHz */
16
17#include <mcf52235/mcf52235.h>
18
19/* Additional register read/write macros (missing in headers) */
20#define MCF_CIM_CCON                   (*(vuint16*)(void*)(&__IPSBAR[0x00110004]))
21
22/* Bit definitions and macros for MCF_CIM_CCON */
23#define MCF_CIM_CCON_SZEN              (0x00000040)
24#define MCF_CIM_CCON_PSTEN             (0x00000020)
25#define MCF_CIM_CCON_BME               (0x00000008)
26#define MCF_CIM_CCON_BMT(x)            (((x)&0x00000007)<<0)
27
28/* Function prototypes */
29void init_main (void); 
30static void disable_interrupts (void);
31static void disable_watchdog_timer (void);
32static void init_ipsbar (void);
33static void init_clock_config (void);
34static void init_sram (void);
35static void init_flash_controller (void);
36static void init_eport (void);
37static void init_flexcan (void);
38static void init_bus_config (void);
39static void init_power_management (void);
40static void init_dma_timers (void);
41static void init_gp_timer (void);
42static void init_interrupt_timers (void);
43static void init_real_time_clock (void);
44static void init_watchdog_timer (void);
45static void init_pin_assignments (void);
46static void init_interrupt_controller (void);
47
48/*********************************************************************
49* init_main - Main entry point for initialisation code               *
50**********************************************************************/
51void init_main (void)
52{
53    /* Mask all interrupts */
54    asm("move.w   #0x2700,%sr");
55
56    /* Initialise base address of peripherals, VBR, etc */
57    init_ipsbar ();
58    init_clock_config ();
59
60    /* Disable interrupts and watchdog timer */
61    disable_interrupts ();
62    disable_watchdog_timer ();
63
64    /* Initialise individual modules */
65    init_sram ();
66    init_flash_controller ();
67    init_eport ();
68    init_flexcan ();
69    init_bus_config ();
70    init_power_management ();
71    init_dma_timers ();
72    init_gp_timer ();
73    init_interrupt_timers ();
74    init_real_time_clock ();
75    init_watchdog_timer ();
76    init_pin_assignments ();
77
78    /* Initialise interrupt controller */
79    init_interrupt_controller ();
80}
81
82/*********************************************************************
83* disable_interrupts - Disable all interrupt sources                 *
84**********************************************************************/
85static void disable_interrupts (void)
86{
87    vuint8  *p;
88    int     i;
89
90    /* Set ICR008-ICR063 to 0x0 */
91    p = (vuint8 *) &MCF_INTC0_ICR8;
92    for (i = 8; i <= 63; i++)
93        *p++ = 0x0;
94
95    /* Set ICR108-ICR139 to 0x0 */
96    p = (vuint8 *) &MCF_INTC1_ICR8;
97    for (i = 108; i <= 139; i++)
98        *p++ = 0x0;
99}
100
101/*********************************************************************
102* disable_watchdog_timer - Disable system watchdog timer             *
103**********************************************************************/
104static void disable_watchdog_timer (void)
105{
106    /* Disable Core Watchdog Timer */
107    MCF_SCM_CWCR = 0;
108}
109
110/*********************************************************************
111* init_clock_config - Clock Module                                   *
112**********************************************************************/
113static void init_clock_config (void)
114{
115    /* Clock source is 25.0000 MHz external crystal
116       Clock mode: Normal PLL mode
117       Processor/Bus clock frequency = 60.00 MHz
118       Loss of clock detection disabled
119       Reset on loss of lock disabled
120    */
121
122    /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */
123    MCF_CLOCK_CCHR = MCF_CLOCK_CCHR_PFD(0x4);
124
125    /* Set RFD+1 to avoid frequency overshoot and wait for PLL to lock */
126    MCF_CLOCK_SYNCR = 0x4103;
127    while ((MCF_CLOCK_SYNSR & 0x08) == 0)
128        ;
129
130    /* Set desired RFD=0 and MFD=4 and wait for PLL to lock */
131    MCF_CLOCK_SYNCR = 0x4003;
132    while ((MCF_CLOCK_SYNSR & 0x08) == 0)
133        ;
134    MCF_CLOCK_SYNCR = 0x4007;                     /* Switch to using PLL */
135}
136
137/*********************************************************************
138* init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
139**********************************************************************/
140static void init_ipsbar (void)
141{
142    /* Base address of internal peripherals (IPSBAR) = 0x40000000
143         
144       Note: Processor powers up with IPS base address = 0x40000000
145             Write to IPS base + 0x00000000 to set new value
146    */
147    * (vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1; /* +1 for Enable */
148}
149
150/*********************************************************************
151* init_flash_controller - Flash Module                               *
152**********************************************************************/
153static void init_flash_controller (void)
154{
155    /* Internal Flash module enabled, address = $00000000
156       Flash state machine clock = 197.37 kHz
157       All access types except CPU space/interrupt acknowledge cycle allowed
158       Flash is Write-Protected
159       All interrupts disabled
160    */
161    MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 |
162                      MCF_CFM_CFMCLKD_DIV(0x12);
163    MCF_CFM_CFMMCR = 0;
164
165    /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
166       This is a workaround for a hardware problem whereby a speculative
167       access to the Flash occuring at the same time as an SRAM access
168       can return corrupt data.
169         
170       This workaround can result in a 4% - 9% performance penalty. Other workarounds
171       are possible for certain applications.
172         
173       For example, if you know that you will not be using the top 32 KB of the Flash 
174       you can place the SRAM base address at 0x20038000
175         
176       See Device Errata for further details
177    */
178    asm("move.l   #0x00000161,%d0");
179    asm("movec    %d0,%FLASHBAR");
180}
181
182/*********************************************************************
183* init_eport - Edge Port Module (EPORT)                              *
184**********************************************************************/
185static void init_eport (void)
186{
187    /* Pins 1-15 configured as GPIO inputs */
188    MCF_EPORT_EPDDR0 = 0;
189    MCF_EPORT_EPDDR1 = 0;
190    MCF_EPORT_EPPAR0 = 0;
191    MCF_EPORT_EPPAR1 = 0;
192    MCF_EPORT_EPIER0 = 0;
193    MCF_EPORT_EPIER1 = 0;
194}
195
196/*********************************************************************
197* init_flexcan - FlexCAN Module                                      *
198**********************************************************************/
199static void init_flexcan (void)
200{
201    /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
202    MCF_CAN_IMASK = 0;
203    MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
204    MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
205    MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
206    MCF_CAN_CANCTRL = 0;
207    MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS       |
208                     MCF_CAN_CANMCR_FRZ        |
209                     MCF_CAN_CANMCR_HALT       |
210                     MCF_CAN_CANMCR_SUPV       |
211                     MCF_CAN_CANMCR_MAXMB(0xf);
212}
213
214/*********************************************************************
215* init_bus_config - Internal Bus Arbitration                         *
216**********************************************************************/
217static void init_bus_config (void)
218{
219    /* Use round robin arbitration scheme
220       Assigned priorities (highest first):
221           Ethernet
222           DMA Controller
223           ColdFire Core
224       DMA bandwidth control disabled
225       Park on last active bus master
226    */
227    MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
228                    MCF_SCM_MPARK_M2PRTY(0x2) |
229                    (0x1 << 16);
230}
231
232/*********************************************************************
233* init_sram - On-chip SRAM                                           *
234**********************************************************************/
235static void init_sram (void)
236{
237    /* Internal SRAM module enabled, address = $20000000
238       DMA access to SRAM block disabled
239       All access types (supervisor and user) allowed
240    */
241    asm("move.l   #0x20000001,%d0");
242    asm("movec    %d0,%RAMBAR");
243}
244
245/*********************************************************************
246* init_power_management - Power Management                           *
247**********************************************************************/
248static void init_power_management (void)
249{
250    /* On executing STOP instruction, processor enters RUN mode
251       Mode is exited when an interrupt of level 1 or higher is received
252    */
253    MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
254    MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN;
255}
256
257/*********************************************************************
258* init_dma_timers - DMA Timer Modules                                *
259**********************************************************************/
260static void init_dma_timers (void)
261{
262    /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
263    MCF_DTIM0_DTMR = MCF_DTIM_DTMR_CLK(0x1);
264    MCF_DTIM0_DTXMR = 0;
265    MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
266
267    /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
268    MCF_DTIM1_DTMR = 0;
269    MCF_DTIM1_DTXMR = 0;
270    MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
271
272    /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
273    MCF_DTIM2_DTMR = 0;
274    MCF_DTIM2_DTXMR = 0;
275    MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
276
277    /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
278    MCF_DTIM3_DTMR = MCF_DTIM_DTMR_CLK(0x1);
279    MCF_DTIM3_DTXMR = 0;
280    MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
281}
282
283/*********************************************************************
284* init_gp_timer - General Purpose Timer (GPT) Module                 *
285**********************************************************************/
286static void init_gp_timer (void)
287{
288    /*   
289       GPT disabled (GPTASCR1[GPTEN] = 0)
290       Channel 0 configured as GPIO input
291       Channel 1 configured as GPIO input
292       Channel 2 configured as GPIO input
293       Channel 3 configured as GPIO input
294    */
295    MCF_GPT_GPTSCR1 = 0;
296    MCF_GPT_GPTDDR = 0;
297}
298
299/**********************************************************************
300* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
301***********************************************************************/
302static void init_interrupt_timers (void)
303{
304    /* PIT0 disabled (PCSR0[EN]=0) */
305    MCF_PIT0_PCSR = 0;
306
307    /* PIT1 disabled (PCSR1[EN]=0) */
308    MCF_PIT1_PCSR = 0;
309}
310
311/*********************************************************************
312* init_real_time_clock - Real-Time Clock (RTC)                       *
313**********************************************************************/
314static void init_real_time_clock (void)
315{
316    /* Disable the RTC */
317    MCF_RTC_CR = 0;
318}
319
320/*********************************************************************
321* init_watchdog_timer - Watchdog Timer                               *
322**********************************************************************/
323static void init_watchdog_timer (void)
324{
325    /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
326    MCF_SCM_CWCR = 0;
327}
328
329/*********************************************************************
330* init_interrupt_controller - Interrupt Controller                   *
331**********************************************************************/
332static void init_interrupt_controller (void)
333{
334    /* Configured interrupt sources in order of priority...
335       Level 7:  External interrupt /IRQ7, (initially masked)
336       Level 6:  External interrupt /IRQ6, (initially masked)
337       Level 5:  External interrupt /IRQ5, (initially masked)
338       Level 4:  External interrupt /IRQ4, (initially masked)
339       Level 3:  External interrupt /IRQ3, (initially masked)
340       Level 2:  External interrupt /IRQ2, (initially masked)
341       Level 1:  External interrupt /IRQ1, (initially masked)
342    */
343    MCF_INTC0_ICR1 = 0;
344    MCF_INTC0_ICR2 = 0;
345    MCF_INTC0_ICR3 = 0;
346    MCF_INTC0_ICR4 = 0;
347    MCF_INTC0_ICR5 = 0;
348    MCF_INTC0_ICR6 = 0;
349    MCF_INTC0_ICR7 = 0;
350    MCF_INTC0_ICR8 = 0;
351    MCF_INTC0_ICR9 = 0;
352    MCF_INTC0_ICR10 = 0;
353    MCF_INTC0_ICR11 = 0;
354    MCF_INTC0_ICR12 = 0;
355    MCF_INTC0_ICR13 = 0;
356    MCF_INTC0_ICR14 = 0;
357    MCF_INTC0_ICR15 = 0;
358    MCF_INTC0_ICR17 = 0;
359    MCF_INTC0_ICR18 = 0;
360    MCF_INTC0_ICR19 = 0;
361    MCF_INTC0_ICR20 = 0;
362    MCF_INTC0_ICR21 = 0;
363    MCF_INTC0_ICR22 = 0;
364    MCF_INTC0_ICR23 = 0;
365    MCF_INTC0_ICR24 = 0;
366    MCF_INTC0_ICR25 = 0;
367    MCF_INTC0_ICR26 = 0;
368    MCF_INTC0_ICR27 = 0;
369    MCF_INTC0_ICR28 = 0;
370    MCF_INTC0_ICR29 = 0;
371    MCF_INTC0_ICR30 = 0;
372    MCF_INTC0_ICR31 = 0;
373    MCF_INTC0_ICR32 = 0;
374    MCF_INTC0_ICR33 = 0;
375    MCF_INTC0_ICR34 = 0;
376    MCF_INTC0_ICR35 = 0;
377    MCF_INTC0_ICR36 = 0;
378    MCF_INTC0_ICR41 = 0;
379    MCF_INTC0_ICR42 = 0;
380    MCF_INTC0_ICR43 = 0;
381    MCF_INTC0_ICR44 = 0;
382    MCF_INTC0_ICR45 = 0;
383    MCF_INTC0_ICR46 = 0;
384    MCF_INTC0_ICR47 = 0;
385    MCF_INTC0_ICR48 = 0;
386    MCF_INTC0_ICR49 = 0;
387    MCF_INTC0_ICR50 = 0;
388    MCF_INTC0_ICR51 = 0;
389    MCF_INTC0_ICR52 = 0;
390    MCF_INTC0_ICR53 = 0;
391    MCF_INTC0_ICR55 = 0;
392    MCF_INTC0_ICR56 = 0;
393    MCF_INTC0_ICR59 = 0;
394    MCF_INTC0_ICR60 = 0;
395    MCF_INTC0_ICR61 = 0;
396    MCF_INTC0_ICR62 = 0;
397    MCF_INTC0_ICR63 = 0;
398    MCF_INTC1_ICR8 = 0;
399    MCF_INTC1_ICR9 = 0;
400    MCF_INTC1_ICR10 = 0;
401    MCF_INTC1_ICR11 = 0;
402    MCF_INTC1_ICR12 = 0;
403    MCF_INTC1_ICR13 = 0;
404    MCF_INTC1_ICR14 = 0;
405    MCF_INTC1_ICR15 = 0;
406    MCF_INTC1_ICR16 = 0;
407    MCF_INTC1_ICR17 = 0;
408    MCF_INTC1_ICR18 = 0;
409    MCF_INTC1_ICR19 = 0;
410    MCF_INTC1_ICR20 = 0;
411    MCF_INTC1_ICR21 = 0;
412    MCF_INTC1_ICR22 = 0;
413    MCF_INTC1_ICR23 = 0;
414    MCF_INTC1_ICR24 = 0;
415    MCF_INTC1_ICR25 = 0;
416    MCF_INTC1_ICR32 = 0;
417    MCF_INTC1_ICR33 = 0;
418    MCF_INTC1_ICR34 = 0;
419    MCF_INTC1_ICR35 = 0;
420    MCF_INTC1_ICR36 = 0;
421    MCF_INTC1_ICR37 = 0;
422    MCF_INTC1_ICR38 = 0;
423    MCF_INTC1_ICR39 = 0;
424    MCF_INTC0_IMRH = 0xffffffff;
425    MCF_INTC0_IMRL = 0xfffffffe;
426    MCF_INTC1_IMRH = 0xffffffff;
427    MCF_INTC1_IMRL = 0xfffffffe;
428}
429
430/*********************************************************************
431* init_pin_assignments - Pin Assignment and General Purpose I/O      *
432**********************************************************************/
433static void init_pin_assignments (void)
434{
435    /* Pin assignments for port NQ
436           Pins NQ7-NQ1 : EdgePort GPIO/IRQ
437    */
438    MCF_GPIO_DDRNQ = 0;
439    MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) |
440                      MCF_GPIO_PNQPAR_PNQPAR6(0x1) |
441                      MCF_GPIO_PNQPAR_PNQPAR5(0x1) |
442                      MCF_GPIO_PNQPAR_PNQPAR4(0x1) |
443                      MCF_GPIO_PNQPAR_PNQPAR3(0x1) |
444                      MCF_GPIO_PNQPAR_PNQPAR2(0x1) |
445                      MCF_GPIO_PNQPAR_PNQPAR1(0x1);
446
447    /* Pin assignments for port GP
448           Pins PG7-PG0 : EdgePort GPIO/IRQ
449    */
450    MCF_GPIO_DDRGP = 0;
451    MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 |
452                      MCF_GPIO_PGPPAR_PGPPAR6 |
453                      MCF_GPIO_PGPPAR_PGPPAR5 |
454                      MCF_GPIO_PGPPAR_PGPPAR4 |
455                      MCF_GPIO_PGPPAR_PGPPAR3 |
456                      MCF_GPIO_PGPPAR_PGPPAR2 |
457                      MCF_GPIO_PGPPAR_PGPPAR1 |
458                      MCF_GPIO_PGPPAR_PGPPAR0;
459
460    /* Pin assignments for port DD
461           Pin DD7 : DDATA[3]
462           Pin DD6 : DDATA[2]
463           Pin DD5 : DDATA[1]
464           Pin DD4 : DDATA[0]
465           Pin DD3 : PST[3]
466           Pin DD2 : PST[2]
467           Pin DD1 : PST[1]
468           Pin DD0 : PST[0]
469       CCON[PSTEN] = 1 to enable PST/DDATA function
470    */
471    MCF_GPIO_DDRDD = 0;
472    MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 |
473                      MCF_GPIO_PDDPAR_PDDPAR6 |
474                      MCF_GPIO_PDDPAR_PDDPAR5 |
475                      MCF_GPIO_PDDPAR_PDDPAR4 |
476                      MCF_GPIO_PDDPAR_PDDPAR3 |
477                      MCF_GPIO_PDDPAR_PDDPAR2 |
478                      MCF_GPIO_PDDPAR_PDDPAR1 |
479                      MCF_GPIO_PDDPAR_PDDPAR0;
480    MCF_CIM_CCON = 0x0021;
481
482    /* Pin assignments for port AN
483           Pins are all GPIO inputs
484    */
485    MCF_GPIO_DDRAN = 0;
486    MCF_GPIO_PANPAR = 0;
487
488    /* Pin assignments for port AS
489           Pins are all GPIO inputs
490    */
491    MCF_GPIO_DDRAS = 0;
492    MCF_GPIO_PASPAR = 0;
493
494    /* Pin assignments for port LD
495           Pins are all GPIO inputs
496    */
497    MCF_GPIO_DDRLD = 0;
498    MCF_GPIO_PLDPAR = 0;
499
500    /* Pin assignments for port QS
501           Pins are all GPIO inputs
502    */
503    MCF_GPIO_DDRQS = 0;
504    MCF_GPIO_PQSPAR = 0;
505
506    /* Pin assignments for port TA
507           Pins are all GPIO inputs
508    */
509    MCF_GPIO_DDRTA = 0;
510    MCF_GPIO_PTAPAR = 0;
511
512    /* Pin assignments for port TC
513           Pins are all GPIO inputs
514    */
515    MCF_GPIO_DDRTC = 0;
516    MCF_GPIO_PTCPAR = 0;
517
518    /* Pin assignments for port TD
519           Pins are all GPIO inputs
520    */
521    MCF_GPIO_DDRTD = 0;
522    MCF_GPIO_PTDPAR = 0;
523
524    /* Pin assignments for port UA
525           Pin UA3 : UART 0 clear-to-send, UCTS0
526           Pin UA2 : UART 0 request-to-send, URTS0
527           Pin UA1 : UART 0 receive data, URXD0
528           Pin UA0 : UART 0 transmit data, UTXD0
529    */
530    MCF_GPIO_DDRUA = 0;
531    MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) |
532                      MCF_GPIO_PUAPAR_PUAPAR2(0x1) |
533                      MCF_GPIO_PUAPAR_PUAPAR1(0x1) |
534                      MCF_GPIO_PUAPAR_PUAPAR0(0x1);
535
536    /* Pin assignments for port UB
537           Pin UB3 : UART 1 clear-to-send, UCTS1
538           Pin UB2 : UART 1 request-to-send, URTS1
539           Pin UB1 : UART 1 receive data, URXD1
540           Pin UB0 : UART 1 transmit data, UTXD1
541    */
542    MCF_GPIO_DDRUB = 0;
543    MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) |
544                      MCF_GPIO_PUBPAR_PUBPAR2(0x1) |
545                      MCF_GPIO_PUBPAR_PUBPAR1(0x1) |
546                      MCF_GPIO_PUBPAR_PUBPAR0(0x1);
547
548    /* Pin assignments for port UC
549           Pin UC3 : UART 2 clear-to-send, UCTS2
550           Pin UC2 : UART 2 request-to-send, URTS2
551           Pin UC1 : UART 2 receive data, URXD2
552           Pin UC0 : UART 2 transmit data, UTXD2
553    */
554    MCF_GPIO_DDRUC = 0;
555    MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 |
556                      MCF_GPIO_PUCPAR_PUCPAR2 |
557                      MCF_GPIO_PUCPAR_PUCPAR1 |
558                      MCF_GPIO_PUCPAR_PUCPAR0;
559
560    /* Configure drive strengths */
561    MCF_GPIO_PDSRH = 0;
562    MCF_GPIO_PDSRL = 0;
563
564    /* Configure Wired-OR register */
565    MCF_GPIO_PWOR = 0;
566}
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