1 | /* |
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2 | * Use the last periodic interval timer (PIT2) as the system clock. |
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3 | * |
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4 | * $Id$ |
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5 | */ |
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6 | |
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7 | #include <rtems.h> |
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8 | #include <bsp.h> |
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9 | |
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10 | /* |
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11 | * Use INTC0 base |
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12 | */ |
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13 | #define CLOCK_VECTOR (64+56) |
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14 | |
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15 | static uint32_t s_pcntrAtTick = 0; |
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16 | static uint32_t s_nanoScale = 0; |
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17 | |
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18 | /* |
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19 | * Provide nanosecond extension |
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20 | * Interrupts are disabled when this is called |
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21 | */ |
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22 | static uint32_t bsp_clock_nanoseconds_since_last_tick(void) |
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23 | { |
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24 | uint32_t i; |
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25 | |
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26 | if (MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF) { |
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27 | i = s_pcntrAtTick + (MCF_PIT1_PMR - MCF_PIT1_PCNTR); |
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28 | } |
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29 | else { |
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30 | i = s_pcntrAtTick - MCF_PIT1_PCNTR; |
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31 | } |
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32 | return i * s_nanoScale; |
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33 | } |
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34 | |
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35 | #define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick |
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36 | |
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37 | /* |
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38 | * Periodic interval timer interrupt handler |
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39 | */ |
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40 | #define Clock_driver_support_at_tick() \ |
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41 | do { \ |
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42 | s_pcntrAtTick = MCF_PIT1_PCNTR; \ |
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43 | MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF; \ |
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44 | } while (0) \ |
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45 | |
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46 | /* |
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47 | * Attach clock interrupt handler |
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48 | */ |
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49 | #define Clock_driver_support_install_isr( _new, _old ) \ |
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50 | do { \ |
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51 | _old = (rtems_isr_entry)set_vector(_new, CLOCK_VECTOR, 1); \ |
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52 | } while(0) |
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53 | |
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54 | /* |
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55 | * Turn off the clock |
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56 | */ |
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57 | static void Clock_driver_support_shutdown_hardware() |
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58 | { |
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59 | MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; |
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60 | } |
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61 | |
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62 | /* |
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63 | * Set up the clock hardware |
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64 | * |
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65 | * We need to have 1 interrupt every BSP_Configuration.microseconds_per_tick |
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66 | */ |
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67 | static void Clock_driver_support_initialize_hardware() |
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68 | { |
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69 | int level; |
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70 | uint32_t pmr; |
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71 | uint32_t preScaleCode = 0; |
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72 | uint32_t clk = bsp_get_CPU_clock_speed() >> 1; |
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73 | uint32_t tps = 1000000 / Configuration.microseconds_per_tick; |
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74 | |
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75 | while (preScaleCode < 15) { |
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76 | pmr = (clk >> preScaleCode) / tps; |
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77 | if (pmr < (1 << 15)) |
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78 | break; |
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79 | preScaleCode++; |
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80 | } |
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81 | s_nanoScale = 1000000000 / (clk >> preScaleCode); |
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82 | |
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83 | MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) | |
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84 | MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY); |
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85 | rtems_interrupt_disable(level); |
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86 | MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56; |
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87 | MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; |
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88 | rtems_interrupt_enable(level); |
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89 | |
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90 | MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | |
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91 | MCF_PIT_PCSR_OVW | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD; |
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92 | MCF_PIT1_PMR = pmr; |
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93 | MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | |
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94 | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN; |
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95 | s_pcntrAtTick = MCF_PIT1_PCNTR; |
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96 | } |
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97 | |
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98 | #include "../../../shared/clockdrv_shell.c" |
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