1 | /* |
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2 | * MCF5206e hardware startup routines |
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3 | * |
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4 | * This is where the real hardware setup is done. A minimal stack |
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5 | * has been provided by the start.S code. No normal C or RTEMS |
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6 | * functions can be called from here. |
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7 | * |
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8 | * This initialization code based on hardware settings of dBUG |
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9 | * monitor. This must be changed if you like to run it immediately |
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10 | * after reset. |
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11 | * |
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12 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia |
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13 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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14 | * |
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15 | * Based on work: |
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16 | * Author: |
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17 | * David Fiddes, D.J@fiddes.surfaid.org |
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18 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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19 | * |
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20 | * COPYRIGHT (c) 1989-1998. |
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21 | * On-Line Applications Research Corporation (OAR). |
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22 | * |
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23 | * The license and distribution terms for this file may be |
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24 | * found in the file LICENSE in this distribution or at |
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25 | * |
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26 | * http://www.rtems.com/license/LICENSE. |
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27 | * |
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28 | * $Id$ |
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29 | */ |
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30 | |
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31 | #include <rtems.h> |
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32 | #include <bsp.h> |
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33 | #include "mcf5206/mcf5206e.h" |
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34 | |
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35 | #define m68k_set_cacr( _cacr ) \ |
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36 | asm volatile ( "movec %0,%%cacr\n\t" \ |
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37 | "nop\n" \ |
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38 | : : "d" (_cacr) ) |
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39 | |
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40 | #define m68k_set_acr0( _acr0 ) \ |
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41 | asm volatile ( "movec %0,%%acr0\n\t" \ |
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42 | "nop\n\t" \ |
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43 | : : "d" (_acr0) ) |
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44 | |
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45 | #define m68k_set_acr1( _acr1 ) \ |
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46 | asm volatile ( "movec %0,%%acr1\n\t" \ |
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47 | "nop\n\t" \ |
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48 | : : "d" (_acr1) ) |
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49 | |
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50 | #define m68k_set_srambar( _rambar0 ) \ |
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51 | asm volatile ( "movec %0,%%rambar0\n\t" \ |
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52 | "nop\n\t" \ |
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53 | : : "d" (_rambar0) ) |
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54 | |
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55 | #define m68k_set_mbar( _mbar ) \ |
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56 | asm volatile ( "movec %0,%%mbar\n\t" \ |
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57 | "nop\n\t" \ |
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58 | : : "d" (_mbar) ) |
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59 | |
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60 | #define mcf5206e_enable_cache() \ |
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61 | m68k_set_cacr( MCF5206E_CACR_CENB ) |
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62 | |
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63 | #define mcf5206e_disable_cache() \ |
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64 | asm volatile ( "nop\n\t" \ |
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65 | "movec %0,%%cacr\n\t" \ |
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66 | "nop\n\t" \ |
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67 | "movec %0,%%cacr\n\t" \ |
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68 | "nop\n\t" \ |
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69 | : : "d" (MCF5206E_CACR_CINV) ) |
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70 | |
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71 | /* Init5206e -- |
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72 | * Initialize MCF5206e on-chip modules |
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73 | * |
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74 | * PARAMETERS: |
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75 | * none |
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76 | * |
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77 | * RETURNS: |
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78 | * none |
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79 | */ |
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80 | void |
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81 | Init5206e(void) |
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82 | { |
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83 | extern void CopyDataClearBSSAndStart(unsigned long ramsize); |
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84 | |
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85 | /* Set Module Base Address register */ |
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86 | m68k_set_mbar((MBAR & MCF5206E_MBAR_BA) | MCF5206E_MBAR_V); |
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87 | |
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88 | /* Set System Protection Control Register (SYPCR): |
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89 | * Bus Monitor Enable, Bus Monitor Timing = 1024 clocks, |
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90 | * Software watchdog disabled |
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91 | */ |
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92 | *MCF5206E_SYPCR(MBAR) = MCF5206E_SYPCR_BME | |
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93 | MCF5206E_SYPCR_BMT_1024; |
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94 | |
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95 | /* Set Pin Assignment Register (PAR): |
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96 | * Output Timer 0 (not DREQ) on *TOUT[0] / *DREQ[1] |
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97 | * Input Timer 0 (not DREQ) on *TIN[0] / *DREQ[0] |
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98 | * IRQ, not IPL |
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99 | * UART2 RTS signal (not \RSTO) |
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100 | * PST/DDATA (not PPIO) |
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101 | * *WE (not CS/A) |
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102 | */ |
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103 | *MCF5206E_PAR(MBAR) = MCF5206E_PAR_PAR9_TOUT | |
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104 | MCF5206E_PAR_PAR8_TIN0 | |
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105 | MCF5206E_PAR_PAR7_UART2 | |
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106 | MCF5206E_PAR_PAR6_IRQ | |
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107 | MCF5206E_PAR_PAR5_PST | |
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108 | MCF5206E_PAR_PAR4_DDATA | |
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109 | MCF5206E_PAR_WE0_WE1_WE2_WE3; |
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110 | |
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111 | /* Set SIM Configuration Register (SIMR): |
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112 | * Disable software watchdog timer and bus timeout monitor when |
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113 | * internal freeze signal is asserted. |
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114 | */ |
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115 | *MCF5206E_SIMR(MBAR) = MCF5206E_SIMR_FRZ0 | MCF5206E_SIMR_FRZ1; |
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116 | |
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117 | /* Set Interrupt Mask Register: Disable all interrupts */ |
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118 | *MCF5206E_IMR(MBAR) = 0xFFFF; |
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119 | |
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120 | /* Assign Interrupt Control Registers as it is defined in bsp.h */ |
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121 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL1) = |
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122 | (BSP_INTLVL_AVEC1 << MCF5206E_ICR_IL_S) | |
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123 | (BSP_INTPRIO_AVEC1 << MCF5206E_ICR_IP_S) | |
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124 | MCF5206E_ICR_AVEC; |
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125 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL2) = |
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126 | (BSP_INTLVL_AVEC2 << MCF5206E_ICR_IL_S) | |
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127 | (BSP_INTPRIO_AVEC2 << MCF5206E_ICR_IP_S) | |
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128 | MCF5206E_ICR_AVEC; |
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129 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL3) = |
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130 | (BSP_INTLVL_AVEC3 << MCF5206E_ICR_IL_S) | |
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131 | (BSP_INTPRIO_AVEC3 << MCF5206E_ICR_IP_S) | |
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132 | MCF5206E_ICR_AVEC; |
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133 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL4) = |
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134 | (BSP_INTLVL_AVEC4 << MCF5206E_ICR_IL_S) | |
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135 | (BSP_INTPRIO_AVEC4 << MCF5206E_ICR_IP_S) | |
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136 | MCF5206E_ICR_AVEC; |
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137 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL5) = |
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138 | (BSP_INTLVL_AVEC5 << MCF5206E_ICR_IL_S) | |
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139 | (BSP_INTPRIO_AVEC5 << MCF5206E_ICR_IP_S) | |
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140 | MCF5206E_ICR_AVEC; |
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141 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL6) = |
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142 | (BSP_INTLVL_AVEC6 << MCF5206E_ICR_IL_S) | |
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143 | (BSP_INTPRIO_AVEC6 << MCF5206E_ICR_IP_S) | |
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144 | MCF5206E_ICR_AVEC; |
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145 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL7) = |
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146 | (BSP_INTLVL_AVEC7 << MCF5206E_ICR_IL_S) | |
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147 | (BSP_INTPRIO_AVEC7 << MCF5206E_ICR_IP_S) | |
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148 | MCF5206E_ICR_AVEC; |
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149 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_1) = |
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150 | (BSP_INTLVL_TIMER1 << MCF5206E_ICR_IL_S) | |
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151 | (BSP_INTPRIO_TIMER1 << MCF5206E_ICR_IP_S) | |
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152 | MCF5206E_ICR_AVEC; |
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153 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_2) = |
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154 | (BSP_INTLVL_TIMER2 << MCF5206E_ICR_IL_S) | |
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155 | (BSP_INTPRIO_TIMER2 << MCF5206E_ICR_IP_S) | |
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156 | MCF5206E_ICR_AVEC; |
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157 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_MBUS) = |
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158 | (BSP_INTLVL_MBUS << MCF5206E_ICR_IL_S) | |
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159 | (BSP_INTPRIO_MBUS << MCF5206E_ICR_IP_S) | |
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160 | MCF5206E_ICR_AVEC; |
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161 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_UART_1) = |
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162 | (BSP_INTLVL_UART1 << MCF5206E_ICR_IL_S) | |
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163 | (BSP_INTPRIO_UART1 << MCF5206E_ICR_IP_S); |
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164 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_UART_2) = |
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165 | (BSP_INTLVL_UART2 << MCF5206E_ICR_IL_S) | |
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166 | (BSP_INTPRIO_UART2 << MCF5206E_ICR_IP_S); |
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167 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_DMA_0) = |
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168 | (BSP_INTLVL_DMA0 << MCF5206E_ICR_IL_S) | |
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169 | (BSP_INTPRIO_DMA0 << MCF5206E_ICR_IP_S) | |
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170 | MCF5206E_ICR_AVEC; |
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171 | *MCF5206E_ICR(MBAR,MCF5206E_INTR_DMA_1) = |
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172 | (BSP_INTLVL_DMA1 << MCF5206E_ICR_IL_S) | |
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173 | (BSP_INTPRIO_DMA1 << MCF5206E_ICR_IP_S) | |
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174 | MCF5206E_ICR_AVEC; |
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175 | |
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176 | /* Software Watchdog timer (not used now) */ |
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177 | *MCF5206E_SWIVR(MBAR) = 0x0F; /* Uninitialized interrupt */ |
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178 | *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY1; |
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179 | *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY2; |
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180 | |
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181 | /* Configuring Chip Selects */ |
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182 | /* CS2: SRAM memory */ |
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183 | *MCF5206E_CSAR(MBAR,2) = BSP_MEM_ADDR_ESRAM >> 16; |
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184 | *MCF5206E_CSMR(MBAR,2) = BSP_MEM_MASK_ESRAM; |
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185 | *MCF5206E_CSCR(MBAR,2) = MCF5206E_CSCR_WS1 | |
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186 | MCF5206E_CSCR_PS_32 | |
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187 | MCF5206E_CSCR_AA | |
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188 | MCF5206E_CSCR_EMAA | |
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189 | MCF5206E_CSCR_WR | |
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190 | MCF5206E_CSCR_RD; |
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191 | |
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192 | /* CS3: GPIO on eLITE board */ |
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193 | *MCF5206E_CSAR(MBAR,3) = BSP_MEM_ADDR_GPIO >> 16; |
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194 | *MCF5206E_CSMR(MBAR,3) = BSP_MEM_MASK_GPIO; |
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195 | *MCF5206E_CSCR(MBAR,3) = MCF5206E_CSCR_WS15 | |
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196 | MCF5206E_CSCR_PS_16 | |
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197 | MCF5206E_CSCR_AA | |
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198 | MCF5206E_CSCR_EMAA | |
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199 | MCF5206E_CSCR_WR | |
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200 | MCF5206E_CSCR_RD; |
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201 | |
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202 | { |
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203 | extern void INTERRUPT_VECTOR(); |
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204 | uint32_t *inttab = (uint32_t*)&INTERRUPT_VECTOR; |
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205 | uint32_t *intvec = (uint32_t*)BSP_MEM_ADDR_ESRAM; |
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206 | register int i; |
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207 | for (i = 0; i < 256; i++) |
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208 | { |
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209 | *(intvec++) = *(inttab++); |
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210 | } |
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211 | } |
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212 | m68k_set_vbr(BSP_MEM_ADDR_ESRAM); |
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213 | |
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214 | /* CS0: Flash EEPROM */ |
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215 | *MCF5206E_CSAR(MBAR,0) = BSP_MEM_ADDR_FLASH >> 16; |
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216 | *MCF5206E_CSCR(MBAR,0) = MCF5206E_CSCR_WS3 | |
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217 | MCF5206E_CSCR_AA | |
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218 | MCF5206E_CSCR_PS_16 | |
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219 | MCF5206E_CSCR_EMAA | |
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220 | MCF5206E_CSCR_WR | |
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221 | MCF5206E_CSCR_RD; |
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222 | *MCF5206E_CSMR(MBAR,0) = BSP_MEM_MASK_FLASH; |
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223 | |
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224 | /* |
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225 | * Invalidate the cache and disable it |
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226 | */ |
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227 | mcf5206e_disable_cache(); |
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228 | |
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229 | /* |
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230 | * Setup ACRs so that if cache turned on, periphal accesses |
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231 | * are not messed up. (Non-cacheable, serialized) |
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232 | */ |
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233 | m68k_set_acr0 ( 0 |
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234 | | MCF5206E_ACR_BASE(BSP_MEM_ADDR_ESRAM) |
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235 | | MCF5206E_ACR_MASK(BSP_MEM_MASK_ESRAM) |
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236 | | MCF5206E_ACR_EN |
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237 | | MCF5206E_ACR_SM_ANY |
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238 | ); |
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239 | m68k_set_acr1 ( 0 |
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240 | | MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
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241 | | MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
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242 | | MCF5206E_ACR_EN |
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243 | | MCF5206E_ACR_SM_ANY |
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244 | ); |
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245 | |
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246 | mcf5206e_enable_cache(); |
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247 | |
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248 | /* |
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249 | * Copy data, clear BSS, switch stacks and call boot_card() |
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250 | */ |
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251 | CopyDataClearBSSAndStart (BSP_MEM_SIZE_ESRAM - 0x400); |
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252 | } |
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