source: rtems/c/src/lib/libbsp/m68k/mcf5206elite/include/bsp.h @ ccceaf3

4.104.115
Last change on this file since ccceaf3 was ccceaf3, checked in by Joel Sherrill <joel.sherrill@…>, on 09/18/08 at 17:42:45

2008-09-18 Joel Sherrill <joel.sherrill@…>

  • include/bsp.h: Remove unnecessary boilerplate comments.
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 * Board Support Package for MCF5206eLITE evaluation board
3 * BSP definitions
4 *
5 * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
6 * Author: Victor V. Vengerov <vvv@oktet.ru>
7 *
8 * The license and distribution terms for this file may be
9 * found in the file LICENSE in this distribution or at
10 *
11 * http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16#ifndef _BSP_H
17#define _BSP_H
18
19#include "mcf5206/mcf5206e.h"
20
21/*** Board resources allocation ***/
22
23/*
24 * To achieve some compatibility with dBUG monitor, we use the same
25 * memory resources allocation as it is used in dBUG.
26 *
27 * If this definitions will be changed, change the linker script also.
28 */
29
30/* Memory mapping */
31/* CS0: Boot Flash */
32#define BSP_MEM_ADDR_FLASH    (0xFFE00000)
33#define BSP_MEM_SIZE_FLASH    (1*1024*1024)
34#define BSP_MEM_MASK_FLASH    (MCF5206E_CSMR_MASK_1M)
35
36/* CS2: External SRAM */
37#define BSP_MEM_ADDR_ESRAM    (0x30000000)
38#define BSP_MEM_SIZE_ESRAM    (1*1024*1024)
39#define BSP_MEM_MASK_ESRAM    (MCF5206E_CSMR_MASK_1M)
40
41/* CS3: General-Purpose I/O register */
42#define BSP_MEM_ADDR_GPIO     (0x40000000)
43#define BSP_MEM_SIZE_GPIO     (64*1024)
44#define BSP_MEM_MASK_GPIO     (MCF5206E_CSMR_MASK_64K)
45
46/* DRAM0: Dynamic RAM */
47#define BSP_MEM_ADDR_DRAM     (0x00000000)
48#define BSP_MEM_SIZE_DRAM     (16*1024*1024)
49#define BSP_MEM_MASK_DRAM     (MCF5206E_DCMR_MASK_16M)
50
51/* On-chip SRAM */
52#define BSP_MEM_ADDR_SRAM     (0x20000000)
53#define BSP_MEM_SIZE_SRAM     (8*1024)
54
55/* On-chip peripherial registers */
56#define BSP_MEM_ADDR_IMM      (0x10000000)
57#define BSP_MEM_SIZE_IMM      (1*1024)
58#define MBAR BSP_MEM_ADDR_IMM
59
60/* Interrupt vector assignment */
61#define BSP_INTVEC_AVEC1    (25)
62#define BSP_INTLVL_AVEC1    (1)
63#define BSP_INTPRIO_AVEC1   (3)
64
65#define BSP_INTVEC_AVEC2    (26)
66#define BSP_INTLVL_AVEC2    (2)
67#define BSP_INTPRIO_AVEC2   (3)
68
69#define BSP_INTVEC_AVEC3    (27)
70#define BSP_INTLVL_AVEC3    (3)
71#define BSP_INTPRIO_AVEC3   (3)
72
73#define BSP_INTVEC_AVEC4    (28)
74#define BSP_INTLVL_AVEC4    (4)
75#define BSP_INTPRIO_AVEC4   (3)
76
77#define BSP_INTVEC_AVEC5    (29)
78#define BSP_INTLVL_AVEC5    (5)
79#define BSP_INTPRIO_AVEC5   (3)
80
81#define BSP_INTVEC_AVEC6    (30)
82#define BSP_INTLVL_AVEC6    (6)
83#define BSP_INTPRIO_AVEC6   (3)
84
85#define BSP_INTVEC_AVEC7    (31)
86#define BSP_INTLVL_AVEC7    (7)
87#define BSP_INTPRIO_AVEC7   (3)
88
89#define BSP_INTVEC_TIMER1   (BSP_INTVEC_AVEC5)
90#define BSP_INTLVL_TIMER1   (BSP_INTLVL_AVEC5)
91#define BSP_INTPRIO_TIMER1  (2)
92
93#define BSP_INTVEC_TIMER2    (BSP_INTVEC_AVEC6)
94#define BSP_INTLVL_TIMER2    (BSP_INTLVL_AVEC6)
95#define BSP_INTPRIO_TIMER2   (2)
96
97#define BSP_INTVEC_MBUS     (BSP_INTVEC_AVEC4)
98#define BSP_INTLVL_MBUS     (BSP_INTLVL_AVEC4)
99#define BSP_INTPRIO_MBUS    (2)
100
101#define BSP_INTVEC_UART1    (64)
102#define BSP_INTLVL_UART1    (4)
103#define BSP_INTPRIO_UART1   (0)
104
105#define BSP_INTVEC_UART2    (65)
106#define BSP_INTLVL_UART2    (4)
107#define BSP_INTPRIO_UART2   (1)
108
109#define BSP_INTVEC_DMA0     (66)
110#define BSP_INTLVL_DMA0     (3)
111#define BSP_INTPRIO_DMA0    (1)
112
113#define BSP_INTVEC_DMA1     (67)
114#define BSP_INTLVL_DMA1     (3)
115#define BSP_INTPRIO_DMA1    (2)
116
117/* Location of DS1307 Real-Time Clock/NVRAM chip */
118#define DS1307_I2C_BUS_NUMBER (0)
119
120#ifndef ASM
121
122#ifdef __cplusplus
123extern "C" {
124#endif
125
126#include <bspopts.h>
127#include <rtems.h>
128#include <rtems/console.h>
129#include <rtems/iosupp.h>
130#include <rtems/clockdrv.h>
131#include <rtems/rtc.h>
132
133#include "i2c.h"
134
135/*
136 *  confdefs.h overrides for this BSP:
137 *   - termios serial ports (defaults to 1)
138 *   - Interrupt stack space is not minimum if defined.
139 */
140
141#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
142
143/* System frequency */
144#define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY)
145extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */
146
147/* MBUS I2C bus clock default frequency */
148#define BSP_MBUS_FREQUENCY (16000)
149
150/* Number of I2C buses supported in this board */
151#define I2C_NUMBER_OF_BUSES (1)
152
153/* I2C bus selection */
154#define I2C_SELECT_BUS(bus)
155
156/*
157 *  Simple spin delay in microsecond units for device drivers.
158 *  This is very dependent on the clock speed of the target.
159 */
160
161#define delay( microseconds ) \
162  { register uint32_t         _delay=(microseconds); \
163    register uint32_t         _tmp=123; \
164    asm volatile( "0: \
165                     nbcd      %0 ; \
166                     nbcd      %0 ; \
167                     dbf       %1,0b" \
168                  : "=d" (_tmp), "=d" (_delay) \
169                  : "0"  (_tmp), "1"  (_delay) ); \
170  }
171
172
173extern m68k_isr_entry M68Kvec[];   /* vector table address */
174
175extern rtems_isr (*rtems_clock_hook)(rtems_vector_number);
176
177/* functions */
178
179m68k_isr_entry set_vector(
180  rtems_isr_entry     handler,
181  rtems_vector_number vector,
182  int                 type
183);
184
185#ifdef __cplusplus
186}
187#endif
188
189#endif /* ASM */
190
191#endif
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