[4d3017a] | 1 | /** |
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| 2 | * @file rtems/motorola/mc68681.h |
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| 3 | * |
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| 4 | * |
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[28a4b1d] | 5 | * mc68681-duart.h -- Low level support code for the Motorola mc68681 |
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[0789abef] | 6 | * DUART. |
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[4d3017a] | 7 | */ |
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| 8 | |
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| 9 | /* |
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[0789abef] | 10 | * |
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| 11 | * Originally written by rob@cygnus.com (Rob Savoye) for the libgloss |
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| 12 | * IDP support. |
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[28a4b1d] | 13 | */ |
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| 14 | |
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[7945944] | 15 | #ifndef _RTEMS_MOTOROLA_MC68681_H |
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| 16 | #define _RTEMS_MOTOROLA_MC68681_H |
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[28a4b1d] | 17 | |
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| 18 | /* |
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[0789abef] | 19 | * In the dark ages when this controller was designed, it was actually |
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| 20 | * possible to access data on unaligned byte boundaries with no penalty. |
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| 21 | * Now we find this chip in configurations in which the registers are |
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| 22 | * at 16-bit, 32-bit, and 64-bit boundaries at the whim of the board |
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| 23 | * designer. If the registers are not at byte addresses, then |
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| 24 | * set this multiplier before including this file to correct the offsets. |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef MC68681_OFFSET_MULTIPLIER |
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| 28 | #define MC68681_OFFSET_MULTIPLIER 1 |
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[28a4b1d] | 29 | #endif |
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| 30 | |
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[0789abef] | 31 | #define __MC68681_REG(_R) ((_R) * MC68681_OFFSET_MULTIPLIER) |
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| 32 | |
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| 33 | /* |
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| 34 | * mc68681 register offsets Read/Write Addresses |
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| 35 | */ |
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| 36 | #define MC68681_MODE_REG_1A __MC68681_REG(0) /* MR1A-MR Prior to Read */ |
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| 37 | #define MC68681_MODE_REG_2A __MC68681_REG(0) /* MR2A-MR After Read */ |
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| 38 | |
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| 39 | #define MC68681_COUNT_MODE_CURRENT_MSB __MC68681_REG(6) /* CTU */ |
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| 40 | #define MC68681_COUNTER_TIMER_UPPER_REG __MC68681_REG(6) /* CTU */ |
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| 41 | #define MC68681_COUNT_MODE_CURRENT_LSB __MC68681_REG(7) /* CTL */ |
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| 42 | #define MC68681_COUNTER_TIMER_LOWER_REG __MC68681_REG(7) /* CTL */ |
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| 43 | #define MC68681_INTERRUPT_VECTOR_REG __MC68681_REG(12) /* IVR */ |
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| 44 | |
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| 45 | #define MC68681_MODE_REG_1B __MC68681_REG(8) /* MR1B-MR Prior to Read */ |
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| 46 | #define MC68681_MODE_REG_2B __MC68681_REG(8) /* MR2BA-MR After Read */ |
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| 47 | |
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| 48 | /* |
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| 49 | * mc68681 register offsets Read Only Addresses |
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| 50 | */ |
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| 51 | #define MC68681_STATUS_REG_A __MC68681_REG(1) /* SRA */ |
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| 52 | #define MC68681_MASK_ISR_REG __MC68681_REG(2) /* MISR */ |
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| 53 | #define MC68681_RECEIVE_BUFFER_A __MC68681_REG(3) /* RHRA */ |
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| 54 | #define MC68681_INPUT_PORT_CHANGE_REG __MC68681_REG(4) /* IPCR */ |
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| 55 | #define MC68681_INTERRUPT_STATUS_REG __MC68681_REG(5) /* ISR */ |
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| 56 | #define MC68681_STATUS_REG_B __MC68681_REG(9) /* SRB */ |
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| 57 | #define MC68681_RECEIVE_BUFFER_B __MC68681_REG(11) /* RHRB */ |
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| 58 | #define MC68681_INPUT_PORT __MC68681_REG(13) /* IP */ |
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| 59 | #define MC68681_START_COUNT_CMD __MC68681_REG(14) /* SCC */ |
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| 60 | #define MC68681_STOP_COUNT_CMD __MC68681_REG(15) /* STC */ |
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| 61 | |
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| 62 | /* |
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| 63 | * mc68681 register offsets Write Only Addresses |
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| 64 | */ |
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| 65 | #define MC68681_CLOCK_SELECT_REG_A __MC68681_REG(1) /* CSRA */ |
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| 66 | #define MC68681_COMMAND_REG_A __MC68681_REG(2) /* CRA */ |
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| 67 | #define MC68681_TRANSMIT_BUFFER_A __MC68681_REG(3) /* THRA */ |
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| 68 | #define MC68681_AUX_CTRL_REG __MC68681_REG(4) /* ACR */ |
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| 69 | #define MC68681_INTERRUPT_MASK_REG __MC68681_REG(5) /* IMR */ |
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| 70 | #define MC68681_CLOCK_SELECT_REG_B __MC68681_REG(9) /* CSRB */ |
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| 71 | #define MC68681_COMMAND_REG_B __MC68681_REG(10) /* CRB */ |
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| 72 | #define MC68681_TRANSMIT_BUFFER_B __MC68681_REG(11) /* THRB */ |
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| 73 | #define MC68681_OUTPUT_PORT_CONFIG_REG __MC68681_REG(13) /* OPCR */ |
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| 74 | #define MC68681_OUTPUT_PORT_SET_REG __MC68681_REG(14) /* SOPBC */ |
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| 75 | #define MC68681_OUTPUT_PORT_RESET_BITS __MC68681_REG(15) /* COPBC */ |
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[28a4b1d] | 76 | |
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| 77 | |
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[0789abef] | 78 | #ifndef MC6681_VOL |
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| 79 | #define MC6681_VOL( ptr ) ((volatile unsigned char *)(ptr)) |
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[28a4b1d] | 80 | #endif |
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[0789abef] | 81 | |
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| 82 | #define MC68681_WRITE( _base, _reg, _data ) \ |
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| 83 | *((volatile unsigned char *)_base+_reg) = (_data) |
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| 84 | |
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| 85 | #define MC68681_READ( _base, _reg ) \ |
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| 86 | *(((volatile unsigned char *)_base+_reg)) |
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| 87 | |
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| 88 | |
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| 89 | |
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[50f32b11] | 90 | #define MC68681_CLEAR 0x00 |
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[0789abef] | 91 | |
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| 92 | #define MC68681_PORT_A 0 |
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| 93 | #define MC68681_PORT_B 1 |
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| 94 | |
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[50f32b11] | 95 | /* |
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| 96 | * DUART Command Register Definitions: |
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[0789abef] | 97 | * |
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[50f32b11] | 98 | * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B |
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[0789abef] | 99 | */ |
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| 100 | #define MC68681_MODE_REG_ENABLE_RX 0x01 |
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| 101 | #define MC68681_MODE_REG_DISABLE_RX 0x02 |
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| 102 | #define MC68681_MODE_REG_ENABLE_TX 0x04 |
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| 103 | #define MC68681_MODE_REG_DISABLE_TX 0x08 |
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| 104 | #define MC68681_MODE_REG_RESET_MR_PTR 0x10 |
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| 105 | #define MC68681_MODE_REG_RESET_RX 0x20 |
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| 106 | #define MC68681_MODE_REG_RESET_TX 0x30 |
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| 107 | #define MC68681_MODE_REG_RESET_ERROR 0x40 |
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| 108 | #define MC68681_MODE_REG_RESET_BREAK 0x50 |
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| 109 | #define MC68681_MODE_REG_START_BREAK 0x60 |
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| 110 | #define MC68681_MODE_REG_STOP_BREAK 0x70 |
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| 111 | #define MC68681_MODE_REG_SET_RX_BRG 0x80 |
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| 112 | #define MC68681_MODE_REG_CLEAR_RX_BRG 0x90 |
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| 113 | #define MC68681_MODE_REG_SET_TX_BRG 0xa0 |
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| 114 | #define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0 |
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| 115 | #define MC68681_MODE_REG_SET_STANDBY 0xc0 |
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| 116 | #define MC68681_MODE_REG_SET_ACTIVE 0xd0 |
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| 117 | |
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| 118 | /* |
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[b29378e] | 119 | * Mode Register Definitions |
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[0789abef] | 120 | * |
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[50f32b11] | 121 | * MC68681_MODE_REG_1A |
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| 122 | * MC68681_MODE_REG_1B |
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[0789abef] | 123 | */ |
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| 124 | #define MC68681_5BIT_CHARS 0x00 |
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| 125 | #define MC68681_6BIT_CHARS 0x01 |
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| 126 | #define MC68681_7BIT_CHARS 0x02 |
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| 127 | #define MC68681_8BIT_CHARS 0x03 |
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| 128 | |
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| 129 | #define MC68681_ODD_PARITY 0x00 |
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| 130 | #define MC68681_EVEN_PARITY 0x04 |
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| 131 | |
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| 132 | #define MC68681_WITH_PARITY 0x00 |
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| 133 | #define MC68681_FORCE_PARITY 0x08 |
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| 134 | #define MC68681_NO_PARITY 0x10 |
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| 135 | #define MC68681_MULTI_DROP 0x18 |
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| 136 | |
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| 137 | #define MC68681_ERR_MODE_CHAR 0x00 |
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| 138 | #define MC68681_ERR_MODE_BLOCK 0x20 |
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| 139 | |
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| 140 | #define MC68681_RX_INTR_RX_READY 0x00 |
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| 141 | #define MC68681_RX_INTR_FFULL 0x40 |
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| 142 | |
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| 143 | #define MC68681_NO_RX_RTS_CTL 0x00 |
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| 144 | #define MC68681_RX_RTS_CTRL 0x80 |
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| 145 | |
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| 146 | |
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| 147 | /* |
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[b29378e] | 148 | * Mode Register Definitions |
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[0789abef] | 149 | * |
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| 150 | * MC68681_MODE_REG_2A |
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| 151 | * MC68681_MODE_REG_2B |
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| 152 | */ |
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| 153 | #define MC68681_STOP_BIT_LENGTH__563 0x00 |
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| 154 | #define MC68681_STOP_BIT_LENGTH__625 0x01 |
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| 155 | #define MC68681_STOP_BIT_LENGTH__688 0x02 |
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| 156 | #define MC68681_STOP_BIT_LENGTH__75 0x03 |
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| 157 | #define MC68681_STOP_BIT_LENGTH__813 0x04 |
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| 158 | #define MC68681_STOP_BIT_LENGTH__875 0x05 |
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| 159 | #define MC68681_STOP_BIT_LENGTH__938 0x06 |
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| 160 | #define MC68681_STOP_BIT_LENGTH_1 0x07 |
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| 161 | #define MC68681_STOP_BIT_LENGTH_1_563 0x08 |
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| 162 | #define MC68681_STOP_BIT_LENGTH_1_625 0x09 |
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| 163 | #define MC68681_STOP_BIT_LENGTH_1_688 0x0a |
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| 164 | #define MC68681_STOP_BIT_LENGTH_1_75 0x0b |
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| 165 | #define MC68681_STOP_BIT_LENGTH_1_813 0x0c |
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| 166 | #define MC68681_STOP_BIT_LENGTH_1_875 0x0d |
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| 167 | #define MC68681_STOP_BIT_LENGTH_1_938 0x0e |
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| 168 | #define MC68681_STOP_BIT_LENGTH_2 0x0f |
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| 169 | |
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| 170 | #define MC68681_CTS_ENABLE_TX 0x10 |
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| 171 | #define MC68681_TX_RTS_CTRL 0x20 |
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| 172 | |
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| 173 | #define MC68681_CHANNEL_MODE_NORMAL 0x00 |
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| 174 | #define MC68681_CHANNEL_MODE_ECHO 0x40 |
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| 175 | #define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80 |
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| 176 | #define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0 |
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| 177 | |
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| 178 | /* |
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[b29378e] | 179 | * Status Register Definitions |
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[0789abef] | 180 | * |
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| 181 | * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B |
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| 182 | */ |
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| 183 | #define MC68681_RX_READY 0x01 |
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| 184 | #define MC68681_FFULL 0x02 |
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| 185 | #define MC68681_TX_READY 0x04 |
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| 186 | #define MC68681_TX_EMPTY 0x08 |
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| 187 | #define MC68681_OVERRUN_ERROR 0x10 |
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| 188 | #define MC68681_PARITY_ERROR 0x20 |
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| 189 | #define MC68681_FRAMING_ERROR 0x40 |
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| 190 | #define MC68681_RECEIVED_BREAK 0x80 |
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| 191 | |
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| 192 | |
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[50f32b11] | 193 | /* |
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| 194 | * Interupt Status Register Definitions. |
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[0789abef] | 195 | * |
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[50f32b11] | 196 | * MC68681_INTERRUPT_STATUS_REG |
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[0789abef] | 197 | */ |
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| 198 | |
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| 199 | |
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[50f32b11] | 200 | /* |
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| 201 | * Interupt Mask Register Definitions |
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[0789abef] | 202 | * |
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[50f32b11] | 203 | * MC68681_INTERRUPT_MASK_REG |
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[0789abef] | 204 | */ |
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| 205 | #define MC68681_IR_TX_READY_A 0x01 |
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| 206 | #define MC68681_IR_RX_READY_A 0x02 |
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| 207 | #define MC68681_IR_BREAK_A 0x04 |
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| 208 | #define MC68681_IR_COUNTER_READY 0x08 |
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| 209 | #define MC68681_IR_TX_READY_B 0x10 |
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| 210 | #define MC68681_IR_RX_READY_B 0x20 |
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| 211 | #define MC68681_IR_BREAK_B 0x40 |
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| 212 | #define MC68681_IR_INPUT_PORT_CHANGE 0x80 |
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| 213 | |
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[50f32b11] | 214 | /* |
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| 215 | * Status Register Definitions. |
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| 216 | * |
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| 217 | * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B |
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[0789abef] | 218 | */ |
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| 219 | #define MC68681_STATUS_RXRDY 0x01 |
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| 220 | #define MC68681_STATUS_FFULL 0x02 |
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| 221 | #define MC68681_STATUS_TXRDY 0x04 |
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| 222 | #define MC68681_STATUS_TXEMT 0x08 |
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| 223 | #define MC68681_STATUS_OVERRUN_ERROR 0x10 |
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| 224 | #define MC68681_STATUS_PARITY_ERROR 0x20 |
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| 225 | #define MC68681_STATUS_FRAMING_ERROR 0x40 |
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| 226 | #define MC68681_STATUS_RECEIVED_BREAK 0x80 |
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| 227 | |
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[50f32b11] | 228 | /* |
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| 229 | * Definitions for the Interrupt Vector Register: |
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[0789abef] | 230 | * |
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[50f32b11] | 231 | * MC68681_INTERRUPT_VECTOR_REG |
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[0789abef] | 232 | */ |
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| 233 | #define MC68681_INTERRUPT_VECTOR_INIT 0x0f |
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| 234 | |
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[50f32b11] | 235 | /* |
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| 236 | * Definitions for the Auxiliary Control Register |
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[0789abef] | 237 | * |
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[50f32b11] | 238 | * MC68681_AUX_CTRL_REG |
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[0789abef] | 239 | */ |
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| 240 | #define MC68681_AUX_BRG_SET1 0x00 |
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| 241 | #define MC68681_AUX_BRG_SET2 0x80 |
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| 242 | |
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| 243 | |
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[50f32b11] | 244 | /* |
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| 245 | * The following Baud rates assume the X1 clock pin is driven with a |
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[0789abef] | 246 | * 3.6864 MHz signal. If a different frequency is used the DUART channel |
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| 247 | * is running at the follwoing baud rate: |
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[50f32b11] | 248 | * ((Table Baud Rate)*frequency)/3.6864 MHz |
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[0789abef] | 249 | */ |
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| 250 | |
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[50f32b11] | 251 | /* |
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| 252 | * Definitions for the Clock Select Register: |
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| 253 | * |
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| 254 | * MC68681_CLOCK_SELECT_REG_A,MC68681_CLOCK_SELECT_REG_A |
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[0789abef] | 255 | * |
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| 256 | * Note: ACR[7] is the MSB of the Auxiliary Control register |
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| 257 | * X is the extend bit. |
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| 258 | * CRA - 0x08 Set Rx BRG Select Extend Bit (X=1) |
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| 259 | * CRA - 0x09 Clear Rx BRG Select Extend Bit (X=0) |
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| 260 | * CRB - 0x0a Set Tx BRG Select Extend Bit (X=1) |
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| 261 | * CRB - 0x0b Clear Tx BRG Select Extend Bit (x=1) |
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| 262 | */ |
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| 263 | #define MC68681_BAUD_RATE_MASK_50 0x00 /* ACR[7]=0,X=0 */ |
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| 264 | /* ARC[7]=1,X=1 */ |
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| 265 | #define MC68681_BAUD_RATE_MASK_75 0x00 /* ACR[7]=0,X=0 */ |
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| 266 | /* ARC[7]=1,X=1 */ |
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[50f32b11] | 267 | #define MC68681_BAUD_RATE_MASK_110 0x01 |
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| 268 | #define MC68681_BAUD_RATE_MASK_134_5 0x02 |
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[0789abef] | 269 | #define MC68681_BAUD_RATE_MASK_150 0x03 /* ACR[7]=0,X=0 */ |
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| 270 | /* ARC[7]=1,X=1 */ |
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| 271 | #define MC68681_BAUD_RATE_MASK_200 0x03 /* ACR[7]=0,X=0 */ |
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| 272 | /* ARC[7]=1,X=1 */ |
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| 273 | #define MC68681_BAUD_RATE_MASK_300 0x04 /* ACR[7]=0,X=0 */ |
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| 274 | /* ARC[7]=1,X=1 */ |
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| 275 | #define MC68681_BAUD_RATE_MASK_600 0x05 /* ACR[7]=0,X=0 */ |
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| 276 | /* ARC[7]=1,X=1 */ |
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| 277 | #define MC68681_BAUD_RATE_MASK_1050 0x07 /* ACR[7]=0,X=0 */ |
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| 278 | /* ARC[7]=1,X=1 */ |
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| 279 | #define MC68681_BAUD_RATE_MASK_1200 0x06 /* ACR[7]=0,X=0 */ |
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| 280 | /* ARC[7]=1,X=1 */ |
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| 281 | #define MC68681_BAUD_RATE_MASK_1800 0x0a /* ACR[7]=0,X=0 */ |
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| 282 | /* ARC[7]=1,X=1 */ |
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| 283 | #define MC68681_BAUD_RATE_MASK_2400 0x08 /* ACR[7]=0,X=0 */ |
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| 284 | /* ARC[7]=1,X=1 */ |
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| 285 | #define MC68681_BAUD_RATE_MASK_3600 0x04 /* ACR[7]=0,X=0 */ |
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| 286 | /* ARC[7]=1,X=1 */ |
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[50f32b11] | 287 | #define MC68681_BAUD_RATE_MASK_4800 0x09 |
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[0789abef] | 288 | #define MC68681_BAUD_RATE_MASK_7200 0x0a /* ACR[7]=0,X=0 */ |
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| 289 | /* ARC[7]=1,X=1 */ |
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[50f32b11] | 290 | #define MC68681_BAUD_RATE_MASK_9600 0xbb |
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[0789abef] | 291 | |
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| 292 | #define MC68681_BAUD_RATE_MASK_14_4K 0x05 /* ACR[7]=0,X=0 */ |
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| 293 | /* ARC[7]=1,X=1 */ |
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| 294 | #define MC68681_BAUD_RATE_MASK_19_2K 0xcc /* ACR[7]=1,X=0 */ |
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| 295 | /* ARC[7]=0,X=1 */ |
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| 296 | #define MC68681_BAUD_RATE_MASK_28_8K 0x06 /* ACR[7]=0,X=0 */ |
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| 297 | /* ARC[7]=1,X=1 */ |
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| 298 | #define MC68681_BAUD_RATE_MASK_38_4K 0xcc /* ACR[7]=0,X=0 */ |
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| 299 | /* ARC[7]=1,X=1 */ |
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| 300 | #define MC68681_BAUD_RATE_MASK_57_6K 0x07 /* ACR[7]=0,X=0 */ |
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| 301 | /* ARC[7]=1,X=1 */ |
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[50f32b11] | 302 | #define MC68681_BAUD_RATE_MASK_115_5K 0x08 |
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| 303 | #define MC68681_BAUD_RATE_MASK_TIMER 0xdd |
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| 304 | #define MC68681_BAUD_RATE_MASK_TIMER_16X 0xee |
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| 305 | #define MC68681_BAUD_RATE_MASK_TIMER_1X 0xff |
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[0789abef] | 306 | |
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| 307 | #endif |
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