[9700578] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | */ |
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[eb5a7e07] | 4 | |
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[ac7d5ef0] | 5 | /*######################################################### |
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| 6 | # |
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| 7 | # This code is a modified version of what you will find at the |
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| 8 | # end of the IDP User's manual. The original code is copyrighted |
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| 9 | # by Motorola and Motorola Semiconductor Products as well as |
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| 10 | # Motorola Software products group. |
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| 11 | # |
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| 12 | # Modifications to the original IDP code by Doug McBride, Colorado |
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| 13 | # Space Grant College. Modifications include a means of accessing |
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| 14 | # port B of the duart as well as port A as well as modifications for |
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| 15 | # buffering and RTEMS support. Modifications are provided |
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| 16 | # as is and may not be correct. |
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| 17 | # |
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| 18 | # Rob Savoye provided the format for the mc68681 header file |
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| 19 | # |
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| 20 | # Joel Sherrill provided inspiration for recoding my original assembly |
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| 21 | # for this file into C (a good idea) |
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| 22 | # |
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| 23 | ##########################################################*/ |
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| 24 | |
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[033ec54] | 25 | #include <bsp.h> |
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| 26 | #include <ringbuf.h> |
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[ac7d5ef0] | 27 | |
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| 28 | rtems_isr C_Receive_ISR(rtems_vector_number vector); |
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| 29 | extern Ring_buffer_t Buffer[]; |
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| 30 | |
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| 31 | extern unsigned char inbuf[]; |
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| 32 | extern unsigned char inbuf_portb[]; |
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| 33 | extern unsigned tail; |
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| 34 | extern unsigned tail_portb; |
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| 35 | unsigned char Pit_initialized = 0; |
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| 36 | |
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| 37 | /*##################################################################### |
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| 38 | # The volatile routine to initialize the duart -- port a and port b |
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| 39 | ######################################################################*/ |
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| 40 | volatile void init_pit() |
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| 41 | { |
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[033ec54] | 42 | /* |
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| 43 | * ports A & B while configuring PIT by: |
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| 44 | * |
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| 45 | * + disable Interrupt Mask Register |
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| 46 | * + disable port A transmitter |
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| 47 | * + disable port A receiver |
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| 48 | * + disable port B transmitter |
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| 49 | * + disable port B receiver |
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| 50 | */ |
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| 51 | |
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| 52 | MC68681_WRITE(MC68681_INTERRUPT_MASK_REG, 0x00); |
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| 53 | MC68681_WRITE(MC68681_COMMAND_REG_A ,MC68681_MODE_REG_DISABLE_TX); |
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| 54 | MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_DISABLE_RX); |
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| 55 | MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_DISABLE_TX); |
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| 56 | MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_DISABLE_RX); |
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| 57 | |
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| 58 | /* |
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| 59 | * install ISR for ports A and B |
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| 60 | */ |
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| 61 | set_vector(C_Receive_ISR, (VECT+H3VECT), 1); |
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| 62 | |
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| 63 | /* |
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| 64 | * initialize pit |
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| 65 | * |
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| 66 | * set mode to 0 -- disable all ports |
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| 67 | * set up pirq and piack |
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| 68 | * all pins on port b are input |
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| 69 | * submode 1x, h3 interrupt enabled |
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| 70 | * setup pivr |
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| 71 | * turn on all ports |
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| 72 | */ |
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| 73 | MC68230_WRITE(PGCR, 0x00); |
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| 74 | MC68230_WRITE(PSRR, 0x18); |
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| 75 | MC68230_WRITE(PBDDR, 0x00); |
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| 76 | MC68230_WRITE(PBCR, 0x82); |
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| 77 | MC68230_WRITE(PIVR, VECT); |
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| 78 | MC68230_WRITE(PGCR, 0x20); |
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| 79 | |
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| 80 | /* |
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| 81 | * For some reason, the reset of receiver/transmitter only works for |
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| 82 | * the first time around -- it garbles the output otherwise |
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| 83 | * (e.g., sp21) |
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| 84 | */ |
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| 85 | if (!Pit_initialized) |
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| 86 | { |
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| 87 | /* |
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| 88 | * initialize the duart registers on port b |
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| 89 | * WARNING:OPTIMIZER MAY ONLY EXECUTE THIRD STATEMENT IF NOT VOLATILE |
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| 90 | * |
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| 91 | * reset tx, channel b |
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| 92 | * reset rx, channel b |
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| 93 | * reset mr pointer, ch |
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| 94 | */ |
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| 95 | MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_TX); |
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| 96 | MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_RX); |
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| 97 | MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_MR_PTR); |
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| 98 | |
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| 99 | /* |
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| 100 | * initialize the duart registers on port a |
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| 101 | * WARNING:OPTIMIZER MAY ONLY EXECUTE THIRD STATEMENT IF NOT VOLATILE |
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| 102 | * |
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| 103 | * reset tx, channel a |
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| 104 | * reset rx, channel a |
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| 105 | * reset mr pointer, ch |
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| 106 | */ |
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| 107 | MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_TX); |
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| 108 | MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_RX); |
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| 109 | MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_MR_PTR); |
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| 110 | |
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| 111 | Pit_initialized = 1; |
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| 112 | } |
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| 113 | |
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| 114 | /* |
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| 115 | * Init the general registers of the duart |
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| 116 | * |
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| 117 | * init ivr |
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| 118 | * init imr |
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| 119 | * init acr |
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| 120 | * init ctur |
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| 121 | * init ctlr |
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| 122 | * init opcr |
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| 123 | * init cts |
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| 124 | */ |
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| 125 | MC68681_WRITE(MC68681_INTERRUPT_VECTOR_REG, |
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| 126 | MC68681_INTERRUPT_VECTOR_INIT); |
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| 127 | MC68681_WRITE(MC68681_INTERRUPT_MASK_REG, |
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| 128 | MC68681_IR_RX_READY_A | MC68681_IR_RX_READY_B); |
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| 129 | MC68681_WRITE(MC68681_AUX_CTRL_REG, MC68681_CLEAR); |
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| 130 | MC68681_WRITE(MC68681_COUNTER_TIMER_UPPER_REG, 0x00); |
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| 131 | MC68681_WRITE(MC68681_COUNTER_TIMER_LOWER_REG, 0x02); |
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| 132 | MC68681_WRITE(MC68681_OUTPUT_PORT_CONFIG_REG, MC68681_CLEAR); |
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| 133 | MC68681_WRITE(MC68681_OUTPUT_PORT_SET_REG, 0x01); |
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| 134 | |
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| 135 | /* |
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| 136 | * init the actual serial port for port a |
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| 137 | * |
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| 138 | * Set Baud Rate to 9600 |
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| 139 | * Set Stop bit length of 1 |
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| 140 | * enable Transmit and receive |
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| 141 | */ |
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| 142 | MC68681_WRITE(MC68681_CLOCK_SELECT_REG_A, MC68681_BAUD_RATE_MASK_9600); |
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| 143 | MC68681_WRITE(MC68681_MODE_REG_1A, |
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| 144 | (MC68681_8BIT_CHARS | MC68681_NO_PARITY)); |
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| 145 | MC68681_WRITE(MC68681_MODE_REG_2A,MC68681_STOP_BIT_LENGTH_1); |
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| 146 | MC68681_WRITE(MC68681_COMMAND_REG_A, |
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| 147 | (MC68681_MODE_REG_ENABLE_TX | MC68681_MODE_REG_ENABLE_RX)); |
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| 148 | |
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| 149 | /* |
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| 150 | * init the actual serial port for port b |
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| 151 | * init csrb -- 9600 baud |
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| 152 | */ |
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| 153 | MC68681_WRITE(MC68681_CLOCK_SELECT_REG_B, MC68681_BAUD_RATE_MASK_9600); |
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| 154 | |
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| 155 | |
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[ac7d5ef0] | 156 | #define EIGHT_BITS_NO_PARITY |
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| 157 | #ifdef EIGHT_BITS_NO_PARITY |
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[033ec54] | 158 | /* |
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| 159 | * Set 8 Bit characters with no parity |
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| 160 | */ |
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| 161 | MC68681_WRITE(MC68681_MODE_REG_1B, |
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| 162 | (MC68681_NO_PARITY | MC68681_8BIT_CHARS) ); |
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| 163 | #else |
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| 164 | /* |
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| 165 | * Set 7 Bit Characters with parity |
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| 166 | */ |
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| 167 | MC68681_WRITE(MC68681_MODE_REG_1B, |
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| 168 | (MC68681_WITH_PARITY | MC68681_7BIT_CHARS) ); |
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[ac7d5ef0] | 169 | #endif |
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[033ec54] | 170 | |
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| 171 | |
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| 172 | /* |
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| 173 | * Set Stop Bit length to 1 |
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| 174 | * Disable Recieve and transmit on B |
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| 175 | */ |
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| 176 | MC68681_WRITE(MC68681_MODE_REG_2B,MC68681_STOP_BIT_LENGTH_1); |
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| 177 | MC68681_WRITE(MC68681_COMMAND_REG_B, |
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| 178 | (MC68681_MODE_REG_ENABLE_TX | MC68681_MODE_REG_ENABLE_RX) ); |
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[ac7d5ef0] | 179 | } |
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| 180 | |
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| 181 | /*##################################################################### |
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| 182 | # interrupt handler for receive of character from duart on ports A & B |
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| 183 | #####################################################################*/ |
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| 184 | rtems_isr C_Receive_ISR(rtems_vector_number vector) |
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| 185 | { |
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[033ec54] | 186 | volatile unsigned char *_addr; |
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| 187 | |
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| 188 | /* |
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| 189 | * Clear pit interrupt. |
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| 190 | */ |
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| 191 | _addr = (unsigned char *) (PIT_ADDR + PITSR); |
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| 192 | *_addr = 0x04; |
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| 193 | |
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| 194 | /* |
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| 195 | * check port A first for input |
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| 196 | * extract rcvrdy on port B |
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| 197 | * set ptr to recieve buffer and read character into ring buffer |
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| 198 | */ |
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| 199 | _addr = (unsigned char *) (DUART_ADDR + MC68681_STATUS_REG_A); |
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| 200 | if (*_addr & MC68681_RX_READY) /* extract rcvrdy on port A */ |
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| 201 | { |
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| 202 | _addr = (unsigned char *) (DUART_ADDR + MC68681_RECEIVE_BUFFER_A); |
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| 203 | Ring_buffer_Add_character( &Buffer[ 0 ], *_addr ); |
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| 204 | } |
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| 205 | |
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| 206 | /* |
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| 207 | * If not on port A, let's check port B |
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| 208 | * extract rcvrdy on port B |
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| 209 | * set ptr to recieve buffer and read character into ring buffer |
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| 210 | */ |
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| 211 | else |
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| 212 | { |
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| 213 | _addr = (unsigned char *) (DUART_ADDR + MC68681_STATUS_REG_B); |
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| 214 | if (*_addr & MC68681_RX_READY) /* extract rcvrdy on port B */ |
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| 215 | { |
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| 216 | _addr = (unsigned char *) (DUART_ADDR + MC68681_RECEIVE_BUFFER_B); |
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| 217 | Ring_buffer_Add_character( &Buffer[ 1 ], *_addr ); |
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| 218 | } |
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| 219 | |
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| 220 | /* |
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| 221 | * if not ready on port A or port B, must be an error |
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| 222 | * if error, get out so that fifo is undisturbed |
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| 223 | */ |
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| 224 | } |
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[ac7d5ef0] | 225 | } |
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| 226 | |
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| 227 | /*##################################################################### |
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| 228 | # This is the routine that actually transmits a character one at a time |
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| 229 | # This routine transmits on port A of the IDP board |
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| 230 | #####################################################################*/ |
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| 231 | void transmit_char(char ch) |
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| 232 | { |
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[033ec54] | 233 | volatile unsigned char *_addr; |
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[ac7d5ef0] | 234 | |
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[033ec54] | 235 | /* |
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| 236 | * Get SRA (extract txrdy) |
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| 237 | */ |
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| 238 | _addr = (unsigned char *) (DUART_ADDR + MC68681_STATUS_REG_A); |
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| 239 | while (!(*_addr & MC68681_TX_READY)) |
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| 240 | { |
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| 241 | } |
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[ac7d5ef0] | 242 | |
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[033ec54] | 243 | /* |
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| 244 | * transmit character over port A |
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| 245 | */ |
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| 246 | MC68681_WRITE(MC68681_TRANSMIT_BUFFER_A, ch); |
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[ac7d5ef0] | 247 | } |
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| 248 | |
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[033ec54] | 249 | |
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[ac7d5ef0] | 250 | /*##################################################################### |
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| 251 | # This is the routine that actually transmits a character one at a time |
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| 252 | # This routine transmits on port B of the IDP board |
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| 253 | #####################################################################*/ |
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| 254 | void transmit_char_portb(char ch) |
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| 255 | { |
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[033ec54] | 256 | volatile unsigned char *_addr; |
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[ac7d5ef0] | 257 | |
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[033ec54] | 258 | /* |
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| 259 | * Get SRB (extract txrdy) |
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| 260 | */ |
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| 261 | _addr = (unsigned char *) (DUART_ADDR + MC68681_STATUS_REG_B); |
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| 262 | while (!(*_addr & MC68681_TX_READY)) |
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| 263 | { |
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| 264 | } |
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[ac7d5ef0] | 265 | |
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[033ec54] | 266 | /* |
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| 267 | * transmit character over port B |
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| 268 | */ |
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| 269 | MC68681_WRITE(MC68681_TRANSMIT_BUFFER_B, ch); |
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[ac7d5ef0] | 270 | } |
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