[4c54bb07] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic mcf548x BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | File: init548x.c | |
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| 5 | +-----------------------------------------------------------------+ |
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| 6 | | The file contains the c part of MCF548x init code | |
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| 7 | +-----------------------------------------------------------------+ |
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| 8 | | Copyright (c) 2007 | |
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| 9 | | Embedded Brains GmbH | |
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| 10 | | Obere Lagerstr. 30 | |
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| 11 | | D-82178 Puchheim | |
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| 12 | | Germany | |
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| 13 | | rtems@embedded-brains.de | |
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| 14 | +-----------------------------------------------------------------+ |
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| 15 | | | |
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| 16 | | Parts of the code has been derived from the "dBUG source code" | |
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| 17 | | package Freescale is providing for M548X EVBs. The usage of | |
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| 18 | | the modified or unmodified code and it's integration into the | |
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| 19 | | generic mcf548x BSP has been done according to the Freescale | |
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| 20 | | license terms. | |
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| 21 | | | |
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| 22 | | The Freescale license terms can be reviewed in the file | |
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| 23 | | | |
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| 24 | | Freescale_license.txt | |
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| 25 | | | |
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| 26 | +-----------------------------------------------------------------+ |
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| 27 | | | |
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| 28 | | The generic mcf548x BSP has been developed on the basic | |
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| 29 | | structures and modules of the av5282 BSP. | |
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| 30 | | | |
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| 31 | +-----------------------------------------------------------------+ |
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| 32 | | | |
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| 33 | | The license and distribution terms for this file may be | |
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| 34 | | found in the file LICENSE in this distribution or at | |
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| 35 | | | |
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| 36 | | http://www.rtems.com/license/LICENSE. | |
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| 37 | | | |
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| 38 | +-----------------------------------------------------------------+ |
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| 39 | | | |
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| 40 | | date history ID | |
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| 41 | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
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| 42 | | 12.11.07 1.0 ras | |
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| 43 | | | |
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| 44 | \*===============================================================*/ |
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| 45 | |
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| 46 | #include <rtems.h> |
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| 47 | #include <bsp.h> |
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| 48 | |
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| 49 | #define SYSTEM_PERIOD 10 /* system bus period in ns */ |
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| 50 | |
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| 51 | /* SDRAM Timing Parameters */ |
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| 52 | #define SDRAM_TWR 2 /* in clocks */ |
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| 53 | #define SDRAM_CASL 2.5 /* in clocks */ |
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| 54 | #define SDRAM_TRCD 20 /* in ns */ |
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| 55 | #define SDRAM_TRP 20 /* in ns */ |
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| 56 | #define SDRAM_TRFC 75 /* in ns */ |
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| 57 | #define SDRAM_TREFI 7800 /* in ns */ |
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| 58 | |
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| 59 | extern uint8_t _DataRom[]; |
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| 60 | extern uint8_t _DataRam[]; |
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| 61 | extern uint8_t _DataEnd[]; |
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| 62 | extern uint8_t _BssStart[]; |
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| 63 | extern uint8_t _BssEnd[]; |
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| 64 | extern uint8_t _BootFlashBase[]; |
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| 65 | extern uint8_t _CodeFlashBase[]; |
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[939439d3] | 66 | extern uint8_t RamBase[]; |
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[4c54bb07] | 67 | extern uint32_t InterruptVectorTable[]; |
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| 68 | extern uint32_t _VectorRam[]; |
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| 69 | |
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| 70 | void gpio_init(void); |
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| 71 | void fbcs_init(void); |
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| 72 | void sdramc_init(void); |
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| 73 | void mcf548x_init(void); |
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| 74 | |
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| 75 | |
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| 76 | void mcf548x_init(void) |
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| 77 | { |
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| 78 | uint32_t n; |
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| 79 | uint8_t *dp, *sp; |
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| 80 | |
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| 81 | /* set XLB arbiter timeouts */ |
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| 82 | #ifdef M5484FIREENGINE |
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| 83 | /* set XLB arbiter timeouts */ |
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| 84 | MCF548X_XLB_ADRTO = 0x00000100; |
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| 85 | MCF548X_XLB_DATTO = 0x00000100; |
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| 86 | MCF548X_XLB_BUSTO = 0x00000100; |
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| 87 | #endif |
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| 88 | |
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| 89 | gpio_init(); |
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| 90 | fbcs_init(); |
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| 91 | sdramc_init(); |
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| 92 | |
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| 93 | /* Copy the vector table to RAM */ |
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| 94 | if (_VectorRam != InterruptVectorTable) |
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| 95 | { |
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| 96 | for( n = 0; n < 256; n++) |
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| 97 | { |
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| 98 | _VectorRam[n] = InterruptVectorTable[n]; |
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| 99 | } |
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| 100 | } |
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| 101 | |
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| 102 | m68k_set_vbr((uint32_t)_VectorRam); |
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| 103 | |
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| 104 | /* Move initialized data from ROM to RAM. */ |
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| 105 | if (_DataRom != _DataRam) |
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| 106 | { |
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| 107 | n = _DataEnd - _DataRam; |
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| 108 | sp = (uint8_t *)_DataRom; |
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| 109 | dp = (uint8_t *)_DataRam; |
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| 110 | while(n--) |
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| 111 | *dp++ = *sp++; |
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| 112 | } |
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| 113 | |
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| 114 | /* Zero uninitialized data */ |
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| 115 | if (_BssStart != _BssEnd) |
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| 116 | { |
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| 117 | n = _BssEnd - _BssStart; |
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| 118 | sp = (uint8_t *)_BssStart; |
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| 119 | while (n--) |
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| 120 | *sp++ = 0; |
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| 121 | } |
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| 122 | |
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| 123 | } |
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| 124 | /********************************************************************/ |
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| 125 | void |
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| 126 | fbcs_init (void) |
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| 127 | { |
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| 128 | #ifdef M5484FIREENGINE |
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| 129 | |
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| 130 | volatile uint32_t cscr, clk_ratio, fb_period, ws; |
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| 131 | |
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| 132 | /* boot flash already valid ? */ |
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| 133 | if(!(MCF548X_FBCS_CSMR0 & MCF548X_FBCS_CSMR_V)) |
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| 134 | { |
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| 135 | |
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| 136 | /* |
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| 137 | * Boot Flash |
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| 138 | */ |
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| 139 | MCF548X_FBCS_CSAR0 = MCF548X_FBCS_CSAR_BA((uint32_t)(_BootFlashBase)); |
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| 140 | |
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| 141 | cscr = (0 |
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| 142 | | MCF548X_FBCS_CSCR_ASET(1) |
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| 143 | | MCF548X_FBCS_CSCR_WRAH(0) |
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| 144 | | MCF548X_FBCS_CSCR_RDAH(0) |
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| 145 | | MCF548X_FBCS_CSCR_AA |
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| 146 | | MCF548X_FBCS_CSCR_PS_16); |
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| 147 | |
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| 148 | /* |
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| 149 | * Determine the necessary wait states based on the defined system |
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| 150 | * period (XLB clock period) and the CLKIN to XLB ratio. |
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| 151 | * The boot flash has a max access time of 110ns. |
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| 152 | */ |
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| 153 | clk_ratio = (MCF548X_PCI_PCIGSCR >> 24) & 0x7; |
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| 154 | fb_period = SYSTEM_PERIOD * clk_ratio; |
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| 155 | ws = 110 / fb_period; |
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| 156 | |
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| 157 | MCF548X_FBCS_CSCR0 = cscr | MCF548X_FBCS_CSCR_WS(ws); |
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| 158 | MCF548X_FBCS_CSMR0 = (0 |
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| 159 | | MCF548X_FBCS_CSMR_BAM_2M |
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| 160 | | MCF548X_FBCS_CSMR_V); |
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| 161 | |
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| 162 | } |
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| 163 | |
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| 164 | /* code flash already valid ? */ |
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| 165 | if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V)) |
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| 166 | { |
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| 167 | |
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| 168 | /* |
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| 169 | * Code Flash |
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| 170 | */ |
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| 171 | MCF548X_FBCS_CSAR1 = MCF548X_FBCS_CSAR_BA((uint32_t)(_CodeFlashBase)); |
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| 172 | |
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| 173 | /* |
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| 174 | * Determine the necessary wait states based on the defined system |
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| 175 | * period (XLB clock period) and the CLKIN to XLB ratio. |
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| 176 | * The user/code flash has a max access time of 120ns. |
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| 177 | */ |
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| 178 | ws = 120 / fb_period; |
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| 179 | MCF548X_FBCS_CSCR1 = cscr | MCF548X_FBCS_CSCR_WS(ws); |
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| 180 | MCF548X_FBCS_CSMR1 = (0 |
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| 181 | | MCF548X_FBCS_CSMR_BAM_16M |
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| 182 | | MCF548X_FBCS_CSMR_V); |
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| 183 | } |
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| 184 | |
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| 185 | #endif |
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| 186 | } |
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| 187 | |
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| 188 | /********************************************************************/ |
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| 189 | void |
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| 190 | sdramc_init (void) |
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| 191 | { |
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| 192 | |
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| 193 | /* |
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| 194 | * Check to see if the SDRAM has already been initialized |
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| 195 | * by a run control tool |
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| 196 | */ |
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| 197 | if (!(MCF548X_SDRAMC_SDCR & MCF548X_SDRAMC_SDCR_REF)) |
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| 198 | { |
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| 199 | /* |
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| 200 | * Basic configuration and initialization |
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| 201 | */ |
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| 202 | MCF548X_SDRAMC_SDRAMDS = (0 |
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| 203 | | MCF548X_SDRAMC_SDRAMDS_SB_E(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA) |
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| 204 | | MCF548X_SDRAMC_SDRAMDS_SB_C(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA) |
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| 205 | | MCF548X_SDRAMC_SDRAMDS_SB_A(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA) |
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| 206 | | MCF548X_SDRAMC_SDRAMDS_SB_S(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA) |
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| 207 | | MCF548X_SDRAMC_SDRAMDS_SB_D(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA) |
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| 208 | ); |
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| 209 | MCF548X_SDRAMC_CS0CFG = (0 |
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[939439d3] | 210 | | MCF548X_SDRAMC_CSnCFG_CSBA((uint32_t)(RamBase)) |
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[4c54bb07] | 211 | | MCF548X_SDRAMC_CSnCFG_CSSZ(MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE) |
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| 212 | ); |
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| 213 | MCF548X_SDRAMC_SDCFG1 = (0 |
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| 214 | | MCF548X_SDRAMC_SDCFG1_SRD2RW(7) |
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| 215 | | MCF548X_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
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| 216 | | MCF548X_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2)) |
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| 217 | | MCF548X_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5)) |
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| 218 | | MCF548X_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5)) |
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| 219 | | MCF548X_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5)) |
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| 220 | | MCF548X_SDRAMC_SDCFG1_WTLAT(3) |
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| 221 | ); |
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| 222 | MCF548X_SDRAMC_SDCFG2 = (0 |
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| 223 | | MCF548X_SDRAMC_SDCFG2_BRD2PRE(4) |
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| 224 | | MCF548X_SDRAMC_SDCFG2_BWT2RW(6) |
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| 225 | | MCF548X_SDRAMC_SDCFG2_BRD2WT(7) |
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| 226 | | MCF548X_SDRAMC_SDCFG2_BL(7) |
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| 227 | ); |
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| 228 | |
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| 229 | /* |
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| 230 | * Precharge and enable write to SDMR |
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| 231 | */ |
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| 232 | MCF548X_SDRAMC_SDCR = (0 |
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| 233 | | MCF548X_SDRAMC_SDCR_MODE_EN |
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| 234 | | MCF548X_SDRAMC_SDCR_CKE |
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| 235 | | MCF548X_SDRAMC_SDCR_DDR |
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| 236 | | MCF548X_SDRAMC_SDCR_MUX(1) |
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| 237 | | MCF548X_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5)) |
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| 238 | | MCF548X_SDRAMC_SDCR_IPALL |
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| 239 | ); |
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| 240 | |
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| 241 | /* |
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| 242 | * Write extended mode register |
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| 243 | */ |
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| 244 | MCF548X_SDRAMC_SDMR = (0 |
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| 245 | | MCF548X_SDRAMC_SDMR_BNKAD_LEMR |
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| 246 | | MCF548X_SDRAMC_SDMR_AD(0x0) |
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| 247 | | MCF548X_SDRAMC_SDMR_CMD |
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| 248 | ); |
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| 249 | |
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| 250 | /* |
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| 251 | * Write mode register and reset DLL |
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| 252 | */ |
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| 253 | MCF548X_SDRAMC_SDMR = (0 |
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| 254 | | MCF548X_SDRAMC_SDMR_BNKAD_LMR |
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| 255 | | MCF548X_SDRAMC_SDMR_AD(0x163) |
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| 256 | | MCF548X_SDRAMC_SDMR_CMD |
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| 257 | ); |
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| 258 | |
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| 259 | /* |
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| 260 | * Execute a PALL command |
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| 261 | */ |
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| 262 | MCF548X_SDRAMC_SDCR |=MCF548X_SDRAMC_SDCR_IPALL; |
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| 263 | |
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| 264 | /* |
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| 265 | * Perform two REF cycles |
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| 266 | */ |
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| 267 | MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF; |
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| 268 | MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF; |
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| 269 | |
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| 270 | /* |
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| 271 | * Write mode register and clear reset DLL |
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| 272 | */ |
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| 273 | MCF548X_SDRAMC_SDMR = (0 |
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| 274 | | MCF548X_SDRAMC_SDMR_BNKAD_LMR |
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| 275 | | MCF548X_SDRAMC_SDMR_AD(0x063) |
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| 276 | | MCF548X_SDRAMC_SDMR_CMD |
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| 277 | ); |
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| 278 | |
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| 279 | /* |
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| 280 | * Enable auto refresh and lock SDMR |
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| 281 | */ |
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| 282 | MCF548X_SDRAMC_SDCR &= ~MCF548X_SDRAMC_SDCR_MODE_EN; |
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| 283 | MCF548X_SDRAMC_SDCR |= (0 |
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| 284 | | MCF548X_SDRAMC_SDCR_REF |
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| 285 | | MCF548X_SDRAMC_SDCR_DQS_OE(0xF) |
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| 286 | ); |
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| 287 | } |
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| 288 | |
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| 289 | } |
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| 290 | |
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| 291 | /********************************************************************/ |
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| 292 | void |
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| 293 | gpio_init(void) |
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| 294 | { |
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| 295 | |
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| 296 | #ifdef M5484FIREENGINE |
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| 297 | |
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| 298 | /* |
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| 299 | * Enable Ethernet signals so that, if a cable is plugged into |
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| 300 | * the ports, the lines won't be floating and potentially cause |
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| 301 | * erroneous transmissions |
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| 302 | */ |
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| 303 | MCF548X_GPIO_PAR_FECI2CIRQ = (0 |
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[045821e] | 304 | |
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[4c54bb07] | 305 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC |
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| 306 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO |
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| 307 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII |
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| 308 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17 |
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[045821e] | 309 | |
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[4c54bb07] | 310 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC |
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| 311 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO |
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| 312 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII |
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| 313 | | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07 |
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| 314 | ); |
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| 315 | |
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| 316 | #endif |
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| 317 | } |
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