1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic mcf548x BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | File: bspstart.c | |
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5 | +-----------------------------------------------------------------+ |
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6 | | The file contains the startup code of generic MCF548x BSP | |
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7 | +-----------------------------------------------------------------+ |
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8 | | Copyright (c) 2007 | |
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9 | | Embedded Brains GmbH | |
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10 | | Obere Lagerstr. 30 | |
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11 | | D-82178 Puchheim | |
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12 | | Germany | |
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13 | | rtems@embedded-brains.de | |
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14 | +-----------------------------------------------------------------+ |
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15 | | | |
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16 | | Parts of the code has been derived from the "dBUG source code" | |
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17 | | package Freescale is providing for M548X EVBs. The usage of | |
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18 | | the modified or unmodified code and it's integration into the | |
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19 | | generic mcf548x BSP has been done according to the Freescale | |
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20 | | license terms. | |
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21 | | | |
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22 | | The Freescale license terms can be reviewed in the file | |
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23 | | | |
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24 | | Freescale_license.txt | |
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25 | | | |
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26 | +-----------------------------------------------------------------+ |
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27 | | | |
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28 | | The generic mcf548x BSP has been developed on the basic | |
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29 | | structures and modules of the av5282 BSP. | |
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30 | | | |
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31 | +-----------------------------------------------------------------+ |
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32 | | | |
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33 | | The license and distribution terms for this file may be | |
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34 | | found in the file LICENSE in this distribution or at | |
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35 | | | |
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36 | | http://www.rtems.com/license/LICENSE. | |
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37 | | | |
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38 | +-----------------------------------------------------------------+ |
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39 | | | |
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40 | | date history ID | |
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41 | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
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42 | | 12.11.07 1.0 ras | |
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43 | | | |
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44 | \*===============================================================*/ |
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45 | |
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46 | #include <bsp.h> |
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47 | |
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48 | extern uint32_t _CPU_cacr_shadow; |
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49 | |
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50 | /* |
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51 | * These labels (!) are defined in the linker command file or when the linker is |
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52 | * invoked. |
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53 | * NOTE: The information (size) is the address of the object, not the object |
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54 | * itself. |
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55 | */ |
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56 | |
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57 | extern char _SdramBase[]; |
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58 | extern char _BootFlashBase[]; |
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59 | extern char _CodeFlashBase[]; |
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60 | extern char _SdramSize[]; |
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61 | extern char _BootFlashSize[]; |
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62 | extern char _CodeFlashSize[]; |
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63 | extern char _TopRamReserved []; |
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64 | extern char WorkAreaBase []; |
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65 | |
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66 | /* |
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67 | * CPU-space access |
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68 | */ |
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69 | #define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2)) |
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70 | #define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3)) |
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71 | |
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72 | /* |
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73 | * Set initial cacr mode, mainly enables branch/intruction/data cache and |
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74 | * switch off FPU. |
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75 | */ |
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76 | static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */ |
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77 | | MCF548X_CACR_BEC /* enable branch cache */ |
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78 | | MCF548X_CACR_IEC /* enable instruction cache */ |
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79 | | MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH) |
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80 | /* set data cache mode to write-through */ |
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81 | | MCF548X_CACR_DESB /* enable data store buffer */ |
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82 | | MCF548X_CACR_DDSP /* data access only in supv. mode */ |
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83 | | MCF548X_CACR_IDSP /* instr. access only in supv. mode */ |
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84 | | MCF548X_CACR_DF; /* disable FPU */ |
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85 | |
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86 | /* |
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87 | * CACR maintenance functions |
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88 | */ |
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89 | |
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90 | void bsp_cacr_set_flags( uint32_t flags) |
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91 | { |
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92 | rtems_interrupt_level level; |
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93 | |
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94 | rtems_interrupt_disable( level); |
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95 | _CPU_cacr_shadow |= flags; |
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96 | m68k_set_cacr( _CPU_cacr_shadow); |
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97 | rtems_interrupt_enable( level); |
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98 | } |
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99 | |
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100 | void bsp_cacr_set_self_clear_flags( uint32_t flags) |
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101 | { |
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102 | rtems_interrupt_level level; |
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103 | uint32_t cacr = 0; |
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104 | |
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105 | rtems_interrupt_disable( level); |
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106 | cacr = _CPU_cacr_shadow | flags; |
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107 | m68k_set_cacr( cacr); |
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108 | rtems_interrupt_enable( level); |
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109 | } |
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110 | |
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111 | void bsp_cacr_clear_flags( uint32_t flags) |
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112 | { |
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113 | rtems_interrupt_level level; |
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114 | |
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115 | rtems_interrupt_disable( level); |
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116 | _CPU_cacr_shadow &= ~flags; |
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117 | m68k_set_cacr( _CPU_cacr_shadow); |
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118 | rtems_interrupt_enable( level); |
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119 | } |
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120 | |
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121 | /* |
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122 | * There is no complete cache lock (only 2 ways of 4 can be locked) |
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123 | */ |
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124 | void _CPU_cache_freeze_data(void) |
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125 | { |
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126 | /* Do nothing */ |
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127 | } |
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128 | |
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129 | void _CPU_cache_unfreeze_data(void) |
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130 | { |
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131 | /* Do nothing */ |
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132 | } |
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133 | |
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134 | void _CPU_cache_freeze_instruction(void) |
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135 | { |
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136 | /* Do nothing */ |
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137 | } |
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138 | |
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139 | void _CPU_cache_unfreeze_instruction(void) |
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140 | { |
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141 | /* Do nothing */ |
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142 | } |
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143 | |
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144 | void _CPU_cache_enable_instruction(void) |
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145 | { |
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146 | bsp_cacr_clear_flags( MCF548X_CACR_IDCM); |
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147 | } |
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148 | |
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149 | void _CPU_cache_disable_instruction(void) |
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150 | { |
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151 | bsp_cacr_set_flags( MCF548X_CACR_IDCM); |
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152 | } |
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153 | |
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154 | void _CPU_cache_invalidate_entire_instruction(void) |
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155 | { |
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156 | bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA); |
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157 | } |
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158 | |
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159 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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160 | { |
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161 | uint32_t a = (uint32_t) addr & ~0x3; |
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162 | |
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163 | asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0)); |
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164 | asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1)); |
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165 | asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2)); |
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166 | asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3)); |
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167 | } |
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168 | |
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169 | void _CPU_cache_enable_data(void) |
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170 | { |
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171 | bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE)); |
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172 | } |
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173 | |
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174 | void _CPU_cache_disable_data(void) |
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175 | { |
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176 | bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE)); |
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177 | } |
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178 | |
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179 | void _CPU_cache_invalidate_entire_data(void) |
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180 | { |
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181 | bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA); |
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182 | } |
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183 | |
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184 | void _CPU_cache_invalidate_1_data_line( const void *addr) |
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185 | { |
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186 | uint32_t a = (uint32_t) addr & ~0x3; |
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187 | |
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188 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0)); |
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189 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1)); |
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190 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2)); |
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191 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3)); |
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192 | } |
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193 | |
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194 | void _CPU_cache_flush_1_data_line( const void *addr) |
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195 | { |
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196 | uint32_t a = (uint32_t) addr & ~0x3; |
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197 | |
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198 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0)); |
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199 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1)); |
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200 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2)); |
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201 | asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3)); |
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202 | } |
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203 | |
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204 | void _CPU_cache_flush_entire_data( void) |
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205 | { |
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206 | uint32_t line = 0; |
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207 | |
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208 | for (line = 0; line < 512; ++line) { |
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209 | _CPU_cache_flush_1_data_line( (const void *) (line * 16)); |
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210 | } |
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211 | } |
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212 | |
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213 | /* |
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214 | * Coldfire acr and mmu settings |
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215 | */ |
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216 | void acr_mmu_mapping(void) |
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217 | { |
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218 | |
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219 | /* |
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220 | * Cache disabled for internal register area (256 kB). |
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221 | * Choose the smallest maskable size of 1MB. |
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222 | */ |
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223 | m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR)) | |
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224 | MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF)) | |
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225 | MCF548X_ACR_E | |
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226 | MCF548X_ACR_SP /* supervisor protection */ | |
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227 | MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ | |
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228 | MCF548X_ACR_CM(CM_OFF_PRECISE)); |
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229 | |
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230 | #ifdef M5484FIREENGINE |
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231 | |
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232 | |
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233 | /* |
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234 | * Cache enabled for entire SDRAM (64 MB) |
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235 | */ |
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236 | m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase)) | |
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237 | MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1)) | |
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238 | MCF548X_ACR_E | |
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239 | MCF548X_ACR_SP /* supervisor protection */ | |
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240 | MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ | |
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241 | MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH)); |
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242 | |
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243 | /* |
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244 | * Cache enabled for entire boot flash (2 MB) |
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245 | */ |
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246 | m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase)) | |
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247 | MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1)) | |
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248 | MCF548X_ACR_E | |
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249 | MCF548X_ACR_SP /* supervisor protection */ | |
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250 | MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ | |
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251 | MCF548X_ACR_CM(CM_ON_COPYBACK)); |
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252 | |
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253 | /* |
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254 | * Cache enabled for entire code flash (16 MB) |
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255 | */ |
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256 | m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase)) | |
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257 | MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1)) | |
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258 | MCF548X_ACR_E | |
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259 | MCF548X_ACR_SP /* supervisor protection */ | |
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260 | MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ | |
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261 | MCF548X_ACR_CM(CM_ON_COPYBACK)); |
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262 | #endif |
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263 | |
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264 | } |
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265 | |
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266 | /* |
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267 | * bsp_start |
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268 | * |
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269 | * This routine does the bulk of the system initialisation. |
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270 | */ |
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271 | void bsp_start( void ) |
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272 | { |
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273 | /* Initialize CACR shadow register */ |
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274 | _CPU_cacr_shadow = BSP_CACR_INIT; |
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275 | |
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276 | /* Switch on FPU in CACR shadow register if necessary */ |
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277 | if ((Configuration_POSIX_API.number_of_initialization_threads > 0) || |
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278 | ((Configuration_RTEMS_API.number_of_initialization_tasks > 0) && |
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279 | (Configuration_RTEMS_API.User_initialization_tasks_table |
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280 | ->attribute_set & RTEMS_FLOATING_POINT) != 0) |
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281 | ) { |
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282 | _CPU_cacr_shadow &= ~MCF548X_CACR_DF; |
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283 | } |
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284 | |
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285 | /* |
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286 | * Load the shadow variable of CACR with initial mode and write it to the |
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287 | * CACR. Interrupts are still disabled, so there is no need for surrounding |
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288 | * rtems_interrupt_enable() / rtems_interrupt_disable(). |
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289 | */ |
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290 | m68k_set_cacr( _CPU_cacr_shadow); |
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291 | |
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292 | /* |
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293 | * do mapping of acr's and/or mmu |
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294 | */ |
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295 | acr_mmu_mapping(); |
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296 | } |
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297 | |
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298 | |
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299 | /* |
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300 | * Get the XLB clock speed |
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301 | */ |
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302 | uint32_t get_CPU_clock_speed(void) |
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303 | { |
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304 | return (uint32_t)BSP_CPU_CLOCK_SPEED; |
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305 | } |
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