source: rtems/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c @ a86f3aac

4.104.114.95
Last change on this file since a86f3aac was 69effbb4, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/11/08 at 10:00:41

added variant to gen68360 BSP
added genmcf548x BSP

  • Property mode set to 100644
File size: 10.7 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic mcf548x BSP                              |
3+-----------------------------------------------------------------+
4| File: bspstart.c                                                |
5+-----------------------------------------------------------------+
6| The file contains the startup code of generic MCF548x BSP       |
7+-----------------------------------------------------------------+
8|                    Copyright (c) 2007                           |
9|                    Embedded Brains GmbH                         |
10|                    Obere Lagerstr. 30                           |
11|                    D-82178 Puchheim                             |
12|                    Germany                                      |
13|                    rtems@embedded-brains.de                     |
14+-----------------------------------------------------------------+
15|                                                                 |
16| Parts of the code has been derived from the "dBUG source code"  |
17| package Freescale is providing for M548X EVBs. The usage of     |
18| the modified or unmodified code and it's integration into the   |
19| generic mcf548x BSP has been done according to the Freescale    |
20| license terms.                                                  |
21|                                                                 |
22| The Freescale license terms can be reviewed in the file         |
23|                                                                 |
24|    Freescale_license.txt                                        |
25|                                                                 |
26+-----------------------------------------------------------------+
27|                                                                 |
28| The generic mcf548x BSP has been developed on the basic         |
29| structures and modules of the av5282 BSP.                       |
30|                                                                 |
31+-----------------------------------------------------------------+
32|                                                                 |
33| The license and distribution terms for this file may be         |
34| found in the file LICENSE in this distribution or at            |
35|                                                                 |
36| http://www.rtems.com/license/LICENSE.                           |
37|                                                                 |
38+-----------------------------------------------------------------+
39|                                                                 |
40|   date                      history                        ID   |
41| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
42| 12.11.07                    1.0                            ras  |
43|                                                                 |
44\*===============================================================*/
45
46#include <bsp.h>
47#include <rtems/libio.h>
48#include <rtems/libcsupport.h>
49#include <string.h>
50
51char *HeapStart, *HeapEnd;
52unsigned long _HeapSize;
53
54extern uint32_t _CPU_cacr_shadow;
55
56extern char _SdramBase[];
57extern char _BootFlashBase[];
58extern char _CodeFlashBase[];
59extern char _SdramSize[];
60extern char _BootFlashSize[];
61extern char _CodeFlashSize[];
62
63/*
64 * CPU-space access
65 */
66#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
67#define m68k_set_acr0(_acr0) asm volatile ("movec %0,#0x0004" : : "d" (_acr0))
68#define m68k_set_acr1(_acr1) asm volatile ("movec %0,#0x0005" : : "d" (_acr1))
69#define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2))
70#define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3))
71
72/*
73 * Set initial cacr mode, mainly enables branch/intruction/data cache and switch off FPU.
74 */
75static uint32_t cacr_mode = (0                                          |
76                             MCF548X_CACR_DEC                           | /* enable data cache */
77                             MCF548X_CACR_BEC                           | /* enable branch cache */
78                             MCF548X_CACR_IEC                           | /* enable instruction cache */
79                             MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH) | /* set data cache mode to write-through */
80                             MCF548X_CACR_DESB                          | /* enable data store buffer */
81                             MCF548X_CACR_DDSP                          | /* data access only in supv. mode */
82                             MCF548X_CACR_IDSP                          | /* instr. access only in supv. mode */
83                             MCF548X_CACR_DF);                            /* disable FPU */
84
85
86/*
87 * Coldfire cacr maintenance functions
88 */
89void _CPU_cacr_set_mode(uint32_t new_cacr_mode)
90{
91rtems_interrupt_level level;
92
93rtems_interrupt_disable(level);
94cacr_mode = new_cacr_mode;
95m68k_set_cacr(new_cacr_mode);
96rtems_interrupt_enable(level);
97}
98
99/*
100 * There is no complete cache lock (only 2 ways of 4 can be locked)
101 */
102void _CPU_cache_freeze_data(void)
103{
104}
105
106void _CPU_cache_unfreeze_data(void)
107{
108}
109
110void _CPU_cache_freeze_instruction(void)
111{
112}
113
114void _CPU_cache_unfreeze_instruction(void)
115{
116}
117
118void _CPU_cache_enable_instruction(void)
119{
120    cacr_mode &= ~(MCF548X_CACR_IDCM);
121    _CPU_cacr_set_mode(cacr_mode);
122}
123
124void _CPU_cache_disable_instruction(void)
125{
126    cacr_mode |= MCF548X_CACR_IDCM;
127    _CPU_cacr_set_mode(cacr_mode);
128}
129
130void _CPU_cache_invalidate_entire_instruction(void)
131{
132        cacr_mode |= MCF548X_CACR_ICINVA;
133    _CPU_cacr_set_mode(cacr_mode);
134}
135
136void _CPU_cache_invalidate_1_instruction_line(const void *addr)
137{
138
139    asm volatile ("cpushl %%ic,(%0)" :: "a" (addr));
140}
141
142void _CPU_cache_enable_data(void)
143{
144    cacr_mode &= ~MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
145    _CPU_cacr_set_mode(cacr_mode);
146}
147
148void _CPU_cache_disable_data(void)
149{
150    cacr_mode |= MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
151    _CPU_cacr_set_mode(cacr_mode);
152}
153
154void _CPU_cache_invalidate_entire_data(void)
155{
156    cacr_mode |= MCF548X_CACR_DCINVA;
157    _CPU_cacr_set_mode(cacr_mode);
158}
159
160void _CPU_cache_invalidate_1_data_line(const void *addr)
161{
162
163   asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
164}
165
166void _CPU_cache_flush_1_data_line(const void *addr)
167{
168   asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
169}
170
171void _CPU_cache_flush_entire_data(void)
172{
173register uint32_t way_cnt, set_cnt, addr;
174
175asm volatile("nop");
176
177for(way_cnt=0; way_cnt<4; way_cnt++)
178  {
179  for(addr=0,set_cnt=0; set_cnt<512; set_cnt++,addr+=0x10)
180    {
181    asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
182    }
183  addr=way_cnt;
184  }
185}
186
187/*
188 *  Use the shared implementations of the following routines
189 */
190
191void bsp_predriver_hook()
192{
193        /* Do nothing */
194}
195
196void bsp_postdriver_hook(void);
197void bsp_libc_init( void *, uint32_t, int );
198void bsp_pretasking_hook(void);         /* m68k version */
199
200void bsp_calc_mem_layout()
201{
202  /*
203   * these labels (!) are defined in the linker command file
204   * or when the linker is invoked
205   * NOTE: the information(size) is the address of the object,
206   * not the object otself
207   */
208  extern char _TopRamReserved [];
209  extern char _WorkspaceBase [];
210
211  /*
212   * compute the memory layout:
213   * - first unused address is Workspace start
214   * - Heap starts at end of workspace
215   * - Heap ends at end of memory - reserved memory area
216   */
217  Configuration.work_space_start = _WorkspaceBase;
218
219  HeapStart = ((char *)Configuration.work_space_start +
220                    Configuration.work_space_size);
221
222  HeapEnd = (void *)(RAM_END - (uint32_t)_TopRamReserved);
223
224  _HeapSize = HeapEnd - HeapStart;
225}
226
227
228/*
229 * Coldfire acr and mmu settings
230 */
231 void acr_mmu_mapping(void)
232   {
233
234  /*
235   * Cache disabled for internal register area (256 kB).
236   * Choose the smallest maskable size of 1MB.
237   */
238  m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR))                           |
239                MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF))                   |
240                MCF548X_ACR_E                                                |
241                MCF548X_ACR_SP               /* supervisor protection */     |
242                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
243                MCF548X_ACR_CM(CM_OFF_PRECISE));
244
245#ifdef M5484FIREENGINE
246
247
248  /*
249   * Cache enabled for entire SDRAM (64 MB)
250   */
251  m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase))                       |
252                MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1))            |
253                MCF548X_ACR_E                                                |
254                MCF548X_ACR_SP               /* supervisor protection */     |
255                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
256                MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
257
258  /*
259   * Cache enabled for entire boot flash (2 MB)
260   */
261  m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase))                   |
262                MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1))        |
263                MCF548X_ACR_E                                                |
264                MCF548X_ACR_SP               /* supervisor protection */     |
265                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
266                MCF548X_ACR_CM(CM_ON_COPYBACK));
267
268  /*
269   * Cache enabled for entire code flash (16 MB)
270   */
271  m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase))                   |
272                MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1))        |
273                MCF548X_ACR_E                                                |
274                MCF548X_ACR_SP               /* supervisor protection */     |
275                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
276                MCF548X_ACR_CM(CM_ON_COPYBACK));
277#endif
278
279   }
280
281/*
282 *  bsp_start
283 *
284 *  This routine does the bulk of the system initialisation.
285 */
286void bsp_start( void )
287{
288  extern char _RamSize[];
289  extern unsigned long  _M68k_Ramsize;
290
291  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
292
293  /*
294   *  Allocate the memory for the RTEMS Work Space and Heap.  This can come from
295   *  a variety of places: hard coded address, malloc'ed from outside
296   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
297   *  typically done by stock BSPs) by subtracting the required amount
298   *  of work space from the last physical address on the CPU board.
299   */
300  bsp_calc_mem_layout();
301
302  /*
303   * do mapping of acr's and/or mmu
304   */
305  acr_mmu_mapping();
306
307  /*
308   * Load the shadow variable of cacr with initial mode and write it to the cacr.
309   * Interrupts are still disabled, so there is no need for surrounding rtems_interrupt_enable()/rtems_interrupt_disable()
310   */
311  _CPU_cacr_shadow = cacr_mode;
312  m68k_set_cacr(_CPU_cacr_shadow);
313
314}
315
316
317/*
318 * Get the XLB clock speed
319 */
320uint32_t get_CPU_clock_speed(void)
321{
322    return (uint32_t)BSP_CPU_CLOCK_SPEED;
323}
Note: See TracBrowser for help on using the repository browser.