source: rtems/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c @ 939439d3

4.104.115
Last change on this file since 939439d3 was 939439d3, checked in by Joel Sherrill <joel.sherrill@…>, on 09/16/08 at 22:16:01

2008-09-16 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, startup/bspstart.c, startup/init548x.c, startup/linkcmds, startup/linkcmds.m5484FireEngine.flash: Use top level shared bsp_get_work_area() implementation.
  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic mcf548x BSP                              |
3+-----------------------------------------------------------------+
4| File: bspstart.c                                                |
5+-----------------------------------------------------------------+
6| The file contains the startup code of generic MCF548x BSP       |
7+-----------------------------------------------------------------+
8|                    Copyright (c) 2007                           |
9|                    Embedded Brains GmbH                         |
10|                    Obere Lagerstr. 30                           |
11|                    D-82178 Puchheim                             |
12|                    Germany                                      |
13|                    rtems@embedded-brains.de                     |
14+-----------------------------------------------------------------+
15|                                                                 |
16| Parts of the code has been derived from the "dBUG source code"  |
17| package Freescale is providing for M548X EVBs. The usage of     |
18| the modified or unmodified code and it's integration into the   |
19| generic mcf548x BSP has been done according to the Freescale    |
20| license terms.                                                  |
21|                                                                 |
22| The Freescale license terms can be reviewed in the file         |
23|                                                                 |
24|    Freescale_license.txt                                        |
25|                                                                 |
26+-----------------------------------------------------------------+
27|                                                                 |
28| The generic mcf548x BSP has been developed on the basic         |
29| structures and modules of the av5282 BSP.                       |
30|                                                                 |
31+-----------------------------------------------------------------+
32|                                                                 |
33| The license and distribution terms for this file may be         |
34| found in the file LICENSE in this distribution or at            |
35|                                                                 |
36| http://www.rtems.com/license/LICENSE.                           |
37|                                                                 |
38+-----------------------------------------------------------------+
39|                                                                 |
40|   date                      history                        ID   |
41| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
42| 12.11.07                    1.0                            ras  |
43|                                                                 |
44\*===============================================================*/
45
46#include <bsp.h>
47
48extern uint32_t _CPU_cacr_shadow;
49
50/*
51* These labels (!) are defined in the linker command file or when the linker is
52* invoked.
53* NOTE: The information (size) is the address of the object, not the object
54* itself.
55*/
56
57extern char _SdramBase[];
58extern char _BootFlashBase[];
59extern char _CodeFlashBase[];
60extern char _SdramSize[];
61extern char _BootFlashSize[];
62extern char _CodeFlashSize[];
63extern char _TopRamReserved [];
64extern char WorkAreaBase [];
65
66/*
67 * CPU-space access
68 */
69#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
70#define m68k_set_acr0(_acr0) asm volatile ("movec %0,#0x0004" : : "d" (_acr0))
71#define m68k_set_acr1(_acr1) asm volatile ("movec %0,#0x0005" : : "d" (_acr1))
72#define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2))
73#define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3))
74
75/*
76 * Set initial cacr mode, mainly enables branch/intruction/data cache and switch off FPU.
77 */
78static uint32_t cacr_mode = (0                                          |
79                             MCF548X_CACR_DEC                           | /* enable data cache */
80                             MCF548X_CACR_BEC                           | /* enable branch cache */
81                             MCF548X_CACR_IEC                           | /* enable instruction cache */
82                             MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH) | /* set data cache mode to write-through */
83                             MCF548X_CACR_DESB                          | /* enable data store buffer */
84                             MCF548X_CACR_DDSP                          | /* data access only in supv. mode */
85                             MCF548X_CACR_IDSP                          | /* instr. access only in supv. mode */
86                             MCF548X_CACR_DF);                            /* disable FPU */
87
88
89/*
90 * Coldfire cacr maintenance functions
91 */
92void _CPU_cacr_set_mode(uint32_t new_cacr_mode)
93{
94rtems_interrupt_level level;
95
96rtems_interrupt_disable(level);
97cacr_mode = new_cacr_mode;
98m68k_set_cacr(new_cacr_mode);
99rtems_interrupt_enable(level);
100}
101
102/*
103 * There is no complete cache lock (only 2 ways of 4 can be locked)
104 */
105void _CPU_cache_freeze_data(void)
106{
107}
108
109void _CPU_cache_unfreeze_data(void)
110{
111}
112
113void _CPU_cache_freeze_instruction(void)
114{
115}
116
117void _CPU_cache_unfreeze_instruction(void)
118{
119}
120
121void _CPU_cache_enable_instruction(void)
122{
123    cacr_mode &= ~(MCF548X_CACR_IDCM);
124    _CPU_cacr_set_mode(cacr_mode);
125}
126
127void _CPU_cache_disable_instruction(void)
128{
129    cacr_mode |= MCF548X_CACR_IDCM;
130    _CPU_cacr_set_mode(cacr_mode);
131}
132
133void _CPU_cache_invalidate_entire_instruction(void)
134{
135        cacr_mode |= MCF548X_CACR_ICINVA;
136    _CPU_cacr_set_mode(cacr_mode);
137}
138
139void _CPU_cache_invalidate_1_instruction_line(const void *addr)
140{
141
142    asm volatile ("cpushl %%ic,(%0)" :: "a" (addr));
143}
144
145void _CPU_cache_enable_data(void)
146{
147    cacr_mode &= ~MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
148    _CPU_cacr_set_mode(cacr_mode);
149}
150
151void _CPU_cache_disable_data(void)
152{
153    cacr_mode |= MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
154    _CPU_cacr_set_mode(cacr_mode);
155}
156
157void _CPU_cache_invalidate_entire_data(void)
158{
159    cacr_mode |= MCF548X_CACR_DCINVA;
160    _CPU_cacr_set_mode(cacr_mode);
161}
162
163void _CPU_cache_invalidate_1_data_line(const void *addr)
164{
165
166   asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
167}
168
169void _CPU_cache_flush_1_data_line(const void *addr)
170{
171   asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
172}
173
174void _CPU_cache_flush_entire_data(void)
175{
176register uint32_t way_cnt, set_cnt, addr;
177
178asm volatile("nop");
179
180for(way_cnt=0; way_cnt<4; way_cnt++)
181  {
182  for(addr=0,set_cnt=0; set_cnt<512; set_cnt++,addr+=0x10)
183    {
184    asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
185    }
186  addr=way_cnt;
187  }
188}
189
190/*
191 * Coldfire acr and mmu settings
192 */
193 void acr_mmu_mapping(void)
194   {
195
196  /*
197   * Cache disabled for internal register area (256 kB).
198   * Choose the smallest maskable size of 1MB.
199   */
200  m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR))                           |
201                MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF))                   |
202                MCF548X_ACR_E                                                |
203                MCF548X_ACR_SP               /* supervisor protection */     |
204                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
205                MCF548X_ACR_CM(CM_OFF_PRECISE));
206
207#ifdef M5484FIREENGINE
208
209
210  /*
211   * Cache enabled for entire SDRAM (64 MB)
212   */
213  m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase))                       |
214                MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1))            |
215                MCF548X_ACR_E                                                |
216                MCF548X_ACR_SP               /* supervisor protection */     |
217                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
218                MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
219
220  /*
221   * Cache enabled for entire boot flash (2 MB)
222   */
223  m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase))                   |
224                MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1))        |
225                MCF548X_ACR_E                                                |
226                MCF548X_ACR_SP               /* supervisor protection */     |
227                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
228                MCF548X_ACR_CM(CM_ON_COPYBACK));
229
230  /*
231   * Cache enabled for entire code flash (16 MB)
232   */
233  m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase))                   |
234                MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1))        |
235                MCF548X_ACR_E                                                |
236                MCF548X_ACR_SP               /* supervisor protection */     |
237                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
238                MCF548X_ACR_CM(CM_ON_COPYBACK));
239#endif
240
241   }
242
243/*
244 *  bsp_start
245 *
246 *  This routine does the bulk of the system initialisation.
247 */
248void bsp_start( void )
249{
250  /*
251   * do mapping of acr's and/or mmu
252   */
253  acr_mmu_mapping();
254
255  /*
256   * Load the shadow variable of cacr with initial mode and write it to the cacr.
257   * Interrupts are still disabled, so there is no need for surrounding rtems_interrupt_enable()/rtems_interrupt_disable()
258   */
259  _CPU_cacr_shadow = cacr_mode;
260  m68k_set_cacr(_CPU_cacr_shadow);
261
262}
263
264
265/*
266 * Get the XLB clock speed
267 */
268uint32_t get_CPU_clock_speed(void)
269{
270    return (uint32_t)BSP_CPU_CLOCK_SPEED;
271}
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