source: rtems/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c @ 28b38f3

4.104.115
Last change on this file since 28b38f3 was 28b38f3, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 02/25/10 at 11:01:35

combine all checks for missing MAC address
enable FPU, if POSIX init task present
explicitly disable all edge port interrupts

  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic mcf548x BSP                              |
3+-----------------------------------------------------------------+
4| File: bspstart.c                                                |
5+-----------------------------------------------------------------+
6| The file contains the startup code of generic MCF548x BSP       |
7+-----------------------------------------------------------------+
8|                    Copyright (c) 2007                           |
9|                    Embedded Brains GmbH                         |
10|                    Obere Lagerstr. 30                           |
11|                    D-82178 Puchheim                             |
12|                    Germany                                      |
13|                    rtems@embedded-brains.de                     |
14+-----------------------------------------------------------------+
15|                                                                 |
16| Parts of the code has been derived from the "dBUG source code"  |
17| package Freescale is providing for M548X EVBs. The usage of     |
18| the modified or unmodified code and it's integration into the   |
19| generic mcf548x BSP has been done according to the Freescale    |
20| license terms.                                                  |
21|                                                                 |
22| The Freescale license terms can be reviewed in the file         |
23|                                                                 |
24|    Freescale_license.txt                                        |
25|                                                                 |
26+-----------------------------------------------------------------+
27|                                                                 |
28| The generic mcf548x BSP has been developed on the basic         |
29| structures and modules of the av5282 BSP.                       |
30|                                                                 |
31+-----------------------------------------------------------------+
32|                                                                 |
33| The license and distribution terms for this file may be         |
34| found in the file LICENSE in this distribution or at            |
35|                                                                 |
36| http://www.rtems.com/license/LICENSE.                           |
37|                                                                 |
38+-----------------------------------------------------------------+
39|                                                                 |
40|   date                      history                        ID   |
41| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
42| 12.11.07                    1.0                            ras  |
43|                                                                 |
44\*===============================================================*/
45
46#include <bsp.h>
47
48extern uint32_t _CPU_cacr_shadow;
49
50/*
51* These labels (!) are defined in the linker command file or when the linker is
52* invoked.
53* NOTE: The information (size) is the address of the object, not the object
54* itself.
55*/
56
57extern char _SdramBase[];
58extern char _BootFlashBase[];
59extern char _CodeFlashBase[];
60extern char _SdramSize[];
61extern char _BootFlashSize[];
62extern char _CodeFlashSize[];
63extern char _TopRamReserved [];
64extern char WorkAreaBase [];
65
66/*
67 * CPU-space access
68 */
69#define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2))
70#define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3))
71
72/*
73 * Set initial cacr mode, mainly enables branch/intruction/data cache and
74 * switch off FPU.
75 */
76static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */
77  | MCF548X_CACR_BEC /* enable branch cache */
78  | MCF548X_CACR_IEC /* enable instruction cache */
79  | MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH)
80      /* set data cache mode to write-through */
81  | MCF548X_CACR_DESB /* enable data store buffer */
82  | MCF548X_CACR_DDSP /* data access only in supv. mode */
83  | MCF548X_CACR_IDSP /* instr. access only in supv. mode */
84  | MCF548X_CACR_DF; /* disable FPU */
85
86/*
87 * CACR maintenance functions
88 */
89
90void bsp_cacr_set_flags( uint32_t flags)
91{
92  rtems_interrupt_level level;
93
94  rtems_interrupt_disable( level);
95  _CPU_cacr_shadow |= flags;
96  m68k_set_cacr( _CPU_cacr_shadow);
97  rtems_interrupt_enable( level);
98}
99
100void bsp_cacr_set_self_clear_flags( uint32_t flags)
101{
102  rtems_interrupt_level level;
103  uint32_t cacr = 0;
104
105  rtems_interrupt_disable( level);
106  cacr = _CPU_cacr_shadow | flags;
107  m68k_set_cacr( cacr);
108  rtems_interrupt_enable( level);
109}
110
111void bsp_cacr_clear_flags( uint32_t flags)
112{
113  rtems_interrupt_level level;
114
115  rtems_interrupt_disable( level);
116  _CPU_cacr_shadow &= ~flags;
117  m68k_set_cacr( _CPU_cacr_shadow);
118  rtems_interrupt_enable( level);
119}
120
121/*
122 * There is no complete cache lock (only 2 ways of 4 can be locked)
123 */
124void _CPU_cache_freeze_data(void)
125{
126  /* Do nothing */
127}
128
129void _CPU_cache_unfreeze_data(void)
130{
131  /* Do nothing */
132}
133
134void _CPU_cache_freeze_instruction(void)
135{
136  /* Do nothing */
137}
138
139void _CPU_cache_unfreeze_instruction(void)
140{
141  /* Do nothing */
142}
143
144void _CPU_cache_enable_instruction(void)
145{
146  bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
147}
148
149void _CPU_cache_disable_instruction(void)
150{
151  bsp_cacr_set_flags( MCF548X_CACR_IDCM);
152}
153
154void _CPU_cache_invalidate_entire_instruction(void)
155{
156  bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
157}
158
159void _CPU_cache_invalidate_1_instruction_line(const void *addr)
160{
161  uint32_t a = (uint32_t) addr & ~0x3;
162
163  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
164  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
165  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
166  asm volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
167}
168
169void _CPU_cache_enable_data(void)
170{
171  bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
172}
173
174void _CPU_cache_disable_data(void)
175{
176  bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
177}
178
179void _CPU_cache_invalidate_entire_data(void)
180{
181  bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
182}
183
184void _CPU_cache_invalidate_1_data_line( const void *addr)
185{
186  uint32_t a = (uint32_t) addr & ~0x3;
187
188  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
189  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
190  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
191  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
192}
193
194void _CPU_cache_flush_1_data_line( const void *addr)
195{
196  uint32_t a = (uint32_t) addr & ~0x3;
197
198  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
199  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
200  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
201  asm volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
202}
203
204void _CPU_cache_flush_entire_data( void)
205{
206  uint32_t line = 0;
207
208  for (line = 0; line < 512; ++line) {
209    _CPU_cache_flush_1_data_line( (const void *) (line * 16));
210  }
211}
212
213/*
214 * Coldfire acr and mmu settings
215 */
216 void acr_mmu_mapping(void)
217   {
218
219  /*
220   * Cache disabled for internal register area (256 kB).
221   * Choose the smallest maskable size of 1MB.
222   */
223  m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR))                           |
224                MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF))                   |
225                MCF548X_ACR_E                                                |
226                MCF548X_ACR_SP               /* supervisor protection */     |
227                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
228                MCF548X_ACR_CM(CM_OFF_PRECISE));
229
230#ifdef M5484FIREENGINE
231
232
233  /*
234   * Cache enabled for entire SDRAM (64 MB)
235   */
236  m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase))                       |
237                MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1))            |
238                MCF548X_ACR_E                                                |
239                MCF548X_ACR_SP               /* supervisor protection */     |
240                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
241                MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
242
243  /*
244   * Cache enabled for entire boot flash (2 MB)
245   */
246  m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase))                   |
247                MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1))        |
248                MCF548X_ACR_E                                                |
249                MCF548X_ACR_SP               /* supervisor protection */     |
250                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
251                MCF548X_ACR_CM(CM_ON_COPYBACK));
252
253  /*
254   * Cache enabled for entire code flash (16 MB)
255   */
256  m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase))                   |
257                MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1))        |
258                MCF548X_ACR_E                                                |
259                MCF548X_ACR_SP               /* supervisor protection */     |
260                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
261                MCF548X_ACR_CM(CM_ON_COPYBACK));
262#endif
263
264   }
265
266/*
267 *  bsp_start
268 *
269 *  This routine does the bulk of the system initialisation.
270 */
271void bsp_start( void )
272{
273  /* Initialize CACR shadow register */
274  _CPU_cacr_shadow = BSP_CACR_INIT;
275
276  /* Switch on FPU in CACR shadow register if necessary */
277  if ((Configuration_POSIX_API.number_of_initialization_threads > 0) ||
278      ((Configuration_RTEMS_API.number_of_initialization_tasks > 0) &&
279       (Configuration_RTEMS_API.User_initialization_tasks_table
280        ->attribute_set & RTEMS_FLOATING_POINT) != 0)
281      ) {
282    _CPU_cacr_shadow &= ~MCF548X_CACR_DF;
283  }
284
285  /*
286   * Load the shadow variable of CACR with initial mode and write it to the
287   * CACR.  Interrupts are still disabled, so there is no need for surrounding
288   * rtems_interrupt_enable() / rtems_interrupt_disable().
289   */
290  m68k_set_cacr( _CPU_cacr_shadow);
291
292  /*
293   * do mapping of acr's and/or mmu
294   */
295  acr_mmu_mapping();
296}
297
298
299/*
300 * Get the XLB clock speed
301 */
302uint32_t get_CPU_clock_speed(void)
303{
304    return (uint32_t)BSP_CPU_CLOCK_SPEED;
305}
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