1 | /*===============================================================*\ |
---|
2 | | Project: RTEMS generic mcf548x BSP | |
---|
3 | +-----------------------------------------------------------------+ |
---|
4 | | File: README | |
---|
5 | +-----------------------------------------------------------------+ |
---|
6 | | This is the README for the generic MCF548x BSP. | |
---|
7 | +-----------------------------------------------------------------+ |
---|
8 | | Copyright (c) 2007 | |
---|
9 | | Embedded Brains GmbH | |
---|
10 | | Obere Lagerstr. 30 | |
---|
11 | | D-82178 Puchheim | |
---|
12 | | Germany | |
---|
13 | | rtems@embedded-brains.de | |
---|
14 | +-----------------------------------------------------------------+ |
---|
15 | | | |
---|
16 | | Parts of the code has been derived from the "dBUG source code" | |
---|
17 | | package Freescale is providing for M548X EVBs. The usage of | |
---|
18 | | the modified or unmodified code and it's integration into the | |
---|
19 | | generic mcf548x BSP has been done according to the Freescale | |
---|
20 | | license terms. | |
---|
21 | | | |
---|
22 | | The Freescale license terms can be reviewed in the file | |
---|
23 | | | |
---|
24 | | Freescale_license.txt | |
---|
25 | | | |
---|
26 | +-----------------------------------------------------------------+ |
---|
27 | | | |
---|
28 | | The generic mcf548x BSP has been developed on the basic | |
---|
29 | | structures and modules of the av5282 BSP. | |
---|
30 | | | |
---|
31 | +-----------------------------------------------------------------+ |
---|
32 | | | |
---|
33 | | The license and distribution terms for this file may be | |
---|
34 | | found in the file LICENSE in this distribution or at | |
---|
35 | | | |
---|
36 | | http://www.rtems.com/license/LICENSE. | |
---|
37 | | | |
---|
38 | +-----------------------------------------------------------------+ |
---|
39 | | | |
---|
40 | | date history ID | |
---|
41 | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
---|
42 | | 12.11.07 1.0 ras | |
---|
43 | | | |
---|
44 | \*===============================================================*/ |
---|
45 | |
---|
46 | |
---|
47 | Description: Generic mcf548x BSP |
---|
48 | ============ |
---|
49 | CPU: MCF548x, 200MHz |
---|
50 | XLB: 100 MHz, which is the main clock for all onchip peripherals |
---|
51 | RAM: 64M (m5484FireEngine) |
---|
52 | Boot-Flash: 2M (m5484FireEngine) |
---|
53 | Code-Flash: 16M (m5484FireEngine) |
---|
54 | Core-SRAM: 8K |
---|
55 | Core-SysRAM: 32K |
---|
56 | |
---|
57 | |
---|
58 | The genmcf548x supports the Fresscale m5484FireEngine EVB. |
---|
59 | |
---|
60 | ACKNOWLEDGEMENTS: |
---|
61 | ================= |
---|
62 | This BSP is based on the |
---|
63 | |
---|
64 | av5282 BSP |
---|
65 | |
---|
66 | and the work of |
---|
67 | |
---|
68 | D. Peter Siddons |
---|
69 | Brett Swimley |
---|
70 | Jay Monkman |
---|
71 | Eric Norum |
---|
72 | Mike Bertosh |
---|
73 | |
---|
74 | BSP INFO: |
---|
75 | ========= |
---|
76 | BSP NAME: genmcf548x |
---|
77 | BOARD: m5484FireEngine (freescale), |
---|
78 | CPU FAMILY: ColdFire 548x |
---|
79 | CPU: MCF5484 |
---|
80 | FPU: MCF548x FPU, context switch supported by RTEMS multitasking |
---|
81 | EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context) |
---|
82 | |
---|
83 | PERIPHERALS |
---|
84 | =========== |
---|
85 | TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose) |
---|
86 | RESOLUTION: System tick 10 millieconds (via SLT0) |
---|
87 | SERIAL PORTS: Internal PSC 0-3 |
---|
88 | NETWORKING: Internal 10/100MHz FEC (not supported yet) |
---|
89 | |
---|
90 | DRIVER INFORMATION |
---|
91 | ================== |
---|
92 | CLOCK DRIVER: SLT0 |
---|
93 | TIMER DRIVER: SLT1 (diagnostics) |
---|
94 | TTY DRIVER: PSC0-3 |
---|
95 | |
---|
96 | STDIO |
---|
97 | ===== |
---|
98 | PORT: PSC0 (UART mode) terminal |
---|
99 | ELECTRICAL: RS-232 |
---|
100 | BAUD: 9600 |
---|
101 | BITS PER CHARACTER: 8 |
---|
102 | PARITY: None |
---|
103 | STOP BITS: 1 |
---|
104 | MODES: Interrupt driven (polled mode alternatively) |
---|
105 | |
---|
106 | |
---|
107 | Memory map as set up by BSP initialization |
---|
108 | |
---|
109 | m5484FireEngine: |
---|
110 | |
---|
111 | +--------------------------------------------------+ |
---|
112 | 0000 0000 | 64 MByte SDRAM (external) | 03FF FFFF |
---|
113 | . . |
---|
114 | . . |
---|
115 | . . |
---|
116 | |
---|
117 | |
---|
118 | m5484FireEngine: |
---|
119 | |
---|
120 | |
---|
121 | | | 0FFF FFFF |
---|
122 | +--------------------------------------------------+ |
---|
123 | 1000 0000 | internal per. registers via MBAR | 1003 FFFF |
---|
124 | . . |
---|
125 | . . |
---|
126 | . . |
---|
127 | | | |
---|
128 | +--------------------------------------------------+ |
---|
129 | 2000 0000 | 8K core SRAM (internal) | 2000 1FFF |
---|
130 | . . |
---|
131 | . . |
---|
132 | . . |
---|
133 | |
---|
134 | m5484FireEngine: |
---|
135 | |
---|
136 | | | |
---|
137 | +--------------------------------------------------+ |
---|
138 | E000 0000 | 16M code flash (external) | E0FF FFFF |
---|
139 | . . |
---|
140 | . . |
---|
141 | . . |
---|
142 | | | |
---|
143 | +--------------------------------------------------+ |
---|
144 | FF80 0000 | External 8 MByte Flash memory | FF9F FFFF |
---|
145 | . . |
---|
146 | . . |
---|
147 | . . |
---|
148 | | | FFFF FFFF |
---|
149 | +--------------------------------------------------+ |
---|
150 | |
---|
151 | ============================================================================ |
---|
152 | |
---|
153 | Interrupt map |
---|
154 | |
---|
155 | +-----+-----------------------------------------------------------------------+ |
---|
156 | | | PRIORITY | |
---|
157 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
158 | |LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
---|
159 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
160 | | 7 | | | | | | | | | |
---|
161 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
162 | | 6 | | | | | | | | | |
---|
163 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
164 | | 5 | | | | | | | | | |
---|
165 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
166 | | 4 | | | | | | | | SLT0 | |
---|
167 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
168 | | 3 | PSC 0 | PSC 1 | PSC 2 | PSC 3 | | | | | |
---|
169 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
170 | | 2 | | | | | | | | | |
---|
171 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
172 | | 1 | | | | | | | | | |
---|
173 | +-----+--------+--------+--------+--------+--------+--------+--------+--------+ |
---|
174 | |
---|
175 | ============================================================================ |
---|
176 | |
---|
177 | TIMING TESTS |
---|
178 | ************************** |
---|
179 | |
---|
180 | tbd. |
---|