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source: rtems/c/src/lib/libbsp/m68k/genmcf548x/README @ 6440903c

4.115

Last change on this file since 6440903c was a9d0c6ec, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 10/16/09 at 12:53:50
added support for COBRA5475 board
Property mode set to `100644`
File size: 10.7 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic mcf548x BSP \|
3	+-----------------------------------------------------------------+
4	\| File: README \|
5	+-----------------------------------------------------------------+
6	\| This is the README for the generic MCF548x BSP. \|
7	+-----------------------------------------------------------------+
8	\| Copyright (c) 2007 \|
9	\| Embedded Brains GmbH \|
10	\| Obere Lagerstr. 30 \|
11	\| D-82178 Puchheim \|
12	\| Germany \|
13	\| rtems@embedded-brains.de \|
14	+-----------------------------------------------------------------+
15	\| \|
16	\| Parts of the code has been derived from the "dBUG source code" \|
17	\| package Freescale is providing for M548X EVBs. The usage of \|
18	\| the modified or unmodified code and it's integration into the \|
19	\| generic mcf548x BSP has been done according to the Freescale \|
20	\| license terms. \|
21	\| \|
22	\| The Freescale license terms can be reviewed in the file \|
23	\| \|
24	\| Freescale_license.txt \|
25	\| \|
26	+-----------------------------------------------------------------+
27	\| \|
28	\| The generic mcf548x BSP has been developed on the basic \|
29	\| structures and modules of the av5282 BSP. \|
30	\| \|
31	+-----------------------------------------------------------------+
32	\| \|
33	\| The license and distribution terms for this file may be \|
34	\| found in the file LICENSE in this distribution or at \|
35	\| \|
36	\| http://www.rtems.com/license/LICENSE. \|
37	\| \|
38	+-----------------------------------------------------------------+
39	\| \|
40	\| date history ID \|
41	\| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ \|
42	\| 12.11.07 1.0 ras \|
43	\| \|
44	\===============================================================/
45
46
47	Description: Generic mcf548x BSP
48
49	The genmcf548x supports several boards based on the Freescale MCF547x/8x
50	ColdFire microcontrollers
51
52	Supported Hardware: mcf5484FireEngine
53	=============================
54	CPU: MCF548x, 200MHz
55	XLB: 100 MHz, which is the main clock for all onchip peripherals
56	RAM: 64M (m5484FireEngine)
57	Boot-Flash: 2M (m5484FireEngine)
58	Code-Flash: 16M (m5484FireEngine)
59	Core-SRAM: 8K
60	Core-SysRAM: 32K
61	Boot-Monitor:None
62
63	Supported Hardware: COBRA5475
64	=============================
65	CPU: MCF5475, 266MHz
66	XLB: 132 MHz, which is the main clock for all onchip peripherals
67	RAM: 128M
68	Boot-Flash: 32M
69	Core-SRAM: 8K
70	Core-SysRAM: 32K
71	Boot-Monitor:DBug
72
73
74	ACKNOWLEDGEMENTS:
75	=================
76	This BSP is based on the
77
78	av5282 BSP
79
80	and the work of
81
82	D. Peter Siddons
83	Brett Swimley
84	Jay Monkman
85	Eric Norum
86	Mike Bertosh
87
88	BSP INFO:
89	=========
90	BSP NAME: genmcf548x
91	BOARD: various MCF547x/8x based boards
92	CPU FAMILY: ColdFire 548x
93	CPU: MCF5475/MCF5484
94	FPU: MCF548x FPU, context switch supported by RTEMS multitasking
95	EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context)
96
97	PERIPHERALS
98	===========
99	TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose)
100	RESOLUTION: System tick 10 millieconds (via SLT0)
101	SERIAL PORTS: Internal PSC 0-3
102	NETWORKING: Internal 10/100MHz FEC on two channels
103
104	DRIVER INFORMATION
105	==================
106	CLOCK DRIVER: SLT0
107	TIMER DRIVER: SLT1 (diagnostics)
108	TTY DRIVER: PSC0-3
109
110	STDIO
111	=====
112	PORT: PSC0 (UART mode) terminal
113	ELECTRICAL: RS-232
114	BAUD: 9600
115	BITS PER CHARACTER: 8
116	PARITY: None
117	STOP BITS: 1
118	MODES: Interrupt driven (polled mode alternatively)
119
120
121	----------------------------------------------------------------------
122
123	Memory map of m5484FireEngine as set up by BSP initialization:
124
125	+--------------------------------------------------+
126	0000 0000 \| 64 MByte SDRAM (external) \| 03FF FFFF
127	. .
128	. .
129	. .
130
131
132	m5484FireEngine:
133
134
135	\| \| 0FFF FFFF
136	+--------------------------------------------------+
137	1000 0000 \| internal per. registers via MBAR \| 1003 FFFF
138	. .
139	. .
140	. .
141	\| \|
142	+--------------------------------------------------+
143	2000 0000 \| 8K core SRAM (internal) \| 2000 1FFF
144	. .
145	. .
146	. .
147
148	m5484FireEngine:
149
150	\| \|
151	+--------------------------------------------------+
152	E000 0000 \| 16M code flash (external) \| E0FF FFFF
153	. .
154	. .
155	. .
156	\| \|
157	+--------------------------------------------------+
158	FF80 0000 \| External 8 MByte Flash memory \| FF9F FFFF
159	. .
160	. .
161	. .
162	\| \| FFFF FFFF
163	+--------------------------------------------------+
164
165
166	----------------------------------------------------------------------
167
168	Memory map for COBRA5475 as set up by DBug:
169
170	+--------------------------------------------------+
171	F000 0000 \| 128 MByte SDRAM (external) \|
172	. .
173	. (first 256KByte reserved for DBug) .
174	. . F03F FFFF
175	F040 0000 \| \|
176	. .
177	. .
178	. .
179	\| \| F7FF FFFF
180	+--------------------------------------------------+
181	FC00 0000 \| 32M code flash (external) \|
182	. .
183	. .
184	. .
185	\| \| FDFF FFFF
186	+--------------------------------------------------+
187	FE00 0000 \| internal per. registers via MBAR \|
188	. .
189	. .
190	. .
191	\| \| FE03 FFFF
192	+--------------------------------------------------+
193	FF00 0000 \| 8K core SRAM (internal) \|
194	. .
195	. .
196	. .
197	\| \| FF00 1FFF
198	+--------------------------------------------------+
199
200	============================================================================
201
202	Interrupt map
203
204	+-----+-----------------------------------------------------------------------+
205	\| \| PRIORITY \|
206	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
207	\|LEVEL\| 7 \| 6 \| 5 \| 4 \| 3 \| 2 \| 1 \| 0 \|
208	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
209	\| 7 \| \| \| \| \| \| \| \| \|
210	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
211	\| 6 \| \| \| \| \| \| \| \| \|
212	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
213	\| 5 \| \| \| \| \| \| \| \| \|
214	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
215	\| 4 \| \| \| \| \| \| \| \| SLT0 \|
216	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
217	\| 3 \| PSC 0 \| PSC 1 \| PSC 2 \| PSC 3 \| \| \| \| \|
218	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
219	\| 2 \| \| \| \| \| FEC0/1 \| MCDMA \| \| \|
220	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
221	\| 1 \| \| \| \| \| \| \| \| \|
222	+-----+--------+--------+--------+--------+--------+--------+--------+--------+
223
224	============================================================================
225
226	TIMING TESTS
227	**************************
228
229	tbd.

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