source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ f99538d

4.104.114.84.95
Last change on this file since f99538d was bdf531ee, checked in by Joel Sherrill <joel.sherrill@…>, on 03/06/96 at 22:25:11

include of mc68360.h changed to m68360.h to reflect filename change.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 * Initialize 68360 hardware
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
15#include "m68360.h"
16
17void
18_Init68360 (void)
19{
20        int i;
21        extern void *_RomBase, *_RamBase;
22        m68k_isr_entry *vbr;
23        extern void _ClearBSSAndStart (void);
24
25        /*
26         * Step 6: Is this a power-up reset?
27         * For now we just ignore this and do *all* the steps
28         * Someday we might want to:
29         *      if (Hard, Loss of Clock, Power-up)
30         *              Do all steps
31         *      else if (Double bus fault, watchdog or soft reset)
32         *              Skip to step 12
33         *      else (must be a CPU32+ reset command)
34         *              Skip to step 14
35         */
36
37        /*
38         * Step 7: Deal with clock synthesizer
39         * HARDWARE:
40         *      Change if you're not using an external 25 MHz oscillator.
41         */
42        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
43        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,  */
44                                        /* no LPSTOP slowdown, PLL X1 */
45        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
46
47        /*
48         * Step 8: Initialize system protection
49         *      Disable watchdog FIXME: Should use watchdog!!!!
50         *      Watchdog causes system reset
51         *      Fastest watchdog timeout
52         *      Enable double bus fault monitor
53         *      Enable bus monitor external
54         *      128 clocks for external timeout
55         */
56        m360.sypcr = 0x4F;
57
58        /*
59         * Step 9: Clear parameter RAM and reset communication processor module
60         */
61        for (i = 0 ; i < 192  ; i += sizeof (long)) {
62                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
63                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
64                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
65                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
66        }
67        m360.cr = M360_CR_RST | M360_CR_FLG;
68
69        /*
70         * Step 10: Write PEPAR
71         *      SINTOUT not used (CPU32+ mode)
72         *      CF1MODE=00 (CONFIG1 input)
73         *      RAS1* double drive
74         *      A31-A28
75         *      OE* output
76         *      CAS2* / CAS3*
77         *      CAS0* / CAS1*
78         *      CS7*
79         *      AVEC*
80         * HARDWARE:
81         *      Change if you are using a different memory configuration
82         *      (static RAM, external address multiplexing, etc).
83         */
84        m360.pepar = 0x0100;
85
86        /*
87         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
88         *      1024 addresses per DRAM page (1M DRAM chips)
89         *      60 nsec DRAM
90         *      180 nsec ROM (3 wait states)
91         * HARDWARE:
92         *      Change if you are using a different memory configuration
93         */
94        m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | M360_GMR_RCYC(0) |
95                        M360_GMR_PGS(3) | M360_GMR_DPS_32BIT | M360_GMR_NCS |
96                        M360_GMR_GAMX;
97        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
98                                                        M360_MEMC_BR_V;
99        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
100                                                        M360_MEMC_OR_8BIT;
101
102        /*
103         * Step 12: Initialize the system RAM
104         *      Set up option/base registers
105         *              4 MB DRAM
106         *              60 nsec DRAM
107         *      Wait for chips to power up
108         *      Perform 8 read cycles
109         *      Set all parity bits to correct state
110         *      Enable parity checking
111         * HARDWARE:
112         *      Change if you are using a different memory configuration
113         */
114        m360.memc[1].or = M360_MEMC_OR_TCYC(0) | M360_MEMC_OR_4MB |
115                                M360_MEMC_OR_DRAM;
116        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
117        for (i = 0; i < 50000; i++)
118                continue;
119        for (i = 0; i < 8; ++i)
120                *((volatile unsigned long *)(unsigned long)&_RamBase);
121        for (i = 0 ; i < 4*1024*1024 ; i += sizeof (unsigned long)) {
122                volatile unsigned long *lp;
123                lp = (unsigned long *)((unsigned char *)&_RamBase + i);
124                *lp = *lp;
125        }
126        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_PAREN |
127                                                                M360_MEMC_BR_V;
128
129        /*
130         * Step 13: Copy  the exception vector table to system RAM
131         */
132        asm volatile ("movec vbr,%0" : "=r" (vbr) : );
133        for (i = 0; i < 256; ++i)
134                M68Kvec[i] = vbr[i];
135        asm volatile ("movec %0,vbr" : : "r" (M68Kvec));
136       
137        /*
138         * Step 14: More system initialization
139         * SDCR (Serial DMA configuratin register)
140         *      Give SDMA priority over all interrupt handlers
141         *      Set DMA arbiration level to 4
142         * CICR (CPM interrupt configuration register):
143         *      SCC1 requests at SCCa position
144         *      SCC2 requests at SCCb position
145         *      SCC3 requests at SCCc position
146         *      SCC4 requests at SCCd position
147         *      Interrupt request level 4
148         *      Maintain original priority order
149         *      Vector base 128
150         *      SCCs priority grouped at top of table
151         */
152        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
153        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
154                                                (4 << 13) | (0x1F << 8) | (128);
155
156        /*
157         * Step 15: Set module configuration register
158         *      Disable timers during FREEZE
159         *      Enable bus monitor during FREEZE
160         *      BCLRO* arbitration level 3
161         *      No show cycles
162         *      User/supervisor access
163         *      Bus clear interupt service level 7
164         *      SIM60 interrupt sources higher priority than CPM
165         */
166        m360.mcr = 0x4C7F;
167
168        /*
169         * Clear BSS, switch stacks and call main()
170         */
171        _ClearBSSAndStart ();
172}
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