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source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ f52111f

4.104.114.84.95

Last change on this file since f52111f was df49c60, checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 15:00:15
Merged from 4.5.0-beta3a
Property mode set to `100644`
File size: 18.8 KB

Line
1	/*
2	* MC68360 support routines
3	*
4	* W. Eric Norum
5	* Saskatchewan Accelerator Laboratory
6	* University of Saskatchewan
7	* Saskatoon, Saskatchewan, CANADA
8	* eric@skatter.usask.ca
9	*
10	* $Id$
11	*/
12
13	#include <rtems.h>
14	#include <bsp.h>
15	#include <m68360.h>
16
17	/*
18	* Declare the m360 structure here for the benefit of the debugger
19	*/
20
21	m360_t m360;
22
23	/*
24	* Send a command to the CPM RISC processer
25	*/
26
27	void M360ExecuteRISC(rtems_unsigned16 command)
28	{
29	rtems_unsigned16 sr;
30
31	m68k_disable_interrupts (sr);
32	while (m360.cr & M360_CR_FLG)
33	continue;
34	m360.cr = command \| M360_CR_FLG;
35	m68k_enable_interrupts (sr);
36	}
37
38	/*
39	* Initialize MC68360
40	*/
41	void _Init68360 (void)
42	{
43	int i;
44	m68k_isr_entry *vbr;
45	unsigned long ramSize;
46	extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
47
48	#if (defined (__mc68040__))
49	/*
50	*******************************************
51	* Motorola 68040 and companion-mode 68360 *
52	*******************************************
53	*/
54
55	/*
56	* Step 6: Is this a power-up reset?
57	* For now we just ignore this and do all the steps
58	* Someday we might want to:
59	* if (Hard, Loss of Clock, Power-up)
60	* Do all steps
61	* else if (Double bus fault, watchdog or soft reset)
62	* Skip to step 12
63	* else (must be a reset command)
64	* Skip to step 14
65	*/
66
67	/*
68	* Step 7: Deal with clock synthesizer
69	* HARDWARE:
70	* Change if you're not using an external 25 MHz oscillator.
71	*/
72	m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */
73	m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
74	no LPSTOP slowdown, PLL X1 */
75	m360.cdvcr = 0x8000; /* No more writes, no clock division */
76
77	/*
78	* Step 8: Initialize system protection
79	* Enable watchdog
80	* Watchdog causes system reset
81	* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
82	* Enable double bus fault monitor
83	* Enable bus monitor for external cycles
84	* 1024 clocks for external timeout
85	*/
86	m360.sypcr = 0xEC;
87
88	/*
89	* Step 9: Clear parameter RAM and reset communication processor module
90	*/
91	for (i = 0 ; i < 192 ; i += sizeof (long)) {
92	((long )((char *)&m360 + 0xC00 + i)) = 0;
93	((long )((char *)&m360 + 0xD00 + i)) = 0;
94	((long )((char *)&m360 + 0xE00 + i)) = 0;
95	((long )((char *)&m360 + 0xF00 + i)) = 0;
96	}
97	M360ExecuteRISC (M360_CR_RST);
98
99	/*
100	* Step 10: Write PEPAR
101	* SINTOUT standard M68000 family interrupt level encoding
102	* CF1MODE=10 (BCLRO* output)
103	* No RAS1* double drive
104	* A31 - A28
105	* AMUX output
106	* CAS2* - CAS3*
107	* CAS0* - CAS1*
108	* CS7*
109	* AVEC*
110	*/
111	m360.pepar = 0x3440;
112
113	/*
114	* Step 11: Remap Chip Select 0 (CS0*), set up GMR
115	*/
116	/*
117	* 512 addresses per DRAM page (256K DRAM chips)
118	* 70 nsec DRAM
119	* 180 nsec ROM (3 wait states)
120	*/
121	m360.gmr = M360_GMR_RCNT(23) \| M360_GMR_RFEN \|
122	M360_GMR_RCYC(0) \| M360_GMR_PGS(1) \|
123	M360_GMR_DPS_32BIT \| M360_GMR_NCS \|
124	M360_GMR_TSS40;
125	m360.memc[0].br = (unsigned long)&_RomBase \| M360_MEMC_BR_WP \|
126	M360_MEMC_BR_V;
127	m360.memc[0].or = M360_MEMC_OR_WAITS(3) \| M360_MEMC_OR_1MB \|
128	M360_MEMC_OR_32BIT;
129
130	/*
131	* Step 12: Initialize the system RAM
132	*/
133	/*
134	* Set up option/base registers
135	* 1M DRAM
136	* 70 nsec DRAM
137	* Enable burst mode
138	* No parity checking
139	* Wait for chips to power up
140	* Perform 8 read cycles
141	*/
142	ramSize = 1 * 1024 * 1024;
143	m360.memc[1].or = M360_MEMC_OR_TCYC(0) \|
144	M360_MEMC_OR_1MB \|
145	M360_MEMC_OR_DRAM;
146	m360.memc[1].br = (unsigned long)&_RamBase \|
147	M360_MEMC_BR_BACK40 \|
148	M360_MEMC_BR_V;
149	for (i = 0; i < 50000; i++)
150	continue;
151	for (i = 0; i < 8; ++i)
152	((volatile unsigned long )(unsigned long)&_RamBase);
153
154	/*
155	* Step 13: Copy the exception vector table to system RAM
156	*/
157	m68k_get_vbr (vbr);
158	for (i = 0; i < 256; ++i)
159	M68Kvec[i] = vbr[i];
160	m68k_set_vbr (M68Kvec);
161
162	/*
163	* Step 14: More system initialization
164	* SDCR (Serial DMA configuration register)
165	* Enable SDMA during FREEZE
166	* Give SDMA priority over all interrupt handlers
167	* Set DMA arbiration level to 4
168	* CICR (CPM interrupt configuration register):
169	* SCC1 requests at SCCa position
170	* SCC2 requests at SCCb position
171	* SCC3 requests at SCCc position
172	* SCC4 requests at SCCd position
173	* Interrupt request level 4
174	* Maintain original priority order
175	* Vector base 128
176	* SCCs priority grouped at top of table
177	*/
178	m360.sdcr = M360_SDMA_SISM_7 \| M360_SDMA_SAID_4;
179	m360.cicr = (3 << 22) \| (2 << 20) \| (1 << 18) \| (0 << 16) \|
180	(4 << 13) \| (0x1F << 8) \| (128);
181
182	/*
183	* Step 15: Set module configuration register
184	* Bus request MC68040 Arbitration ID 3
185	* Bus asynchronous timing mode (work around bug in Rev. B)
186	* Arbitration asynchronous timing mode
187	* Disable timers during FREEZE
188	* Disable bus monitor during FREEZE
189	* BCLRO* arbitration level 3
190	* No show cycles
191	* User/supervisor access
192	* Bus clear in arbitration ID level 3
193	* SIM60 interrupt sources higher priority than CPM
194	*/
195	m360.mcr = 0x6000EC3F;
196
197	#elif (defined (M68360_ATLAS_HSB))
198	/*
199	******************************************
200	* Standalone Motorola 68360 -- ATLAS HSB *
201	******************************************
202	*/
203
204	/*
205	* Step 6: Is this a power-up reset?
206	* For now we just ignore this and do all the steps
207	* Someday we might want to:
208	* if (Hard, Loss of Clock, Power-up)
209	* Do all steps
210	* else if (Double bus fault, watchdog or soft reset)
211	* Skip to step 12
212	* else (must be a CPU32+ reset command)
213	* Skip to step 14
214	*/
215
216	/*
217	* Step 7: Deal with clock synthesizer
218	* HARDWARE:
219	* Change if you're not using an external 25 MHz oscillator.
220	*/
221	m360.clkocr = 0x8F; /* No more writes, no clock outputs */
222	m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
223	no LPSTOP slowdown, PLL X1 */
224	m360.cdvcr = 0x8000; /* No more writes, no clock division */
225
226	/*
227	* Step 8: Initialize system protection
228	* Enable watchdog
229	* Watchdog causes system reset
230	* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
231	* Enable double bus fault monitor
232	* Enable bus monitor for external cycles
233	* 1024 clocks for external timeout
234	*/
235	m360.sypcr = 0xEC;
236
237	/*
238	* Step 9: Clear parameter RAM and reset communication processor module
239	*/
240	for (i = 0 ; i < 192 ; i += sizeof (long)) {
241	((long )((char *)&m360 + 0xC00 + i)) = 0;
242	((long )((char *)&m360 + 0xD00 + i)) = 0;
243	((long )((char *)&m360 + 0xE00 + i)) = 0;
244	((long )((char *)&m360 + 0xF00 + i)) = 0;
245	}
246	M360ExecuteRISC (M360_CR_RST);
247
248	/*
249	* Step 10: Write PEPAR
250	* SINTOUT not used (CPU32+ mode)
251	* CF1MODE=00 (CONFIG1 input)
252	* RAS1* double drive
253	* WE0* - WE3*
254	* OE* output
255	* CAS2* - CAS3*
256	* CAS0* - CAS1*
257	* CS7*
258	* AVEC*
259	* HARDWARE:
260	* Change if you are using a different memory configuration
261	* (static RAM, external address multiplexing, etc).
262	*/
263	m360.pepar = 0x0180;
264
265	/*
266	* Step 11: Remap Chip Select 0 (CS0*), set up GMR
267	*/
268	m360.gmr = M360_GMR_RCNT(12) \| M360_GMR_RFEN \|
269	M360_GMR_RCYC(0) \| M360_GMR_PGS(1) \|
270	M360_GMR_DPS_32BIT \| M360_GMR_DWQ \|
271	M360_GMR_GAMX;
272	m360.memc[0].br = (unsigned long)&_RomBase \| M360_MEMC_BR_WP \|
273	M360_MEMC_BR_V;
274	m360.memc[0].or = M360_MEMC_OR_WAITS(3) \| M360_MEMC_OR_1MB \|
275	M360_MEMC_OR_8BIT;
276
277	/*
278	* Step 12: Initialize the system RAM
279	*/
280	ramSize = 2 * 1024 * 1024;
281	/* first bank 1MByte DRAM */
282	m360.memc[1].or = M360_MEMC_OR_TCYC(2) \| M360_MEMC_OR_1MB \|
283	M360_MEMC_OR_PGME \| M360_MEMC_OR_DRAM;
284	m360.memc[1].br = (unsigned long)&_RamBase \| M360_MEMC_BR_V;
285
286	/* second bank 1MByte DRAM */
287	m360.memc[2].or = M360_MEMC_OR_TCYC(2) \| M360_MEMC_OR_1MB \|
288	M360_MEMC_OR_PGME \| M360_MEMC_OR_DRAM;
289	m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) \|
290	M360_MEMC_BR_V;
291
292	/* flash rom socket U6 on CS5 */
293	m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 \| M360_MEMC_BR_WP \|
294	M360_MEMC_BR_V;
295	m360.memc[5].or = M360_MEMC_OR_WAITS(2) \| M360_MEMC_OR_512KB \|
296	M360_MEMC_OR_8BIT;
297
298	/* CSRs on CS7 */
299	m360.memc[7].or = M360_MEMC_OR_TCYC(4) \| M360_MEMC_OR_64KB \|
300	M360_MEMC_OR_8BIT;
301	m360.memc[7].br = ATLASHSB_ESR \| 0x01;
302	for (i = 0; i < 50000; i++)
303	continue;
304	for (i = 0; i < 8; ++i)
305	((volatile unsigned long )(unsigned long)&_RamBase);
306
307	/*
308	* Step 13: Copy the exception vector table to system RAM
309	*/
310	m68k_get_vbr (vbr);
311	for (i = 0; i < 256; ++i)
312	M68Kvec[i] = vbr[i];
313	m68k_set_vbr (M68Kvec);
314
315	/*
316	* Step 14: More system initialization
317	* SDCR (Serial DMA configuration register)
318	* Enable SDMA during FREEZE
319	* Give SDMA priority over all interrupt handlers
320	* Set DMA arbiration level to 4
321	* CICR (CPM interrupt configuration register):
322	* SCC1 requests at SCCa position
323	* SCC2 requests at SCCb position
324	* SCC3 requests at SCCc position
325	* SCC4 requests at SCCd position
326	* Interrupt request level 4
327	* Maintain original priority order
328	* Vector base 128
329	* SCCs priority grouped at top of table
330	*/
331	m360.sdcr = M360_SDMA_SISM_7 \| M360_SDMA_SAID_4;
332	m360.cicr = (3 << 22) \| (2 << 20) \| (1 << 18) \| (0 << 16) \|
333	(4 << 13) \| (0x1F << 8) \| (128);
334
335	/*
336	* Step 15: Set module configuration register
337	* Disable timers during FREEZE
338	* Enable bus monitor during FREEZE
339	* BCLRO* arbitration level 3
340	*/
341
342	#elif (defined (GEN68360_WITH_SRAM))
343	/*
344	***************************************************
345	* Generic Standalone Motorola 68360 *
346	* As described in MC68360 User's Manual *
347	* But uses SRAM instead of DRAM *
348	* CS0* - 512kx8 flash memory *
349	* CS1* - 512kx32 static RAM *
350	* CS2* - 512kx32 static RAM *
351	***************************************************
352	*/
353
354	/*
355	* Step 7: Deal with clock synthesizer
356	* HARDWARE:
357	* Change if you're not using an external oscillator which
358	* oscillates at the system clock rate.
359	*/
360	m360.clkocr = 0x8F; /* No more writes, no clock outputs */
361	m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
362	no LPSTOP slowdown, PLL X1 */
363	m360.cdvcr = 0x8000; /* No more writes, no clock division */
364
365	/*
366	* Step 8: Initialize system protection
367	* Enable watchdog
368	* Watchdog causes system reset
369	* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
370	* Enable double bus fault monitor
371	* Enable bus monitor for external cycles
372	* 1024 clocks for external timeout
373	*/
374	m360.sypcr = 0xEC;
375
376	/*
377	* Step 9: Clear parameter RAM and reset communication processor module
378	*/
379	for (i = 0 ; i < 192 ; i += sizeof (long)) {
380	((long )((char *)&m360 + 0xC00 + i)) = 0;
381	((long )((char *)&m360 + 0xD00 + i)) = 0;
382	((long )((char *)&m360 + 0xE00 + i)) = 0;
383	((long )((char *)&m360 + 0xF00 + i)) = 0;
384	}
385	M360ExecuteRISC (M360_CR_RST);
386
387	/*
388	* Step 10: Write PEPAR
389	* SINTOUT not used (CPU32+ mode)
390	* CF1MODE=00 (CONFIG1 input)
391	* IPIPE1*
392	* WE0* - WE3*
393	* OE* output
394	* CAS2* - CAS3*
395	* CAS0* - CAS1*
396	* CS7*
397	* AVEC*
398	* HARDWARE:
399	* Change if you are using a different memory configuration
400	* (static RAM, external address multiplexing, etc).
401	*/
402	m360.pepar = 0x0080;
403
404	/*
405	* Step 11: Set up GMR
406	*
407	*/
408	m360.gmr = 0x0;
409
410	/*
411	* Step 11a: Remap 512Kx8 flash memory on CS0*
412	* 2 wait states
413	* Make it read-only for now
414	*/
415	m360.memc[0].br = (unsigned long)&_RomBase \| M360_MEMC_BR_WP \|
416	M360_MEMC_BR_V;
417	m360.memc[0].or = M360_MEMC_OR_WAITS(2) \| M360_MEMC_OR_512KB \|
418	M360_MEMC_OR_8BIT;
419	/*
420	* Step 12: Set up main memory
421	* 512Kx32 SRAM on CS1*
422	* 512Kx32 SRAM on CS2*
423	* 0 wait states
424	*/
425	ramSize = 4 * 1024 * 1024;
426	m360.memc[1].br = (unsigned long)&_RamBase \| M360_MEMC_BR_V;
427	m360.memc[1].or = M360_MEMC_OR_WAITS(0) \| M360_MEMC_OR_2MB \|
428	M360_MEMC_OR_32BIT;
429	m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) \| M360_MEMC_BR_V;
430	m360.memc[2].or = M360_MEMC_OR_WAITS(0) \| M360_MEMC_OR_2MB \|
431	M360_MEMC_OR_32BIT;
432	/*
433	* Step 13: Copy the exception vector table to system RAM
434	*/
435	m68k_get_vbr (vbr);
436	for (i = 0; i < 256; ++i)
437	M68Kvec[i] = vbr[i];
438	m68k_set_vbr (M68Kvec);
439
440	/*
441	* Step 14: More system initialization
442	* SDCR (Serial DMA configuration register)
443	* Enable SDMA during FREEZE
444	* Give SDMA priority over all interrupt handlers
445	* Set DMA arbiration level to 4
446	* CICR (CPM interrupt configuration register):
447	* SCC1 requests at SCCa position
448	* SCC2 requests at SCCb position
449	* SCC3 requests at SCCc position
450	* SCC4 requests at SCCd position
451	* Interrupt request level 4
452	* Maintain original priority order
453	* Vector base 128
454	* SCCs priority grouped at top of table
455	*/
456	m360.sdcr = M360_SDMA_SISM_7 \| M360_SDMA_SAID_4;
457	m360.cicr = (3 << 22) \| (2 << 20) \| (1 << 18) \| (0 << 16) \|
458	(4 << 13) \| (0x1F << 8) \| (128);
459
460	/*
461	* Step 15: Set module configuration register
462	* Disable timers during FREEZE
463	* Enable bus monitor during FREEZE
464	* BCLRO* arbitration level 3
465	* No show cycles
466	* User/supervisor access
467	* Bus clear interrupt service level 7
468	* SIM60 interrupt sources higher priority than CPM
469	*/
470	m360.mcr = 0x4C7F;
471
472	#else
473	/*
474	***************************************************
475	* Generic Standalone Motorola 68360 *
476	* As described in MC68360 User's Manual *
477	* Atlas ACE360 *
478	***************************************************
479	*/
480
481	/*
482	* Step 6: Is this a power-up reset?
483	* For now we just ignore this and do all the steps
484	* Someday we might want to:
485	* if (Hard, Loss of Clock, Power-up)
486	* Do all steps
487	* else if (Double bus fault, watchdog or soft reset)
488	* Skip to step 12
489	* else (must be a CPU32+ reset command)
490	* Skip to step 14
491	*/
492
493	/*
494	* Step 7: Deal with clock synthesizer
495	* HARDWARE:
496	* Change if you're not using an external 25 MHz oscillator.
497	*/
498	m360.clkocr = 0x8F; /* No more writes, no clock outputs */
499	m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
500	no LPSTOP slowdown, PLL X1 */
501	m360.cdvcr = 0x8000; /* No more writes, no clock division */
502
503	/*
504	* Step 8: Initialize system protection
505	* Enable watchdog
506	* Watchdog causes system reset
507	* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
508	* Enable double bus fault monitor
509	* Enable bus monitor for external cycles
510	* 1024 clocks for external timeout
511	*/
512	m360.sypcr = 0xEC;
513
514	/*
515	* Step 9: Clear parameter RAM and reset communication processor module
516	*/
517	for (i = 0 ; i < 192 ; i += sizeof (long)) {
518	((long )((char *)&m360 + 0xC00 + i)) = 0;
519	((long )((char *)&m360 + 0xD00 + i)) = 0;
520	((long )((char *)&m360 + 0xE00 + i)) = 0;
521	((long )((char *)&m360 + 0xF00 + i)) = 0;
522	}
523	M360ExecuteRISC (M360_CR_RST);
524
525	/*
526	* Step 10: Write PEPAR
527	* SINTOUT not used (CPU32+ mode)
528	* CF1MODE=00 (CONFIG1 input)
529	* RAS1* double drive
530	* WE0* - WE3*
531	* OE* output
532	* CAS2* - CAS3*
533	* CAS0* - CAS1*
534	* CS7*
535	* AVEC*
536	* HARDWARE:
537	* Change if you are using a different memory configuration
538	* (static RAM, external address multiplexing, etc).
539	*/
540	m360.pepar = 0x0180;
541
542	/*
543	* Step 11: Remap Chip Select 0 (CS0*), set up GMR
544	* 32-bit DRAM
545	* Internal DRAM address multiplexing
546	* 60 nsec DRAM
547	* 180 nsec ROM (3 wait states)
548	* 15.36 usec DRAM refresh interval
549	* The DRAM page size selection is not modified since this
550	* startup code may be running in a bootstrap PROM or in
551	* a program downloaded by the bootstrap PROM.
552	*/
553	m360.gmr = (m360.gmr & 0x001C0000) \| M360_GMR_RCNT(23) \|
554	M360_GMR_RFEN \| M360_GMR_RCYC(0) \|
555	M360_GMR_DPS_32BIT \| M360_GMR_NCS \|
556	M360_GMR_GAMX;
557	m360.memc[0].br = (unsigned long)&_RomBase \| M360_MEMC_BR_WP \|
558	M360_MEMC_BR_V;
559	m360.memc[0].or = M360_MEMC_OR_WAITS(3) \| M360_MEMC_OR_1MB \|
560	M360_MEMC_OR_8BIT;
561
562	/*
563	* Step 12: Initialize the system RAM
564	* Do this only if the DRAM has not already been set up
565	*/
566	if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
567	/*
568	* Set up GMR DRAM page size, option and base registers
569	* Assume 16Mbytes of DRAM
570	* 60 nsec DRAM
571	*/
572	m360.gmr = (m360.gmr & ~0x001C0000) \| M360_GMR_PGS(5);
573	m360.memc[1].or = M360_MEMC_OR_TCYC(0) \|
574	M360_MEMC_OR_16MB \|
575	M360_MEMC_OR_DRAM;
576	m360.memc[1].br = (unsigned long)&_RamBase \| M360_MEMC_BR_V;
577
578	/*
579	* Wait for chips to power up
580	* Perform 8 read cycles
581	*/
582	for (i = 0; i < 50000; i++)
583	continue;
584	for (i = 0; i < 8; ++i)
585	((volatile unsigned long )(unsigned long)&_RamBase);
586
587	/*
588	* Determine memory size (1, 4, or 16 Mbytes)
589	* Set GMR DRAM page size appropriately.
590	* The OR is left at 16 Mbytes. The bootstrap PROM places its
591	* .data and .bss segments at the top of the 16 Mbyte space.
592	* A 1 Mbyte or 4 Mbyte DRAM will show up several times in
593	* the memory map, but will work with the same bootstrap PROM.
594	*/
595	(volatile char )&_RamBase = 0;
596	((volatile char )&_RamBase+0x00C01800) = 1;
597	if ((volatile char )&_RamBase) {
598	m360.gmr = (m360.gmr & ~0x001C0000) \| M360_GMR_PGS(1);
599	}
600	else {
601	((volatile char )&_RamBase+0x00801000) = 1;
602	if ((volatile char )&_RamBase) {
603	m360.gmr = (m360.gmr & ~0x001C0000) \| M360_GMR_PGS(3);
604	}
605	}
606
607	/*
608	* Enable parity checking
609	*/
610	m360.memc[1].br \|= M360_MEMC_BR_PAREN;
611	}
612	switch (m360.gmr & 0x001C0000) {
613	default: ramSize = 4 * 1024 * 1024; break;
614	case M360_GMR_PGS(1): ramSize = 1 * 1024 * 1024; break;
615	case M360_GMR_PGS(3): ramSize = 4 * 1024 * 1024; break;
616	case M360_GMR_PGS(5): ramSize = 16 * 1024 * 1024; break;
617	}
618
619	/*
620	* Step 13: Copy the exception vector table to system RAM
621	*/
622	m68k_get_vbr (vbr);
623	for (i = 0; i < 256; ++i)
624	M68Kvec[i] = vbr[i];
625	m68k_set_vbr (M68Kvec);
626
627	/*
628	* Step 14: More system initialization
629	* SDCR (Serial DMA configuration register)
630	* Enable SDMA during FREEZE
631	* Give SDMA priority over all interrupt handlers
632	* Set DMA arbiration level to 4
633	* CICR (CPM interrupt configuration register):
634	* SCC1 requests at SCCa position
635	* SCC2 requests at SCCb position
636	* SCC3 requests at SCCc position
637	* SCC4 requests at SCCd position
638	* Interrupt request level 4
639	* Maintain original priority order
640	* Vector base 128
641	* SCCs priority grouped at top of table
642	*/
643	m360.sdcr = M360_SDMA_SISM_7 \| M360_SDMA_SAID_4;
644	m360.cicr = (3 << 22) \| (2 << 20) \| (1 << 18) \| (0 << 16) \|
645	(4 << 13) \| (0x1F << 8) \| (128);
646
647	/*
648	* Step 15: Set module configuration register
649	* Disable timers during FREEZE
650	* Enable bus monitor during FREEZE
651	* BCLRO* arbitration level 3
652	* No show cycles
653	* User/supervisor access
654	* Bus clear interrupt service level 7
655	* SIM60 interrupt sources higher priority than CPM
656	*/
657	m360.mcr = 0x4C7F;
658	#endif
659
660	/*
661	* Copy data, clear BSS, switch stacks and call main()
662	* Must pass ramSize as argument since the data/bss segment
663	* may be overwritten.
664	*/
665	_CopyDataClearBSSAndStart (ramSize);
666	}

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