1 | /* |
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2 | * MC68360 support routines |
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3 | * |
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4 | * W. Eric Norum |
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5 | * Saskatchewan Accelerator Laboratory |
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6 | * University of Saskatchewan |
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7 | * Saskatoon, Saskatchewan, CANADA |
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8 | * eric@skatter.usask.ca |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | #include <rtems.h> |
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14 | #include <bsp.h> |
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15 | #include <m68360.h> |
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16 | |
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17 | /* |
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18 | * Send a command to the CPM RISC processer |
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19 | */ |
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20 | |
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21 | void M360ExecuteRISC(rtems_unsigned16 command) |
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22 | { |
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23 | rtems_unsigned16 sr; |
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24 | |
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25 | m68k_disable_interrupts (sr); |
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26 | while (m360.cr & M360_CR_FLG) |
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27 | continue; |
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28 | m360.cr = command | M360_CR_FLG; |
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29 | m68k_enable_interrupts (sr); |
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30 | } |
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31 | |
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32 | /* |
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33 | * Initialize MC68360 |
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34 | */ |
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35 | |
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36 | void _Init68360 (void) |
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37 | { |
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38 | int i; |
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39 | extern void *_RomBase, *_RamBase; |
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40 | m68k_isr_entry *vbr; |
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41 | extern void _CopyDataClearBSSAndStart (void); |
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42 | |
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43 | /* |
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44 | * Step 6: Is this a power-up reset? |
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45 | * For now we just ignore this and do *all* the steps |
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46 | * Someday we might want to: |
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47 | * if (Hard, Loss of Clock, Power-up) |
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48 | * Do all steps |
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49 | * else if (Double bus fault, watchdog or soft reset) |
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50 | * Skip to step 12 |
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51 | * else (must be a CPU32+ reset command) |
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52 | * Skip to step 14 |
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53 | */ |
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54 | |
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55 | /* |
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56 | * Step 7: Deal with clock synthesizer |
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57 | * HARDWARE: |
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58 | * Change if you're not using an external 25 MHz oscillator. |
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59 | */ |
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60 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
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61 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, */ |
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62 | /* no LPSTOP slowdown, PLL X1 */ |
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63 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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64 | |
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65 | /* |
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66 | * Step 8: Initialize system protection |
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67 | * Disable watchdog FIXME: Should use watchdog!!!! |
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68 | * Watchdog causes system reset |
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69 | * Fastest watchdog timeout |
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70 | * Enable double bus fault monitor |
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71 | * Enable bus monitor external |
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72 | * 128 clocks for external timeout |
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73 | */ |
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74 | m360.sypcr = 0x4F; |
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75 | |
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76 | /* |
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77 | * Step 9: Clear parameter RAM and reset communication processor module |
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78 | */ |
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79 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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80 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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81 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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82 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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83 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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84 | } |
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85 | M360ExecuteRISC (M360_CR_RST); |
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86 | |
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87 | /* |
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88 | * Step 10: Write PEPAR |
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89 | * SINTOUT not used (CPU32+ mode) |
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90 | * CF1MODE=00 (CONFIG1 input) |
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91 | * RAS1* double drive |
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92 | * A31-A28 |
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93 | * OE* output |
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94 | * CAS2* / CAS3* |
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95 | * CAS0* / CAS1* |
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96 | * CS7* |
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97 | * AVEC* |
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98 | * HARDWARE: |
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99 | * Change if you are using a different memory configuration |
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100 | * (static RAM, external address multiplexing, etc). |
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101 | */ |
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102 | m360.pepar = 0x0100; |
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103 | |
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104 | /* |
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105 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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106 | * 1024 addresses per DRAM page (1M DRAM chips) |
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107 | * 60 nsec DRAM |
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108 | * 180 nsec ROM (3 wait states) |
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109 | * HARDWARE: |
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110 | * Change if you are using a different memory configuration |
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111 | */ |
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112 | m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | M360_GMR_RCYC(0) | |
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113 | M360_GMR_PGS(3) | M360_GMR_DPS_32BIT | M360_GMR_NCS | |
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114 | M360_GMR_GAMX; |
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115 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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116 | M360_MEMC_BR_V; |
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117 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB | |
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118 | M360_MEMC_OR_8BIT; |
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119 | |
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120 | /* |
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121 | * Step 12: Initialize the system RAM |
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122 | * Set up option/base registers |
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123 | * 4 MB DRAM |
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124 | * 60 nsec DRAM |
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125 | * Wait for chips to power up |
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126 | * Perform 8 read cycles |
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127 | * Set all parity bits to correct state |
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128 | * Enable parity checking |
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129 | * HARDWARE: |
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130 | * Change if you are using a different memory configuration |
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131 | */ |
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132 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) | M360_MEMC_OR_4MB | |
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133 | M360_MEMC_OR_DRAM; |
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134 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; |
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135 | for (i = 0; i < 50000; i++) |
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136 | continue; |
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137 | for (i = 0; i < 8; ++i) |
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138 | *((volatile unsigned long *)(unsigned long)&_RamBase); |
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139 | for (i = 0 ; i < 4*1024*1024 ; i += sizeof (unsigned long)) { |
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140 | volatile unsigned long *lp; |
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141 | lp = (unsigned long *)((unsigned char *)&_RamBase + i); |
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142 | *lp = *lp; |
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143 | } |
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144 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_PAREN | |
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145 | M360_MEMC_BR_V; |
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146 | |
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147 | /* |
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148 | * Step 13: Copy the exception vector table to system RAM |
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149 | */ |
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150 | m68k_get_vbr (vbr); |
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151 | for (i = 0; i < 256; ++i) |
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152 | M68Kvec[i] = vbr[i]; |
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153 | m68k_set_vbr (M68Kvec); |
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154 | |
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155 | /* |
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156 | * Step 14: More system initialization |
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157 | * SDCR (Serial DMA configuratin register) |
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158 | * Give SDMA priority over all interrupt handlers |
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159 | * Set DMA arbiration level to 4 |
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160 | * CICR (CPM interrupt configuration register): |
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161 | * SCC1 requests at SCCa position |
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162 | * SCC2 requests at SCCb position |
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163 | * SCC3 requests at SCCc position |
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164 | * SCC4 requests at SCCd position |
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165 | * Interrupt request level 4 |
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166 | * Maintain original priority order |
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167 | * Vector base 128 |
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168 | * SCCs priority grouped at top of table |
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169 | */ |
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170 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
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171 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
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172 | (4 << 13) | (0x1F << 8) | (128); |
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173 | |
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174 | /* |
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175 | * Step 15: Set module configuration register |
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176 | * Disable timers during FREEZE |
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177 | * Enable bus monitor during FREEZE |
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178 | * BCLRO* arbitration level 3 |
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179 | * No show cycles |
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180 | * User/supervisor access |
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181 | * Bus clear interupt service level 7 |
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182 | * SIM60 interrupt sources higher priority than CPM |
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183 | */ |
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184 | m360.mcr = 0x4C7F; |
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185 | |
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186 | /* |
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187 | * Copy data, clear BSS, switch stacks and call main() |
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188 | */ |
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189 | _CopyDataClearBSSAndStart (); |
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190 | } |
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