source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ d9fe8e2

4.104.114.84.95
Last change on this file since d9fe8e2 was 6b4ca31, checked in by Joel Sherrill <joel.sherrill@…>, on 09/18/97 at 16:01:52

Merged changes from Eric Norum:

Enable 68360 watchdog. The watchdog control register is a
`write-once' register, so the watchdog has to be enabled in the boot
roms if it is to be used at all. To make the change transparent I
added a default feed of the watchdog to the clock interrupt handler.
This can be overridden if the application wants to handle the
watchdog. The only difficulty with this change is that an
application has to either include the clock driver or handle the
watchdog explicitely. I don't think this is much of a problem since
I am pretty sure that almost every application includes the clock
driver.
  • Property mode set to 100644
File size: 14.2 KB
Line 
1/*
2 * MC68360 support routines
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
15#include <m68360.h>
16
17/*
18 * Send a command to the CPM RISC processer
19 */
20
21void M360ExecuteRISC(rtems_unsigned16 command)
22{
23        rtems_unsigned16 sr;
24
25        m68k_disable_interrupts (sr);
26        while (m360.cr & M360_CR_FLG)
27                continue;
28        m360.cr = command | M360_CR_FLG;
29        m68k_enable_interrupts (sr);
30}
31
32/*
33 * Initialize MC68360
34 */
35void _Init68360 (void)
36{
37        int i;
38        m68k_isr_entry *vbr;
39        extern void _CopyDataClearBSSAndStart (void);
40
41#if (defined (m68040) || defined (m68lc040) || defined (m68ec040))
42        /*
43         *******************************************
44         * Motorola 68040 and companion-mode 68360 *
45         *******************************************
46         */
47
48        /*
49         * Step 6: Is this a power-up reset?
50         * For now we just ignore this and do *all* the steps
51         * Someday we might want to:
52         *      if (Hard, Loss of Clock, Power-up)
53         *              Do all steps
54         *      else if (Double bus fault, watchdog or soft reset)
55         *              Skip to step 12
56         *      else (must be a reset command)
57         *              Skip to step 14
58         */
59
60        /*
61         * Step 7: Deal with clock synthesizer
62         * HARDWARE:
63         *      Change if you're not using an external 25 MHz oscillator.
64         */
65        m360.clkocr = 0x83;     /* No more writes, full-power CLKO2 */
66        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
67                                   no LPSTOP slowdown, PLL X1 */
68        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
69
70        /*
71         * Step 8: Initialize system protection
72         *      Enable watchdog
73         *      Watchdog causes system reset
74         *      Next-to-slowest watchdog timeout
75         *          (21 seconds with 25 MHz oscillator)
76         *      Enable double bus fault monitor
77         *      Enable bus monitor for external cycles
78         *      1024 clocks for external timeout
79         */
80         m360.sypcr = 0xEC;
81
82        /*
83         * Step 9: Clear parameter RAM and reset communication processor module
84         */
85        for (i = 0 ; i < 192  ; i += sizeof (long)) {
86                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
87                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
88                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
89                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
90        }
91        M360ExecuteRISC (M360_CR_RST);
92
93        /*
94         * Step 10: Write PEPAR
95         *      SINTOUT standard M68000 family interrupt level encoding
96         *      CF1MODE=10 (BCLRO* output)
97         *      No RAS1* double drive
98         *      A31 - A28
99         *      AMUX output
100         *      CAS2* - CAS3*
101         *      CAS0* - CAS1*
102         *      CS7*
103         *      AVEC*
104         */
105        m360.pepar = 0x3440;
106
107        /*
108         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
109         */
110        /*
111         * 512 addresses per DRAM page (256K DRAM chips)
112         * 70 nsec DRAM
113         * 180 nsec ROM (3 wait states)
114         */
115        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
116                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
117                                M360_GMR_DPS_32BIT | M360_GMR_NCS |
118                                M360_GMR_TSS40;
119        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
120                                                        M360_MEMC_BR_V;
121        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
122                                                M360_MEMC_OR_32BIT;
123
124        /*
125         * Step 12: Initialize the system RAM
126         */
127        /*
128         *      Set up option/base registers
129         *              1M DRAM
130         *              70 nsec DRAM
131         *      Enable burst mode
132         *      No parity checking
133         *      Wait for chips to power up
134         *      Perform 8 read cycles
135         */
136        m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
137                                        M360_MEMC_OR_1MB |
138                                        M360_MEMC_OR_DRAM;
139        m360.memc[1].br = (unsigned long)&_RamBase |
140                                        M360_MEMC_BR_BACK40 |
141                                        M360_MEMC_BR_V;
142        for (i = 0; i < 50000; i++)
143                continue;
144        for (i = 0; i < 8; ++i)
145                *((volatile unsigned long *)(unsigned long)&_RamBase);
146
147        /*
148         * Step 13: Copy  the exception vector table to system RAM
149         */
150        m68k_get_vbr (vbr);
151        for (i = 0; i < 256; ++i)
152                M68Kvec[i] = vbr[i];
153        m68k_set_vbr (M68Kvec);
154       
155        /*
156         * Step 14: More system initialization
157         * SDCR (Serial DMA configuration register)
158         *      Enable SDMA during FREEZE
159         *      Give SDMA priority over all interrupt handlers
160         *      Set DMA arbiration level to 4
161         * CICR (CPM interrupt configuration register):
162         *      SCC1 requests at SCCa position
163         *      SCC2 requests at SCCb position
164         *      SCC3 requests at SCCc position
165         *      SCC4 requests at SCCd position
166         *      Interrupt request level 4
167         *      Maintain original priority order
168         *      Vector base 128
169         *      SCCs priority grouped at top of table
170         */
171        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
172        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
173                                                (4 << 13) | (0x1F << 8) | (128);
174
175        /*
176         * Step 15: Set module configuration register
177         *      Bus request MC68040 Arbitration ID 3
178         *      Bus asynchronous timing mode (work around bug in Rev. B)
179         *      Arbitration asynchronous timing mode
180         *      Disable timers during FREEZE
181         *      Disable bus monitor during FREEZE
182         *      BCLRO* arbitration level 3
183         *      No show cycles
184         *      User/supervisor access
185         *      Bus clear in arbitration ID level  3
186         *      SIM60 interrupt sources higher priority than CPM
187         */
188        m360.mcr = 0x6000EC3F;
189
190#elif (defined (M68360_ATLAS_HSB))
191        /*
192         ******************************************
193         * Standalone Motorola 68360 -- ATLAS HSB *
194         ******************************************
195         */
196
197        /*
198         * Step 6: Is this a power-up reset?
199         * For now we just ignore this and do *all* the steps
200         * Someday we might want to:
201         *      if (Hard, Loss of Clock, Power-up)
202         *              Do all steps
203         *      else if (Double bus fault, watchdog or soft reset)
204         *              Skip to step 12
205         *      else (must be a CPU32+ reset command)
206         *              Skip to step 14
207         */
208
209        /*
210         * Step 7: Deal with clock synthesizer
211         * HARDWARE:
212         *      Change if you're not using an external 25 MHz oscillator.
213         */
214        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
215        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
216                                   no LPSTOP slowdown, PLL X1 */
217        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
218
219        /*
220         * Step 8: Initialize system protection
221         *      Disable watchdog FIXME: Should use watchdog!!!!
222         *      Watchdog causes system reset
223         *      Slowest watchdog timeout
224         *      Enable double bus fault monitor
225         *      Enable bus monitor external
226         *      128 clocks for external timeout
227         */
228        m360.sypcr = 0x7F;
229
230        /*
231         * Step 9: Clear parameter RAM and reset communication processor module
232         */
233        for (i = 0 ; i < 192  ; i += sizeof (long)) {
234                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
235                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
236                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
237                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
238        }
239        M360ExecuteRISC (M360_CR_RST);
240
241        /*
242         * Step 10: Write PEPAR
243         *      SINTOUT not used (CPU32+ mode)
244         *      CF1MODE=00 (CONFIG1 input)
245         *      RAS1* double drive
246         *      WE0* - WE3*
247         *      OE* output
248         *      CAS2* - CAS3*
249         *      CAS0* - CAS1*
250         *      CS7*
251         *      AVEC*
252         * HARDWARE:
253         *      Change if you are using a different memory configuration
254         *      (static RAM, external address multiplexing, etc).
255         */
256        m360.pepar = 0x0180;
257
258        /*
259         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
260         */
261        m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
262                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
263                                M360_GMR_DPS_32BIT | M360_GMR_DWQ |
264                                M360_GMR_GAMX;
265        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
266                                                                M360_MEMC_BR_V;
267        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
268                                                        M360_MEMC_OR_8BIT;
269
270        /*
271         * Step 12: Initialize the system RAM
272         */
273        /* first bank 1MByte DRAM */
274        m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
275                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
276        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
277
278        /* second bank 1MByte DRAM */
279        m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
280                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
281        m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
282                                        M360_MEMC_BR_V;
283
284        /* flash rom socket U6 on CS5 */
285        m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
286                                                                M360_MEMC_BR_V;
287        m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
288                                                                M360_MEMC_OR_8BIT;
289
290        /* CSRs on CS7 */
291        m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
292                                        M360_MEMC_OR_8BIT;
293        m360.memc[7].br = ATLASHSB_ESR | 0x01;
294        for (i = 0; i < 50000; i++)
295                continue;
296        for (i = 0; i < 8; ++i)
297                *((volatile unsigned long *)(unsigned long)&_RamBase);
298
299        /*
300         * Step 13: Copy  the exception vector table to system RAM
301         */
302        m68k_get_vbr (vbr);
303        for (i = 0; i < 256; ++i)
304                M68Kvec[i] = vbr[i];
305        m68k_set_vbr (M68Kvec);
306       
307        /*
308         * Step 14: More system initialization
309         * SDCR (Serial DMA configuration register)
310         *      Disable SDMA during FREEZE
311         *      Give SDMA priority over all interrupt handlers
312         *      Set DMA arbiration level to 4
313         * CICR (CPM interrupt configuration register):
314         *      SCC1 requests at SCCa position
315         *      SCC2 requests at SCCb position
316         *      SCC3 requests at SCCc position
317         *      SCC4 requests at SCCd position
318         *      Interrupt request level 4
319         *      Maintain original priority order
320         *      Vector base 128
321         *      SCCs priority grouped at top of table
322         */
323        m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
324        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
325                                                (4 << 13) | (0x1F << 8) | (128);
326
327        /*
328         * Step 15: Set module configuration register
329         *      Disable timers during FREEZE
330         *      Enable bus monitor during FREEZE
331         *      BCLRO* arbitration level 3
332         *      No show cycles
333         *      User/supervisor access
334         *      Bus clear interrupt service level 7
335         *      SIM60 interrupt sources higher priority than CPM
336         */
337        m360.mcr = 0x4C7F;
338
339#else
340        /*
341         ***************************************************
342         * Generic Standalone Motorola 68360               *
343         *           As described in MC68360 User's Manual *
344         *           Atlas ACE360                          *
345         ***************************************************
346         */
347
348        /*
349         * Step 6: Is this a power-up reset?
350         * For now we just ignore this and do *all* the steps
351         * Someday we might want to:
352         *      if (Hard, Loss of Clock, Power-up)
353         *              Do all steps
354         *      else if (Double bus fault, watchdog or soft reset)
355         *              Skip to step 12
356         *      else (must be a CPU32+ reset command)
357         *              Skip to step 14
358         */
359
360        /*
361         * Step 7: Deal with clock synthesizer
362         * HARDWARE:
363         *      Change if you're not using an external 25 MHz oscillator.
364         */
365        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
366        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
367                                   no LPSTOP slowdown, PLL X1 */
368        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
369
370        /*
371         * Step 8: Initialize system protection
372         *      Enable watchdog
373         *      Watchdog causes system reset
374         *      Next-to-slowest watchdog timeout
375         *          (21 seconds with 25 MHz oscillator)
376         *      Enable double bus fault monitor
377         *      Enable bus monitor for external cycles
378         *      1024 clocks for external timeout
379         */
380         m360.sypcr = 0xEC;
381
382        /*
383         * Step 9: Clear parameter RAM and reset communication processor module
384         */
385        for (i = 0 ; i < 192  ; i += sizeof (long)) {
386                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
387                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
388                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
389                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
390        }
391        M360ExecuteRISC (M360_CR_RST);
392
393        /*
394         * Step 10: Write PEPAR
395         *      SINTOUT not used (CPU32+ mode)
396         *      CF1MODE=00 (CONFIG1 input)
397         *      RAS1* double drive
398         *      WE0* - WE3*
399         *      OE* output
400         *      CAS2* - CAS3*
401         *      CAS0* - CAS1*
402         *      CS7*
403         *      AVEC*
404         * HARDWARE:
405         *      Change if you are using a different memory configuration
406         *      (static RAM, external address multiplexing, etc).
407         */
408        m360.pepar = 0x0180;
409
410        /*
411         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
412         */
413        /*
414         * 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips)
415         * 60 nsec DRAM
416         * 180 nsec ROM (3 wait states)
417         */
418        switch ((unsigned long)&_RamSize) {
419        default:
420        case 4*1024*1024:
421                m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
422                                        M360_GMR_RCYC(0) | M360_GMR_PGS(3) |
423                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
424                                        M360_GMR_GAMX;
425                break;
426
427        case 16*1024*1024:
428                m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
429                                        M360_GMR_RCYC(0) | M360_GMR_PGS(5) |
430                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
431                                        M360_GMR_GAMX;
432                break;
433
434        case 64*1024*1024:
435                m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
436                                        M360_GMR_RCYC(0) | M360_GMR_PGS(7) |
437                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
438                                        M360_GMR_GAMX;
439                break;
440        }
441        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
442                                                                M360_MEMC_BR_V;
443        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
444                                                        M360_MEMC_OR_8BIT;
445
446        /*
447         * Step 12: Initialize the system RAM
448         */
449        /*
450         *      Set up option/base registers
451         *              4M/16M/64M DRAM
452         *              60 nsec DRAM
453         *      Wait for chips to power up
454         *      Perform 8 read cycles
455         *      Set all parity bits to correct state
456         *      Enable parity checking
457         */
458        switch ((unsigned long)&_RamSize) {
459        default:
460        case 4*1024*1024:
461                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
462                                        M360_MEMC_OR_4MB |
463                                        M360_MEMC_OR_DRAM;
464                break;
465
466        case 16*1024*1024:
467                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
468                                        M360_MEMC_OR_16MB |
469                                        M360_MEMC_OR_DRAM;
470                break;
471
472        case 64*1024*1024:
473                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
474                                        M360_MEMC_OR_64MB |
475                                        M360_MEMC_OR_DRAM;
476                break;
477        }
478        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
479        for (i = 0; i < 50000; i++)
480                continue;
481        for (i = 0; i < 8; ++i)
482                *((volatile unsigned long *)(unsigned long)&_RamBase);
483        for (i = 0 ; i < (unsigned long)&_RamSize ; i += sizeof (unsigned long)) {
484                volatile unsigned long *lp;
485                lp = (unsigned long *)((unsigned char *)&_RamBase + i);
486                *lp = *lp;
487        }
488        m360.memc[1].br = (unsigned long)&_RamBase |
489                                M360_MEMC_BR_PAREN | M360_MEMC_BR_V;
490
491        /*
492         * Step 13: Copy  the exception vector table to system RAM
493         */
494        m68k_get_vbr (vbr);
495        for (i = 0; i < 256; ++i)
496                M68Kvec[i] = vbr[i];
497        m68k_set_vbr (M68Kvec);
498       
499        /*
500         * Step 14: More system initialization
501         * SDCR (Serial DMA configuration register)
502         *      Enable SDMA during FREEZE
503         *      Give SDMA priority over all interrupt handlers
504         *      Set DMA arbiration level to 4
505         * CICR (CPM interrupt configuration register):
506         *      SCC1 requests at SCCa position
507         *      SCC2 requests at SCCb position
508         *      SCC3 requests at SCCc position
509         *      SCC4 requests at SCCd position
510         *      Interrupt request level 4
511         *      Maintain original priority order
512         *      Vector base 128
513         *      SCCs priority grouped at top of table
514         */
515        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
516        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
517                                                (4 << 13) | (0x1F << 8) | (128);
518
519        /*
520         * Step 15: Set module configuration register
521         *      Disable timers during FREEZE
522         *      Enable bus monitor during FREEZE
523         *      BCLRO* arbitration level 3
524         *      No show cycles
525         *      User/supervisor access
526         *      Bus clear interrupt service level 7
527         *      SIM60 interrupt sources higher priority than CPM
528         */
529        m360.mcr = 0x4C7F;
530#endif
531
532        /*
533         * Copy data, clear BSS, switch stacks and call main()
534         */
535        _CopyDataClearBSSAndStart ();
536}
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