1 | /*
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2 | * MC68360 support routines
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3 | *
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4 | * W. Eric Norum
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5 | * Saskatchewan Accelerator Laboratory
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6 | * University of Saskatchewan
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7 | * Saskatoon, Saskatchewan, CANADA
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8 | * eric@skatter.usask.ca
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9 | *
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10 | * $Id$
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11 | */
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12 |
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13 | #include <rtems.h>
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14 | #include <bsp.h>
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15 | #include <m68360.h>
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16 |
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17 | /*
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18 | * Send a command to the CPM RISC processer
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19 | */
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20 |
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21 | void M360ExecuteRISC(rtems_unsigned16 command)
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22 | {
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23 | rtems_unsigned16 sr;
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24 |
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25 | m68k_disable_interrupts (sr);
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26 | while (m360.cr & M360_CR_FLG)
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27 | continue;
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28 | m360.cr = command | M360_CR_FLG;
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29 | m68k_enable_interrupts (sr);
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30 | }
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31 |
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32 | /*
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33 | * Initialize MC68360
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34 | */
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35 | void _Init68360 (void)
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36 | {
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37 | int i;
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38 | m68k_isr_entry *vbr;
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39 | extern void _CopyDataClearBSSAndStart (void);
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40 |
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41 | #if (defined (m68040) || defined (m68lc040) || defined (m68ec040))
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42 | /*
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43 | *******************************************
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44 | * Motorola 68040 and companion-mode 68360 *
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45 | *******************************************
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46 | */
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47 |
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48 | /*
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49 | * Step 6: Is this a power-up reset?
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50 | * For now we just ignore this and do *all* the steps
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51 | * Someday we might want to:
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52 | * if (Hard, Loss of Clock, Power-up)
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53 | * Do all steps
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54 | * else if (Double bus fault, watchdog or soft reset)
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55 | * Skip to step 12
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56 | * else (must be a reset command)
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57 | * Skip to step 14
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58 | */
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59 |
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60 | /*
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61 | * Step 7: Deal with clock synthesizer
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62 | * HARDWARE:
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63 | * Change if you're not using an external 25 MHz oscillator.
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64 | */
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65 | m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */
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66 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
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67 | no LPSTOP slowdown, PLL X1 */
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68 | m360.cdvcr = 0x8000; /* No more writes, no clock division */
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69 |
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70 | /*
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71 | * Step 8: Initialize system protection
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72 | * Enable watchdog
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73 | * Watchdog causes system reset
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74 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
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75 | * Enable double bus fault monitor
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76 | * Enable bus monitor for external cycles
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77 | * 1024 clocks for external timeout
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78 | */
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79 | m360.sypcr = 0xEC;
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80 |
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81 | /*
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82 | * Step 9: Clear parameter RAM and reset communication processor module
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83 | */
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84 | for (i = 0 ; i < 192 ; i += sizeof (long)) {
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85 | *((long *)((char *)&m360 + 0xC00 + i)) = 0;
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86 | *((long *)((char *)&m360 + 0xD00 + i)) = 0;
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87 | *((long *)((char *)&m360 + 0xE00 + i)) = 0;
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88 | *((long *)((char *)&m360 + 0xF00 + i)) = 0;
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89 | }
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90 | M360ExecuteRISC (M360_CR_RST);
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91 |
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92 | /*
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93 | * Step 10: Write PEPAR
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94 | * SINTOUT standard M68000 family interrupt level encoding
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95 | * CF1MODE=10 (BCLRO* output)
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96 | * No RAS1* double drive
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97 | * A31 - A28
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98 | * AMUX output
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99 | * CAS2* - CAS3*
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100 | * CAS0* - CAS1*
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101 | * CS7*
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102 | * AVEC*
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103 | */
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104 | m360.pepar = 0x3440;
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105 |
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106 | /*
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107 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR
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108 | */
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109 | /*
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110 | * 512 addresses per DRAM page (256K DRAM chips)
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111 | * 70 nsec DRAM
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112 | * 180 nsec ROM (3 wait states)
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113 | */
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114 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
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115 | M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
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116 | M360_GMR_DPS_32BIT | M360_GMR_NCS |
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117 | M360_GMR_TSS40;
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118 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
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119 | M360_MEMC_BR_V;
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120 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
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121 | M360_MEMC_OR_32BIT;
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122 |
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123 | /*
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124 | * Step 12: Initialize the system RAM
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125 | */
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126 | /*
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127 | * Set up option/base registers
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128 | * 1M DRAM
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129 | * 70 nsec DRAM
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130 | * Enable burst mode
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131 | * No parity checking
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132 | * Wait for chips to power up
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133 | * Perform 8 read cycles
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134 | */
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135 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
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136 | M360_MEMC_OR_1MB |
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137 | M360_MEMC_OR_DRAM;
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138 | m360.memc[1].br = (unsigned long)&_RamBase |
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139 | M360_MEMC_BR_BACK40 |
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140 | M360_MEMC_BR_V;
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141 | for (i = 0; i < 50000; i++)
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142 | continue;
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143 | for (i = 0; i < 8; ++i)
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144 | *((volatile unsigned long *)(unsigned long)&_RamBase);
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145 |
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146 | /*
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147 | * Step 13: Copy the exception vector table to system RAM
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148 | */
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149 | m68k_get_vbr (vbr);
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150 | for (i = 0; i < 256; ++i)
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151 | M68Kvec[i] = vbr[i];
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152 | m68k_set_vbr (M68Kvec);
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153 |
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154 | /*
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155 | * Step 14: More system initialization
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156 | * SDCR (Serial DMA configuration register)
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157 | * Enable SDMA during FREEZE
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158 | * Give SDMA priority over all interrupt handlers
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159 | * Set DMA arbiration level to 4
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160 | * CICR (CPM interrupt configuration register):
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161 | * SCC1 requests at SCCa position
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162 | * SCC2 requests at SCCb position
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163 | * SCC3 requests at SCCc position
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164 | * SCC4 requests at SCCd position
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165 | * Interrupt request level 4
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166 | * Maintain original priority order
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167 | * Vector base 128
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168 | * SCCs priority grouped at top of table
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169 | */
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170 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
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171 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
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172 | (4 << 13) | (0x1F << 8) | (128);
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173 |
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174 | /*
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175 | * Step 15: Set module configuration register
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176 | * Bus request MC68040 Arbitration ID 3
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177 | * Bus asynchronous timing mode (work around bug in Rev. B)
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178 | * Arbitration asynchronous timing mode
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179 | * Disable timers during FREEZE
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180 | * Disable bus monitor during FREEZE
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181 | * BCLRO* arbitration level 3
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182 | * No show cycles
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183 | * User/supervisor access
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184 | * Bus clear in arbitration ID level 3
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185 | * SIM60 interrupt sources higher priority than CPM
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186 | */
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187 | m360.mcr = 0x6000EC3F;
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188 |
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189 | #elif (defined (M68360_ATLAS_HSB))
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190 | /*
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191 | ******************************************
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192 | * Standalone Motorola 68360 -- ATLAS HSB *
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193 | ******************************************
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194 | */
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195 |
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196 | /*
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197 | * Step 6: Is this a power-up reset?
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198 | * For now we just ignore this and do *all* the steps
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199 | * Someday we might want to:
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200 | * if (Hard, Loss of Clock, Power-up)
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201 | * Do all steps
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202 | * else if (Double bus fault, watchdog or soft reset)
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203 | * Skip to step 12
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204 | * else (must be a CPU32+ reset command)
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205 | * Skip to step 14
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206 | */
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207 |
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208 | /*
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209 | * Step 7: Deal with clock synthesizer
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210 | * HARDWARE:
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211 | * Change if you're not using an external 25 MHz oscillator.
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212 | */
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213 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */
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214 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
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215 | no LPSTOP slowdown, PLL X1 */
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216 | m360.cdvcr = 0x8000; /* No more writes, no clock division */
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217 |
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218 | /*
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219 | * Step 8: Initialize system protection
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220 | * Enable watchdog
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221 | * Watchdog causes system reset
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222 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
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223 | * Enable double bus fault monitor
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224 | * Enable bus monitor for external cycles
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225 | * 1024 clocks for external timeout
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226 | */
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227 | m360.sypcr = 0xEC;
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228 |
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229 | /*
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230 | * Step 9: Clear parameter RAM and reset communication processor module
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231 | */
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232 | for (i = 0 ; i < 192 ; i += sizeof (long)) {
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233 | *((long *)((char *)&m360 + 0xC00 + i)) = 0;
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234 | *((long *)((char *)&m360 + 0xD00 + i)) = 0;
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235 | *((long *)((char *)&m360 + 0xE00 + i)) = 0;
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236 | *((long *)((char *)&m360 + 0xF00 + i)) = 0;
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237 | }
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238 | M360ExecuteRISC (M360_CR_RST);
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239 |
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240 | /*
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241 | * Step 10: Write PEPAR
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242 | * SINTOUT not used (CPU32+ mode)
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243 | * CF1MODE=00 (CONFIG1 input)
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244 | * RAS1* double drive
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245 | * WE0* - WE3*
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246 | * OE* output
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247 | * CAS2* - CAS3*
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248 | * CAS0* - CAS1*
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249 | * CS7*
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250 | * AVEC*
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251 | * HARDWARE:
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252 | * Change if you are using a different memory configuration
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253 | * (static RAM, external address multiplexing, etc).
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254 | */
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255 | m360.pepar = 0x0180;
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256 |
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257 | /*
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258 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR
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259 | */
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260 | m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
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261 | M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
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262 | M360_GMR_DPS_32BIT | M360_GMR_DWQ |
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263 | M360_GMR_GAMX;
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264 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
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265 | M360_MEMC_BR_V;
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266 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
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267 | M360_MEMC_OR_8BIT;
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268 |
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269 | /*
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270 | * Step 12: Initialize the system RAM
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271 | */
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272 | /* first bank 1MByte DRAM */
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273 | m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
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274 | M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
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275 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
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276 |
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277 | /* second bank 1MByte DRAM */
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278 | m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
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279 | M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
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280 | m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
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281 | M360_MEMC_BR_V;
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282 |
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283 | /* flash rom socket U6 on CS5 */
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284 | m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
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285 | M360_MEMC_BR_V;
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286 | m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
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287 | M360_MEMC_OR_8BIT;
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288 |
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289 | /* CSRs on CS7 */
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290 | m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
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291 | M360_MEMC_OR_8BIT;
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292 | m360.memc[7].br = ATLASHSB_ESR | 0x01;
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293 | for (i = 0; i < 50000; i++)
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294 | continue;
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295 | for (i = 0; i < 8; ++i)
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296 | *((volatile unsigned long *)(unsigned long)&_RamBase);
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297 |
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298 | /*
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299 | * Step 13: Copy the exception vector table to system RAM
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300 | */
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301 | m68k_get_vbr (vbr);
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302 | for (i = 0; i < 256; ++i)
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303 | M68Kvec[i] = vbr[i];
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304 | m68k_set_vbr (M68Kvec);
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305 |
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306 | /*
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307 | * Step 14: More system initialization
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308 | * SDCR (Serial DMA configuration register)
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309 | * Enable SDMA during FREEZE
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310 | * Give SDMA priority over all interrupt handlers
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311 | * Set DMA arbiration level to 4
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312 | * CICR (CPM interrupt configuration register):
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313 | * SCC1 requests at SCCa position
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314 | * SCC2 requests at SCCb position
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315 | * SCC3 requests at SCCc position
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316 | * SCC4 requests at SCCd position
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317 | * Interrupt request level 4
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318 | * Maintain original priority order
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319 | * Vector base 128
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320 | * SCCs priority grouped at top of table
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321 | */
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322 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
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323 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
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324 | (4 << 13) | (0x1F << 8) | (128);
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325 |
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326 | /*
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327 | * Step 15: Set module configuration register
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328 | * Disable timers during FREEZE
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329 | * Enable bus monitor during FREEZE
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330 | * BCLRO* arbitration level 3
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331 | * No show cycles
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332 | * User/supervisor access
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333 | * Bus clear interrupt service level 7
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334 | * SIM60 interrupt sources higher priority than CPM
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335 | */
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336 | m360.mcr = 0x4C7F;
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337 |
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338 | #else
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339 | /*
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340 | ***************************************************
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341 | * Generic Standalone Motorola 68360 *
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342 | * As described in MC68360 User's Manual *
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343 | * Atlas ACE360 *
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344 | ***************************************************
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345 | */
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346 |
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347 | /*
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348 | * Step 6: Is this a power-up reset?
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349 | * For now we just ignore this and do *all* the steps
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350 | * Someday we might want to:
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351 | * if (Hard, Loss of Clock, Power-up)
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352 | * Do all steps
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353 | * else if (Double bus fault, watchdog or soft reset)
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354 | * Skip to step 12
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355 | * else (must be a CPU32+ reset command)
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356 | * Skip to step 14
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357 | */
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358 |
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359 | /*
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360 | * Step 7: Deal with clock synthesizer
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361 | * HARDWARE:
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362 | * Change if you're not using an external 25 MHz oscillator.
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363 | */
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364 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */
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365 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
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366 | no LPSTOP slowdown, PLL X1 */
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367 | m360.cdvcr = 0x8000; /* No more writes, no clock division */
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368 |
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369 | /*
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370 | * Step 8: Initialize system protection
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371 | * Enable watchdog
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372 | * Watchdog causes system reset
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373 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
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374 | * Enable double bus fault monitor
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375 | * Enable bus monitor for external cycles
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376 | * 1024 clocks for external timeout
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377 | */
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378 | m360.sypcr = 0xEC;
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379 |
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380 | /*
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381 | * Step 9: Clear parameter RAM and reset communication processor module
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382 | */
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383 | for (i = 0 ; i < 192 ; i += sizeof (long)) {
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384 | *((long *)((char *)&m360 + 0xC00 + i)) = 0;
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385 | *((long *)((char *)&m360 + 0xD00 + i)) = 0;
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386 | *((long *)((char *)&m360 + 0xE00 + i)) = 0;
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387 | *((long *)((char *)&m360 + 0xF00 + i)) = 0;
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388 | }
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389 | M360ExecuteRISC (M360_CR_RST);
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390 |
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391 | /*
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392 | * Step 10: Write PEPAR
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393 | * SINTOUT not used (CPU32+ mode)
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394 | * CF1MODE=00 (CONFIG1 input)
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395 | * RAS1* double drive
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396 | * WE0* - WE3*
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397 | * OE* output
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398 | * CAS2* - CAS3*
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399 | * CAS0* - CAS1*
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400 | * CS7*
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401 | * AVEC*
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402 | * HARDWARE:
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403 | * Change if you are using a different memory configuration
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404 | * (static RAM, external address multiplexing, etc).
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405 | */
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406 | m360.pepar = 0x0180;
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407 |
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408 | /*
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409 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR
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410 | */
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411 | /*
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412 | * 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips)
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413 | * 60 nsec DRAM
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414 | * 180 nsec ROM (3 wait states)
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415 | */
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416 | switch ((unsigned long)&_RamSize) {
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417 | default:
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418 | case 4*1024*1024:
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419 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
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420 | M360_GMR_RCYC(0) | M360_GMR_PGS(3) |
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421 | M360_GMR_DPS_32BIT | M360_GMR_NCS |
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422 | M360_GMR_GAMX;
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423 | break;
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424 |
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425 | case 16*1024*1024:
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426 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
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427 | M360_GMR_RCYC(0) | M360_GMR_PGS(5) |
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428 | M360_GMR_DPS_32BIT | M360_GMR_NCS |
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429 | M360_GMR_GAMX;
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430 | break;
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431 |
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432 | case 64*1024*1024:
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433 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
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434 | M360_GMR_RCYC(0) | M360_GMR_PGS(7) |
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435 | M360_GMR_DPS_32BIT | M360_GMR_NCS |
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436 | M360_GMR_GAMX;
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---|
437 | break;
|
---|
438 | }
|
---|
439 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
|
---|
440 | M360_MEMC_BR_V;
|
---|
441 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
|
---|
442 | M360_MEMC_OR_8BIT;
|
---|
443 |
|
---|
444 | /*
|
---|
445 | * Step 12: Initialize the system RAM
|
---|
446 | */
|
---|
447 | /*
|
---|
448 | * Set up option/base registers
|
---|
449 | * 4M/16M/64M DRAM
|
---|
450 | * 60 nsec DRAM
|
---|
451 | * Wait for chips to power up
|
---|
452 | * Perform 8 read cycles
|
---|
453 | * Set all parity bits to correct state
|
---|
454 | * Enable parity checking
|
---|
455 | */
|
---|
456 | switch ((unsigned long)&_RamSize) {
|
---|
457 | default:
|
---|
458 | case 4*1024*1024:
|
---|
459 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
|
---|
460 | M360_MEMC_OR_4MB |
|
---|
461 | M360_MEMC_OR_DRAM;
|
---|
462 | break;
|
---|
463 |
|
---|
464 | case 16*1024*1024:
|
---|
465 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
|
---|
466 | M360_MEMC_OR_16MB |
|
---|
467 | M360_MEMC_OR_DRAM;
|
---|
468 | break;
|
---|
469 |
|
---|
470 | case 64*1024*1024:
|
---|
471 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
|
---|
472 | M360_MEMC_OR_64MB |
|
---|
473 | M360_MEMC_OR_DRAM;
|
---|
474 | break;
|
---|
475 | }
|
---|
476 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
|
---|
477 | for (i = 0; i < 50000; i++)
|
---|
478 | continue;
|
---|
479 | for (i = 0; i < 8; ++i)
|
---|
480 | *((volatile unsigned long *)(unsigned long)&_RamBase);
|
---|
481 | for (i = 0 ; i < (unsigned long)&_RamSize ; i += sizeof (unsigned long)) {
|
---|
482 | volatile unsigned long *lp;
|
---|
483 | lp = (unsigned long *)((unsigned char *)&_RamBase + i);
|
---|
484 | *lp = *lp;
|
---|
485 | }
|
---|
486 | m360.memc[1].br = (unsigned long)&_RamBase |
|
---|
487 | M360_MEMC_BR_PAREN | M360_MEMC_BR_V;
|
---|
488 |
|
---|
489 | /*
|
---|
490 | * Step 13: Copy the exception vector table to system RAM
|
---|
491 | */
|
---|
492 | m68k_get_vbr (vbr);
|
---|
493 | for (i = 0; i < 256; ++i)
|
---|
494 | M68Kvec[i] = vbr[i];
|
---|
495 | m68k_set_vbr (M68Kvec);
|
---|
496 |
|
---|
497 | /*
|
---|
498 | * Step 14: More system initialization
|
---|
499 | * SDCR (Serial DMA configuration register)
|
---|
500 | * Enable SDMA during FREEZE
|
---|
501 | * Give SDMA priority over all interrupt handlers
|
---|
502 | * Set DMA arbiration level to 4
|
---|
503 | * CICR (CPM interrupt configuration register):
|
---|
504 | * SCC1 requests at SCCa position
|
---|
505 | * SCC2 requests at SCCb position
|
---|
506 | * SCC3 requests at SCCc position
|
---|
507 | * SCC4 requests at SCCd position
|
---|
508 | * Interrupt request level 4
|
---|
509 | * Maintain original priority order
|
---|
510 | * Vector base 128
|
---|
511 | * SCCs priority grouped at top of table
|
---|
512 | */
|
---|
513 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
|
---|
514 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
|
---|
515 | (4 << 13) | (0x1F << 8) | (128);
|
---|
516 |
|
---|
517 | /*
|
---|
518 | * Step 15: Set module configuration register
|
---|
519 | * Disable timers during FREEZE
|
---|
520 | * Enable bus monitor during FREEZE
|
---|
521 | * BCLRO* arbitration level 3
|
---|
522 | * No show cycles
|
---|
523 | * User/supervisor access
|
---|
524 | * Bus clear interrupt service level 7
|
---|
525 | * SIM60 interrupt sources higher priority than CPM
|
---|
526 | */
|
---|
527 | m360.mcr = 0x4C7F;
|
---|
528 | #endif
|
---|
529 |
|
---|
530 | /*
|
---|
531 | * Copy data, clear BSS, switch stacks and call main()
|
---|
532 | */
|
---|
533 | _CopyDataClearBSSAndStart ();
|
---|
534 | }
|
---|