source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ b04a2b3

4.104.114.84.95
Last change on this file since b04a2b3 was d1a7910, checked in by Joel Sherrill <joel.sherrill@…>, on 09/21/01 at 17:50:39

2001-09-14 Eric Norum <eric.norum@…>

  • startup/init68360.c: Modifications to make gcc 3.x happy.
  • Property mode set to 100644
File size: 18.7 KB
Line 
1/*
2 * MC68360 support routines
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
15#include <m68360.h>
16
17/*
18 * Send a command to the CPM RISC processer
19 */
20
21void M360ExecuteRISC(rtems_unsigned16 command)
22{
23        rtems_unsigned16 sr;
24
25        m68k_disable_interrupts (sr);
26        while (m360.cr & M360_CR_FLG)
27                continue;
28        m360.cr = command | M360_CR_FLG;
29        m68k_enable_interrupts (sr);
30}
31
32/*
33 * Initialize MC68360
34 */
35void _Init68360 (void)
36{
37        int i;
38        m68k_isr_entry *vbr;
39        unsigned long ramSize;
40        extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
41
42#if (defined (__mc68040__))
43        /*
44         *******************************************
45         * Motorola 68040 and companion-mode 68360 *
46         *******************************************
47         */
48
49        /*
50         * Step 6: Is this a power-up reset?
51         * For now we just ignore this and do *all* the steps
52         * Someday we might want to:
53         *      if (Hard, Loss of Clock, Power-up)
54         *              Do all steps
55         *      else if (Double bus fault, watchdog or soft reset)
56         *              Skip to step 12
57         *      else (must be a reset command)
58         *              Skip to step 14
59         */
60
61        /*
62         * Step 7: Deal with clock synthesizer
63         * HARDWARE:
64         *      Change if you're not using an external 25 MHz oscillator.
65         */
66        m360.clkocr = 0x83;     /* No more writes, full-power CLKO2 */
67        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
68                                   no LPSTOP slowdown, PLL X1 */
69        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
70
71        /*
72         * Step 8: Initialize system protection
73         *      Enable watchdog
74         *      Watchdog causes system reset
75         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
76         *      Enable double bus fault monitor
77         *      Enable bus monitor for external cycles
78         *      1024 clocks for external timeout
79         */
80        m360.sypcr = 0xEC;
81
82        /*
83         * Step 9: Clear parameter RAM and reset communication processor module
84         */
85        for (i = 0 ; i < 192  ; i += sizeof (long)) {
86                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
87                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
88                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
89                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
90        }
91        M360ExecuteRISC (M360_CR_RST);
92
93        /*
94         * Step 10: Write PEPAR
95         *      SINTOUT standard M68000 family interrupt level encoding
96         *      CF1MODE=10 (BCLRO* output)
97         *      No RAS1* double drive
98         *      A31 - A28
99         *      AMUX output
100         *      CAS2* - CAS3*
101         *      CAS0* - CAS1*
102         *      CS7*
103         *      AVEC*
104         */
105        m360.pepar = 0x3440;
106
107        /*
108         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
109         */
110        /*
111         * 512 addresses per DRAM page (256K DRAM chips)
112         * 70 nsec DRAM
113         * 180 nsec ROM (3 wait states)
114         */
115        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
116                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
117                                M360_GMR_DPS_32BIT | M360_GMR_NCS |
118                                M360_GMR_TSS40;
119        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
120                                                        M360_MEMC_BR_V;
121        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
122                                                M360_MEMC_OR_32BIT;
123
124        /*
125         * Step 12: Initialize the system RAM
126         */
127        /*
128         *      Set up option/base registers
129         *              1M DRAM
130         *              70 nsec DRAM
131         *      Enable burst mode
132         *      No parity checking
133         *      Wait for chips to power up
134         *      Perform 8 read cycles
135         */
136        ramSize = 1 * 1024 * 1024;
137        m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
138                                        M360_MEMC_OR_1MB |
139                                        M360_MEMC_OR_DRAM;
140        m360.memc[1].br = (unsigned long)&_RamBase |
141                                        M360_MEMC_BR_BACK40 |
142                                        M360_MEMC_BR_V;
143        for (i = 0; i < 50000; i++)
144                continue;
145        for (i = 0; i < 8; ++i)
146                *((volatile unsigned long *)(unsigned long)&_RamBase);
147
148        /*
149         * Step 13: Copy  the exception vector table to system RAM
150         */
151        m68k_get_vbr (vbr);
152        for (i = 0; i < 256; ++i)
153                M68Kvec[i] = vbr[i];
154        m68k_set_vbr (M68Kvec);
155       
156        /*
157         * Step 14: More system initialization
158         * SDCR (Serial DMA configuration register)
159         *      Enable SDMA during FREEZE
160         *      Give SDMA priority over all interrupt handlers
161         *      Set DMA arbiration level to 4
162         * CICR (CPM interrupt configuration register):
163         *      SCC1 requests at SCCa position
164         *      SCC2 requests at SCCb position
165         *      SCC3 requests at SCCc position
166         *      SCC4 requests at SCCd position
167         *      Interrupt request level 4
168         *      Maintain original priority order
169         *      Vector base 128
170         *      SCCs priority grouped at top of table
171         */
172        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
173        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
174                                                (4 << 13) | (0x1F << 8) | (128);
175
176        /*
177         * Step 15: Set module configuration register
178         *      Bus request MC68040 Arbitration ID 3
179         *      Bus asynchronous timing mode (work around bug in Rev. B)
180         *      Arbitration asynchronous timing mode
181         *      Disable timers during FREEZE
182         *      Disable bus monitor during FREEZE
183         *      BCLRO* arbitration level 3
184         *      No show cycles
185         *      User/supervisor access
186         *      Bus clear in arbitration ID level  3
187         *      SIM60 interrupt sources higher priority than CPM
188         */
189        m360.mcr = 0x6000EC3F;
190
191#elif (defined (M68360_ATLAS_HSB))
192        /*
193         ******************************************
194         * Standalone Motorola 68360 -- ATLAS HSB *
195         ******************************************
196         */
197
198        /*
199         * Step 6: Is this a power-up reset?
200         * For now we just ignore this and do *all* the steps
201         * Someday we might want to:
202         *      if (Hard, Loss of Clock, Power-up)
203         *              Do all steps
204         *      else if (Double bus fault, watchdog or soft reset)
205         *              Skip to step 12
206         *      else (must be a CPU32+ reset command)
207         *              Skip to step 14
208         */
209
210        /*
211         * Step 7: Deal with clock synthesizer
212         * HARDWARE:
213         *      Change if you're not using an external 25 MHz oscillator.
214         */
215        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
216        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
217                                   no LPSTOP slowdown, PLL X1 */
218        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
219
220        /*
221         * Step 8: Initialize system protection
222         *      Enable watchdog
223         *      Watchdog causes system reset
224         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
225         *      Enable double bus fault monitor
226         *      Enable bus monitor for external cycles
227         *      1024 clocks for external timeout
228         */
229        m360.sypcr = 0xEC;
230
231        /*
232         * Step 9: Clear parameter RAM and reset communication processor module
233         */
234        for (i = 0 ; i < 192  ; i += sizeof (long)) {
235                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
236                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
237                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
238                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
239        }
240        M360ExecuteRISC (M360_CR_RST);
241
242        /*
243         * Step 10: Write PEPAR
244         *      SINTOUT not used (CPU32+ mode)
245         *      CF1MODE=00 (CONFIG1 input)
246         *      RAS1* double drive
247         *      WE0* - WE3*
248         *      OE* output
249         *      CAS2* - CAS3*
250         *      CAS0* - CAS1*
251         *      CS7*
252         *      AVEC*
253         * HARDWARE:
254         *      Change if you are using a different memory configuration
255         *      (static RAM, external address multiplexing, etc).
256         */
257        m360.pepar = 0x0180;
258
259        /*
260         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
261         */
262        m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
263                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
264                                M360_GMR_DPS_32BIT | M360_GMR_DWQ |
265                                M360_GMR_GAMX;
266        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
267                                                                M360_MEMC_BR_V;
268        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
269                                                        M360_MEMC_OR_8BIT;
270
271        /*
272         * Step 12: Initialize the system RAM
273         */
274        ramSize = 2 * 1024 * 1024;
275        /* first bank 1MByte DRAM */
276        m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
277                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
278        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
279
280        /* second bank 1MByte DRAM */
281        m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
282                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
283        m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
284                                        M360_MEMC_BR_V;
285
286        /* flash rom socket U6 on CS5 */
287        m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
288                                                                M360_MEMC_BR_V;
289        m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
290                                                                M360_MEMC_OR_8BIT;
291
292        /* CSRs on CS7 */
293        m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
294                                        M360_MEMC_OR_8BIT;
295        m360.memc[7].br = ATLASHSB_ESR | 0x01;
296        for (i = 0; i < 50000; i++)
297                continue;
298        for (i = 0; i < 8; ++i)
299                *((volatile unsigned long *)(unsigned long)&_RamBase);
300
301        /*
302         * Step 13: Copy  the exception vector table to system RAM
303         */
304        m68k_get_vbr (vbr);
305        for (i = 0; i < 256; ++i)
306                M68Kvec[i] = vbr[i];
307        m68k_set_vbr (M68Kvec);
308       
309        /*
310         * Step 14: More system initialization
311         * SDCR (Serial DMA configuration register)
312         *      Enable SDMA during FREEZE
313         *      Give SDMA priority over all interrupt handlers
314         *      Set DMA arbiration level to 4
315         * CICR (CPM interrupt configuration register):
316         *      SCC1 requests at SCCa position
317         *      SCC2 requests at SCCb position
318         *      SCC3 requests at SCCc position
319         *      SCC4 requests at SCCd position
320         *      Interrupt request level 4
321         *      Maintain original priority order
322         *      Vector base 128
323         *      SCCs priority grouped at top of table
324         */
325        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
326        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
327                                                (4 << 13) | (0x1F << 8) | (128);
328
329        /*
330         * Step 15: Set module configuration register
331         *      Disable timers during FREEZE
332         *      Enable bus monitor during FREEZE
333         *      BCLRO* arbitration level 3
334         */
335
336#elif (defined (GEN68360_WITH_SRAM))
337   /*
338    ***************************************************
339    * Generic Standalone Motorola 68360               *
340    *           As described in MC68360 User's Manual *
341    * But uses SRAM instead of DRAM                   *
342    *  CS0* - 512kx8 flash memory                     *
343    *  CS1* - 512kx32 static RAM                      *
344    *  CS2* - 512kx32 static RAM                      *
345    ***************************************************
346    */
347
348   /*
349    * Step 7: Deal with clock synthesizer
350    * HARDWARE:
351    * Change if you're not using an external oscillator which
352    * oscillates at the system clock rate.
353    */
354   m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
355   m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
356                              no LPSTOP slowdown, PLL X1 */
357   m360.cdvcr = 0x8000;    /* No more writes, no clock division */
358
359   /*
360    * Step 8: Initialize system protection
361    * Enable watchdog
362    * Watchdog causes system reset
363    * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
364    * Enable double bus fault monitor
365    * Enable bus monitor for external cycles
366    * 1024 clocks for external timeout
367    */
368    m360.sypcr = 0xEC;
369
370   /*
371    * Step 9: Clear parameter RAM and reset communication processor module
372    */
373   for (i = 0 ; i < 192  ; i += sizeof (long)) {
374      *((long *)((char *)&m360 + 0xC00 + i)) = 0;
375      *((long *)((char *)&m360 + 0xD00 + i)) = 0;
376      *((long *)((char *)&m360 + 0xE00 + i)) = 0;
377      *((long *)((char *)&m360 + 0xF00 + i)) = 0;
378   }
379   M360ExecuteRISC (M360_CR_RST);
380
381   /*
382    * Step 10: Write PEPAR
383    * SINTOUT not used (CPU32+ mode)
384    * CF1MODE=00 (CONFIG1 input)
385    * IPIPE1*
386    * WE0* - WE3*
387    * OE* output
388    * CAS2* - CAS3*
389    * CAS0* - CAS1*
390    * CS7*
391    * AVEC*
392    * HARDWARE:
393    * Change if you are using a different memory configuration
394    * (static RAM, external address multiplexing, etc).
395    */
396   m360.pepar = 0x0080;
397
398   /*
399    * Step 11: Set up GMR
400    *     
401    */
402   m360.gmr = 0x0;
403
404   /*
405    * Step 11a: Remap 512Kx8 flash memory on CS0*
406    * 2 wait states
407    * Make it read-only for now
408    */
409   m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
410                                                   M360_MEMC_BR_V;
411   m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
412                                                   M360_MEMC_OR_8BIT;
413   /*
414    * Step 12: Set up main memory
415    * 512Kx32 SRAM on CS1*
416    * 512Kx32 SRAM on CS2*
417    * 0 wait states
418    */
419   ramSize = 4 * 1024 * 1024;
420   m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
421   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
422                                                   M360_MEMC_OR_32BIT;
423   m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V;
424   m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
425                                                   M360_MEMC_OR_32BIT;
426   /*
427    * Step 13: Copy  the exception vector table to system RAM
428    */
429   m68k_get_vbr (vbr);
430   for (i = 0; i < 256; ++i)
431           M68Kvec[i] = vbr[i];
432   m68k_set_vbr (M68Kvec);
433
434   /*
435    * Step 14: More system initialization
436    * SDCR (Serial DMA configuration register)
437    * Enable SDMA during FREEZE
438    * Give SDMA priority over all interrupt handlers
439    * Set DMA arbiration level to 4
440    * CICR (CPM interrupt configuration register):
441    * SCC1 requests at SCCa position
442    * SCC2 requests at SCCb position
443    * SCC3 requests at SCCc position
444    * SCC4 requests at SCCd position
445    * Interrupt request level 4
446    * Maintain original priority order
447    * Vector base 128
448    * SCCs priority grouped at top of table
449    */
450   m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
451   m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
452                  (4 << 13) | (0x1F << 8) | (128);
453
454   /*
455    * Step 15: Set module configuration register
456    * Disable timers during FREEZE
457    * Enable bus monitor during FREEZE
458    * BCLRO* arbitration level 3
459    * No show cycles
460    * User/supervisor access
461    * Bus clear interrupt service level 7
462    * SIM60 interrupt sources higher priority than CPM
463    */
464   m360.mcr = 0x4C7F;
465
466#else
467        /*
468         ***************************************************
469         * Generic Standalone Motorola 68360               *
470         *           As described in MC68360 User's Manual *
471         *           Atlas ACE360                          *
472         ***************************************************
473         */
474
475        /*
476         * Step 6: Is this a power-up reset?
477         * For now we just ignore this and do *all* the steps
478         * Someday we might want to:
479         *      if (Hard, Loss of Clock, Power-up)
480         *              Do all steps
481         *      else if (Double bus fault, watchdog or soft reset)
482         *              Skip to step 12
483         *      else (must be a CPU32+ reset command)
484         *              Skip to step 14
485         */
486
487        /*
488         * Step 7: Deal with clock synthesizer
489         * HARDWARE:
490         *      Change if you're not using an external 25 MHz oscillator.
491         */
492        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
493        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
494                                   no LPSTOP slowdown, PLL X1 */
495        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
496
497        /*
498         * Step 8: Initialize system protection
499         *      Enable watchdog
500         *      Watchdog causes system reset
501         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
502         *      Enable double bus fault monitor
503         *      Enable bus monitor for external cycles
504         *      1024 clocks for external timeout
505         */
506        m360.sypcr = 0xEC;
507
508        /*
509         * Step 9: Clear parameter RAM and reset communication processor module
510         */
511        for (i = 0 ; i < 192  ; i += sizeof (long)) {
512                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
513                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
514                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
515                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
516        }
517        M360ExecuteRISC (M360_CR_RST);
518
519        /*
520         * Step 10: Write PEPAR
521         *      SINTOUT not used (CPU32+ mode)
522         *      CF1MODE=00 (CONFIG1 input)
523         *      RAS1* double drive
524         *      WE0* - WE3*
525         *      OE* output
526         *      CAS2* - CAS3*
527         *      CAS0* - CAS1*
528         *      CS7*
529         *      AVEC*
530         * HARDWARE:
531         *      Change if you are using a different memory configuration
532         *      (static RAM, external address multiplexing, etc).
533         */
534        m360.pepar = 0x0180;
535
536        /*
537         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
538         *      32-bit DRAM
539         *      Internal DRAM address multiplexing
540         *      60 nsec DRAM
541         *      180 nsec ROM (3 wait states)
542         *      15.36 usec DRAM refresh interval
543         *      The DRAM page size selection is not modified since this
544         *      startup code may be running in a bootstrap PROM or in
545         *      a program downloaded by the bootstrap PROM.
546         */
547        m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
548                                        M360_GMR_RFEN | M360_GMR_RCYC(0) |
549                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
550                                        M360_GMR_GAMX;
551        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
552                                                                M360_MEMC_BR_V;
553        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
554                                                        M360_MEMC_OR_8BIT;
555
556        /*
557         * Step 12: Initialize the system RAM
558         * Do this only if the DRAM has not already been set up
559         */
560        if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
561                /*
562                 * Set up GMR DRAM page size, option and  base registers
563                 *      Assume 16Mbytes of DRAM
564                 *      60 nsec DRAM
565                 */
566                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
567                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
568                                                M360_MEMC_OR_16MB |
569                                                M360_MEMC_OR_DRAM;
570                m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
571
572                /*
573                 * Wait for chips to power up
574                 *      Perform 8 read cycles
575                 */
576                for (i = 0; i < 50000; i++)
577                        continue;
578                for (i = 0; i < 8; ++i)
579                        *((volatile unsigned long *)(unsigned long)&_RamBase);
580
581                /*
582                 * Determine memory size (1, 4, or 16 Mbytes)
583                 * Set GMR DRAM page size appropriately.
584                 * The OR is left at 16 Mbytes.  The bootstrap PROM places its
585                 * .data and .bss segments at the top of the 16 Mbyte space.
586                 * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
587                 * the memory map, but will work with the same bootstrap PROM.
588                 */
589                *(volatile char *)&_RamBase = 0;
590                *((volatile char *)&_RamBase+0x00C01800) = 1;
591                if (*(volatile char *)&_RamBase) {
592                        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
593                }
594                else {
595                        *((volatile char *)&_RamBase+0x00801000) = 1;
596                        if (*(volatile char *)&_RamBase) {
597                                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
598                        }
599                }
600
601                /*
602                 * Enable parity checking
603                 */
604                m360.memc[1].br |= M360_MEMC_BR_PAREN;
605        }
606        switch (m360.gmr & 0x001C0000) {
607        default:                ramSize =  4 * 1024 * 1024;     break;
608        case M360_GMR_PGS(1):   ramSize =  1 * 1024 * 1024;     break;
609        case M360_GMR_PGS(3):   ramSize =  4 * 1024 * 1024;     break;
610        case M360_GMR_PGS(5):   ramSize = 16 * 1024 * 1024;     break;
611        }
612
613        /*
614         * Step 13: Copy  the exception vector table to system RAM
615         */
616        m68k_get_vbr (vbr);
617        for (i = 0; i < 256; ++i)
618                M68Kvec[i] = vbr[i];
619        m68k_set_vbr (M68Kvec);
620       
621        /*
622         * Step 14: More system initialization
623         * SDCR (Serial DMA configuration register)
624         *      Enable SDMA during FREEZE
625         *      Give SDMA priority over all interrupt handlers
626         *      Set DMA arbiration level to 4
627         * CICR (CPM interrupt configuration register):
628         *      SCC1 requests at SCCa position
629         *      SCC2 requests at SCCb position
630         *      SCC3 requests at SCCc position
631         *      SCC4 requests at SCCd position
632         *      Interrupt request level 4
633         *      Maintain original priority order
634         *      Vector base 128
635         *      SCCs priority grouped at top of table
636         */
637        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
638        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
639                                                (4 << 13) | (0x1F << 8) | (128);
640
641        /*
642         * Step 15: Set module configuration register
643         *      Disable timers during FREEZE
644         *      Enable bus monitor during FREEZE
645         *      BCLRO* arbitration level 3
646         *      No show cycles
647         *      User/supervisor access
648         *      Bus clear interrupt service level 7
649         *      SIM60 interrupt sources higher priority than CPM
650         */
651        m360.mcr = 0x4C7F;
652#endif
653
654        /*
655         * Copy data, clear BSS, switch stacks and call main()
656         * Must pass ramSize as argument since the data/bss segment
657         * may be overwritten.
658         */
659        _CopyDataClearBSSAndStart (ramSize);
660}
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