source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ 6e7b6ca

4.104.114.84.95
Last change on this file since 6e7b6ca was 6e7b6ca, checked in by Joel Sherrill <joel.sherrill@…>, on 01/10/00 at 15:03:28

Fixed unterminated comment spotted by eagle eye Ralf Corsepius
<corsepiu@…>.

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1/*
2 * MC68360 support routines
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
15#include <m68360.h>
16
17/*
18 * Declare the m360 structure here for the benefit of the debugger
19 */
20
21m360_t m360;
22
23/*
24 * Send a command to the CPM RISC processer
25 */
26
27void M360ExecuteRISC(rtems_unsigned16 command)
28{
29        rtems_unsigned16 sr;
30
31        m68k_disable_interrupts (sr);
32        while (m360.cr & M360_CR_FLG)
33                continue;
34        m360.cr = command | M360_CR_FLG;
35        m68k_enable_interrupts (sr);
36}
37
38/*
39 * Initialize MC68360
40 */
41void _Init68360 (void)
42{
43        int i;
44        m68k_isr_entry *vbr;
45        extern void _CopyDataClearBSSAndStart (void);
46
47#if (defined (__mc68040__))
48        /*
49         *******************************************
50         * Motorola 68040 and companion-mode 68360 *
51         *******************************************
52         */
53
54        /*
55         * Step 6: Is this a power-up reset?
56         * For now we just ignore this and do *all* the steps
57         * Someday we might want to:
58         *      if (Hard, Loss of Clock, Power-up)
59         *              Do all steps
60         *      else if (Double bus fault, watchdog or soft reset)
61         *              Skip to step 12
62         *      else (must be a reset command)
63         *              Skip to step 14
64         */
65
66        /*
67         * Step 7: Deal with clock synthesizer
68         * HARDWARE:
69         *      Change if you're not using an external 25 MHz oscillator.
70         */
71        m360.clkocr = 0x83;     /* No more writes, full-power CLKO2 */
72        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
73                                   no LPSTOP slowdown, PLL X1 */
74        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
75
76        /*
77         * Step 8: Initialize system protection
78         *      Enable watchdog
79         *      Watchdog causes system reset
80         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
81         *      Enable double bus fault monitor
82         *      Enable bus monitor for external cycles
83         *      1024 clocks for external timeout
84         */
85        m360.sypcr = 0xEC;
86
87        /*
88         * Step 9: Clear parameter RAM and reset communication processor module
89         */
90        for (i = 0 ; i < 192  ; i += sizeof (long)) {
91                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
92                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
93                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
94                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
95        }
96        M360ExecuteRISC (M360_CR_RST);
97
98        /*
99         * Step 10: Write PEPAR
100         *      SINTOUT standard M68000 family interrupt level encoding
101         *      CF1MODE=10 (BCLRO* output)
102         *      No RAS1* double drive
103         *      A31 - A28
104         *      AMUX output
105         *      CAS2* - CAS3*
106         *      CAS0* - CAS1*
107         *      CS7*
108         *      AVEC*
109         */
110        m360.pepar = 0x3440;
111
112        /*
113         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
114         */
115        /*
116         * 512 addresses per DRAM page (256K DRAM chips)
117         * 70 nsec DRAM
118         * 180 nsec ROM (3 wait states)
119         */
120        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
121                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
122                                M360_GMR_DPS_32BIT | M360_GMR_NCS |
123                                M360_GMR_TSS40;
124        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
125                                                        M360_MEMC_BR_V;
126        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
127                                                M360_MEMC_OR_32BIT;
128
129        /*
130         * Step 12: Initialize the system RAM
131         */
132        /*
133         *      Set up option/base registers
134         *              1M DRAM
135         *              70 nsec DRAM
136         *      Enable burst mode
137         *      No parity checking
138         *      Wait for chips to power up
139         *      Perform 8 read cycles
140         */
141        m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
142                                        M360_MEMC_OR_1MB |
143                                        M360_MEMC_OR_DRAM;
144        m360.memc[1].br = (unsigned long)&_RamBase |
145                                        M360_MEMC_BR_BACK40 |
146                                        M360_MEMC_BR_V;
147        for (i = 0; i < 50000; i++)
148                continue;
149        for (i = 0; i < 8; ++i)
150                *((volatile unsigned long *)(unsigned long)&_RamBase);
151
152        /*
153         * Step 13: Copy  the exception vector table to system RAM
154         */
155        m68k_get_vbr (vbr);
156        for (i = 0; i < 256; ++i)
157                M68Kvec[i] = vbr[i];
158        m68k_set_vbr (M68Kvec);
159       
160        /*
161         * Step 14: More system initialization
162         * SDCR (Serial DMA configuration register)
163         *      Enable SDMA during FREEZE
164         *      Give SDMA priority over all interrupt handlers
165         *      Set DMA arbiration level to 4
166         * CICR (CPM interrupt configuration register):
167         *      SCC1 requests at SCCa position
168         *      SCC2 requests at SCCb position
169         *      SCC3 requests at SCCc position
170         *      SCC4 requests at SCCd position
171         *      Interrupt request level 4
172         *      Maintain original priority order
173         *      Vector base 128
174         *      SCCs priority grouped at top of table
175         */
176        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
177        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
178                                                (4 << 13) | (0x1F << 8) | (128);
179
180        /*
181         * Step 15: Set module configuration register
182         *      Bus request MC68040 Arbitration ID 3
183         *      Bus asynchronous timing mode (work around bug in Rev. B)
184         *      Arbitration asynchronous timing mode
185         *      Disable timers during FREEZE
186         *      Disable bus monitor during FREEZE
187         *      BCLRO* arbitration level 3
188         *      No show cycles
189         *      User/supervisor access
190         *      Bus clear in arbitration ID level  3
191         *      SIM60 interrupt sources higher priority than CPM
192         */
193        m360.mcr = 0x6000EC3F;
194
195#elif (defined (M68360_ATLAS_HSB))
196        /*
197         ******************************************
198         * Standalone Motorola 68360 -- ATLAS HSB *
199         ******************************************
200         */
201
202        /*
203         * Step 6: Is this a power-up reset?
204         * For now we just ignore this and do *all* the steps
205         * Someday we might want to:
206         *      if (Hard, Loss of Clock, Power-up)
207         *              Do all steps
208         *      else if (Double bus fault, watchdog or soft reset)
209         *              Skip to step 12
210         *      else (must be a CPU32+ reset command)
211         *              Skip to step 14
212         */
213
214        /*
215         * Step 7: Deal with clock synthesizer
216         * HARDWARE:
217         *      Change if you're not using an external 25 MHz oscillator.
218         */
219        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
220        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
221                                   no LPSTOP slowdown, PLL X1 */
222        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
223
224        /*
225         * Step 8: Initialize system protection
226         *      Enable watchdog
227         *      Watchdog causes system reset
228         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
229         *      Enable double bus fault monitor
230         *      Enable bus monitor for external cycles
231         *      1024 clocks for external timeout
232         */
233        m360.sypcr = 0xEC;
234
235        /*
236         * Step 9: Clear parameter RAM and reset communication processor module
237         */
238        for (i = 0 ; i < 192  ; i += sizeof (long)) {
239                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
240                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
241                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
242                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
243        }
244        M360ExecuteRISC (M360_CR_RST);
245
246        /*
247         * Step 10: Write PEPAR
248         *      SINTOUT not used (CPU32+ mode)
249         *      CF1MODE=00 (CONFIG1 input)
250         *      RAS1* double drive
251         *      WE0* - WE3*
252         *      OE* output
253         *      CAS2* - CAS3*
254         *      CAS0* - CAS1*
255         *      CS7*
256         *      AVEC*
257         * HARDWARE:
258         *      Change if you are using a different memory configuration
259         *      (static RAM, external address multiplexing, etc).
260         */
261        m360.pepar = 0x0180;
262
263        /*
264         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
265         */
266        m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
267                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
268                                M360_GMR_DPS_32BIT | M360_GMR_DWQ |
269                                M360_GMR_GAMX;
270        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
271                                                                M360_MEMC_BR_V;
272        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
273                                                        M360_MEMC_OR_8BIT;
274
275        /*
276         * Step 12: Initialize the system RAM
277         */
278        /* first bank 1MByte DRAM */
279        m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
280                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
281        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
282
283        /* second bank 1MByte DRAM */
284        m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
285                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
286        m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
287                                        M360_MEMC_BR_V;
288
289        /* flash rom socket U6 on CS5 */
290        m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
291                                                                M360_MEMC_BR_V;
292        m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
293                                                                M360_MEMC_OR_8BIT;
294
295        /* CSRs on CS7 */
296        m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
297                                        M360_MEMC_OR_8BIT;
298        m360.memc[7].br = ATLASHSB_ESR | 0x01;
299        for (i = 0; i < 50000; i++)
300                continue;
301        for (i = 0; i < 8; ++i)
302                *((volatile unsigned long *)(unsigned long)&_RamBase);
303
304        /*
305         * Step 13: Copy  the exception vector table to system RAM
306         */
307        m68k_get_vbr (vbr);
308        for (i = 0; i < 256; ++i)
309                M68Kvec[i] = vbr[i];
310        m68k_set_vbr (M68Kvec);
311       
312        /*
313         * Step 14: More system initialization
314         * SDCR (Serial DMA configuration register)
315         *      Enable SDMA during FREEZE
316         *      Give SDMA priority over all interrupt handlers
317         *      Set DMA arbiration level to 4
318         * CICR (CPM interrupt configuration register):
319         *      SCC1 requests at SCCa position
320         *      SCC2 requests at SCCb position
321         *      SCC3 requests at SCCc position
322         *      SCC4 requests at SCCd position
323         *      Interrupt request level 4
324         *      Maintain original priority order
325         *      Vector base 128
326         *      SCCs priority grouped at top of table
327         */
328        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
329        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
330                                                (4 << 13) | (0x1F << 8) | (128);
331
332        /*
333         * Step 15: Set module configuration register
334         *      Disable timers during FREEZE
335         *      Enable bus monitor during FREEZE
336         *      BCLRO* arbitration level 3
337         */
338
339#elif (defined (GEN68360_WITH_SRAM))
340   /*
341    ***************************************************
342    * Generic Standalone Motorola 68360               *
343    *           As described in MC68360 User's Manual *
344    * But uses SRAM instead of DRAM                   *
345    *  CS0* - 512kx8 flash memory                     *
346    *  CS1* - 512kx32 static RAM                      *
347    ***************************************************
348    */
349
350   /*
351    * Step 7: Deal with clock synthesizer
352    * HARDWARE:
353    * Change if you're not using an external oscillator which
354    * oscillates at the system clock rate.
355    */
356   m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
357   m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
358                              no LPSTOP slowdown, PLL X1 */
359   m360.cdvcr = 0x8000;    /* No more writes, no clock division */
360
361   /*
362    * Step 8: Initialize system protection
363    * Enable watchdog
364    * Watchdog causes system reset
365    * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
366    * Enable double bus fault monitor
367    * Enable bus monitor for external cycles
368    * 1024 clocks for external timeout
369    */
370    m360.sypcr = 0xEC;
371
372   /*
373    * Step 9: Clear parameter RAM and reset communication processor module
374    */
375   for (i = 0 ; i < 192  ; i += sizeof (long)) {
376      *((long *)((char *)&m360 + 0xC00 + i)) = 0;
377      *((long *)((char *)&m360 + 0xD00 + i)) = 0;
378      *((long *)((char *)&m360 + 0xE00 + i)) = 0;
379      *((long *)((char *)&m360 + 0xF00 + i)) = 0;
380   }
381   M360ExecuteRISC (M360_CR_RST);
382
383   /*
384    * Step 10: Write PEPAR
385    * SINTOUT not used (CPU32+ mode)
386    * CF1MODE=00 (CONFIG1 input)
387    * IPIPE1*
388    * WE0* - WE3*
389    * OE* output
390    * CAS2* - CAS3*
391    * CAS0* - CAS1*
392    * CS7*
393    * AVEC*
394    * HARDWARE:
395    * Change if you are using a different memory configuration
396    * (static RAM, external address multiplexing, etc).
397    */
398   m360.pepar = 0x0080;
399
400   /*
401    * Step 11: Set up GMR
402    *     
403    */
404   m360.gmr = 0x0;
405
406   /*
407    * Step 11a: Remap 512Kx8 flash memory on CS0*
408    * 2 wait states
409    * Make it read-only for now
410    */
411   m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
412                                                   M360_MEMC_BR_V;
413   m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
414                                                   M360_MEMC_OR_8BIT;
415   /*
416    * Step 12: Set up main memory
417    * 512Kx32 SRAM on CS1*
418    * 0 wait states
419    */
420   m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
421   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
422                                                   M360_MEMC_OR_32BIT;
423   /*
424    * Step 13: Copy  the exception vector table to system RAM
425    */
426   m68k_get_vbr (vbr);
427   for (i = 0; i < 256; ++i)
428           M68Kvec[i] = vbr[i];
429   m68k_set_vbr (M68Kvec);
430
431   /*
432    * Step 14: More system initialization
433    * SDCR (Serial DMA configuration register)
434    * Enable SDMA during FREEZE
435    * Give SDMA priority over all interrupt handlers
436    * Set DMA arbiration level to 4
437    * CICR (CPM interrupt configuration register):
438    * SCC1 requests at SCCa position
439    * SCC2 requests at SCCb position
440    * SCC3 requests at SCCc position
441    * SCC4 requests at SCCd position
442    * Interrupt request level 4
443    * Maintain original priority order
444    * Vector base 128
445    * SCCs priority grouped at top of table
446    */
447   m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
448   m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
449                  (4 << 13) | (0x1F << 8) | (128);
450
451   /*
452    * Step 15: Set module configuration register
453    * Disable timers during FREEZE
454    * Enable bus monitor during FREEZE
455    * BCLRO* arbitration level 3
456    * No show cycles
457    * User/supervisor access
458    * Bus clear interrupt service level 7
459    * SIM60 interrupt sources higher priority than CPM
460    */
461   m360.mcr = 0x4C7F;
462         *      No show cycles
463         *      User/supervisor access
464         *      Bus clear interrupt service level 7
465         *      SIM60 interrupt sources higher priority than CPM
466         */
467        m360.mcr = 0x4C7F;
468
469#else
470        /*
471         ***************************************************
472         * Generic Standalone Motorola 68360               *
473         *           As described in MC68360 User's Manual *
474         *           Atlas ACE360                          *
475         ***************************************************
476         */
477
478        /*
479         * Step 6: Is this a power-up reset?
480         * For now we just ignore this and do *all* the steps
481         * Someday we might want to:
482         *      if (Hard, Loss of Clock, Power-up)
483         *              Do all steps
484         *      else if (Double bus fault, watchdog or soft reset)
485         *              Skip to step 12
486         *      else (must be a CPU32+ reset command)
487         *              Skip to step 14
488         */
489
490        /*
491         * Step 7: Deal with clock synthesizer
492         * HARDWARE:
493         *      Change if you're not using an external 25 MHz oscillator.
494         */
495        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
496        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
497                                   no LPSTOP slowdown, PLL X1 */
498        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
499
500        /*
501         * Step 8: Initialize system protection
502         *      Enable watchdog
503         *      Watchdog causes system reset
504         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
505         *      Enable double bus fault monitor
506         *      Enable bus monitor for external cycles
507         *      1024 clocks for external timeout
508         */
509        m360.sypcr = 0xEC;
510
511        /*
512         * Step 9: Clear parameter RAM and reset communication processor module
513         */
514        for (i = 0 ; i < 192  ; i += sizeof (long)) {
515                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
516                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
517                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
518                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
519        }
520        M360ExecuteRISC (M360_CR_RST);
521
522        /*
523         * Step 10: Write PEPAR
524         *      SINTOUT not used (CPU32+ mode)
525         *      CF1MODE=00 (CONFIG1 input)
526         *      RAS1* double drive
527         *      WE0* - WE3*
528         *      OE* output
529         *      CAS2* - CAS3*
530         *      CAS0* - CAS1*
531         *      CS7*
532         *      AVEC*
533         * HARDWARE:
534         *      Change if you are using a different memory configuration
535         *      (static RAM, external address multiplexing, etc).
536         */
537        m360.pepar = 0x0180;
538
539        /*
540         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
541         *      32-bit DRAM
542         *      Internal DRAM address multiplexing
543         *      60 nsec DRAM
544         *      180 nsec ROM (3 wait states)
545         *      15.36 usec DRAM refresh interval
546         *      The DRAM page size selection is not modified since this
547         *      startup code may be running in a bootstrap PROM or in
548         *      a program downloaded by the bootstrap PROM.
549         */
550        m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
551                                        M360_GMR_RFEN | M360_GMR_RCYC(0) |
552                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
553                                        M360_GMR_GAMX;
554        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
555                                                                M360_MEMC_BR_V;
556        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
557                                                        M360_MEMC_OR_8BIT;
558
559        /*
560         * Step 12: Initialize the system RAM
561         * Do this only if the DRAM has not already been set up
562         */
563        if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
564                /*
565                 * Set up GMR DRAM page size, option and  base registers
566                 *      Assume 16Mbytes of DRAM
567                 *      60 nsec DRAM
568                 */
569                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
570                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
571                                                M360_MEMC_OR_16MB |
572                                                M360_MEMC_OR_DRAM;
573                m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
574
575                /*
576                 * Wait for chips to power up
577                 *      Perform 8 read cycles
578                 */
579                for (i = 0; i < 50000; i++)
580                        continue;
581                for (i = 0; i < 8; ++i)
582                        *((volatile unsigned long *)(unsigned long)&_RamBase);
583
584                /*
585                 * Determine memory size (1, 4, or 16 Mbytes)
586                 * Set GMR DRAM page size appropriately.
587                 * The OR is left at 16 Mbytes.  The bootstrap PROM places its
588                 * .data and .bss segments at the top of the 16 Mbyte space.
589                 * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
590                 * the memory map, but will work with the same bootstrap PROM.
591                 */
592                *(volatile char *)&_RamBase = 0;
593                *((volatile char *)&_RamBase+0x00C01800) = 1;
594                if (*(volatile char *)&_RamBase) {
595                        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
596                }
597                else {
598                        *((volatile char *)&_RamBase+0x00801000) = 1;
599                        if (*(volatile char *)&_RamBase) {
600                                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
601                        }
602                }
603
604                /*
605                 * Enable parity checking
606                 */
607                m360.memc[1].br |= M360_MEMC_BR_PAREN;
608        }
609
610        /*
611         * Step 13: Copy  the exception vector table to system RAM
612         */
613        m68k_get_vbr (vbr);
614        for (i = 0; i < 256; ++i)
615                M68Kvec[i] = vbr[i];
616        m68k_set_vbr (M68Kvec);
617       
618        /*
619         * Step 14: More system initialization
620         * SDCR (Serial DMA configuration register)
621         *      Enable SDMA during FREEZE
622         *      Give SDMA priority over all interrupt handlers
623         *      Set DMA arbiration level to 4
624         * CICR (CPM interrupt configuration register):
625         *      SCC1 requests at SCCa position
626         *      SCC2 requests at SCCb position
627         *      SCC3 requests at SCCc position
628         *      SCC4 requests at SCCd position
629         *      Interrupt request level 4
630         *      Maintain original priority order
631         *      Vector base 128
632         *      SCCs priority grouped at top of table
633         */
634        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
635        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
636                                                (4 << 13) | (0x1F << 8) | (128);
637
638        /*
639         * Step 15: Set module configuration register
640         *      Disable timers during FREEZE
641         *      Enable bus monitor during FREEZE
642         *      BCLRO* arbitration level 3
643         *      No show cycles
644         *      User/supervisor access
645         *      Bus clear interrupt service level 7
646         *      SIM60 interrupt sources higher priority than CPM
647         */
648        m360.mcr = 0x4C7F;
649#endif
650
651        /*
652         * Copy data, clear BSS, switch stacks and call main()
653         */
654        _CopyDataClearBSSAndStart ();
655}
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