1 | /* |
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2 | * MC68360 support routines |
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3 | * |
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4 | * W. Eric Norum |
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5 | * Saskatchewan Accelerator Laboratory |
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6 | * University of Saskatchewan |
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7 | * Saskatoon, Saskatchewan, CANADA |
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8 | * eric@skatter.usask.ca |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | #include <rtems.h> |
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14 | #include <bsp.h> |
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15 | #include <rtems/m68k/m68360.h> |
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16 | |
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17 | |
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18 | /* |
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19 | * Declare the m360 structure here for the benefit of the debugger |
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20 | */ |
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21 | |
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22 | volatile m360_t m360; |
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23 | |
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24 | /* |
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25 | * Send a command to the CPM RISC processer |
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26 | */ |
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27 | |
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28 | void M360ExecuteRISC(uint16_t command) |
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29 | { |
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30 | uint16_t sr; |
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31 | |
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32 | m68k_disable_interrupts (sr); |
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33 | while (m360.cr & M360_CR_FLG) |
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34 | continue; |
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35 | m360.cr = command | M360_CR_FLG; |
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36 | m68k_enable_interrupts (sr); |
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37 | } |
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38 | |
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39 | /* |
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40 | * Initialize MC68360 |
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41 | */ |
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42 | void _Init68360 (void) |
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43 | { |
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44 | int i; |
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45 | m68k_isr_entry *vbr; |
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46 | unsigned long ramSize; |
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47 | extern void _CopyDataClearBSSAndStart (unsigned long ramSize); |
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48 | extern void *RamBase; |
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49 | extern void *_RomBase; /* From linkcmds */ |
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50 | |
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51 | #if (defined (__mc68040__)) |
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52 | /* |
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53 | ******************************************* |
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54 | * Motorola 68040 and companion-mode 68360 * |
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55 | ******************************************* |
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56 | */ |
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57 | |
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58 | /* |
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59 | * Step 6: Is this a power-up reset? |
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60 | * For now we just ignore this and do *all* the steps |
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61 | * Someday we might want to: |
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62 | * if (Hard, Loss of Clock, Power-up) |
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63 | * Do all steps |
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64 | * else if (Double bus fault, watchdog or soft reset) |
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65 | * Skip to step 12 |
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66 | * else (must be a reset command) |
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67 | * Skip to step 14 |
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68 | */ |
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69 | |
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70 | /* |
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71 | * Step 7: Deal with clock synthesizer |
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72 | * HARDWARE: |
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73 | * Change if you're not using an external 25 MHz oscillator. |
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74 | */ |
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75 | m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */ |
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76 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
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77 | no LPSTOP slowdown, PLL X1 */ |
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78 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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79 | |
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80 | /* |
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81 | * Step 8: Initialize system protection |
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82 | * Enable watchdog |
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83 | * Watchdog causes system reset |
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84 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
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85 | * Enable double bus fault monitor |
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86 | * Enable bus monitor for external cycles |
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87 | * 1024 clocks for external timeout |
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88 | */ |
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89 | m360.sypcr = 0xEC; |
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90 | |
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91 | /* |
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92 | * Step 9: Clear parameter RAM and reset communication processor module |
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93 | */ |
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94 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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95 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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96 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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97 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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98 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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99 | } |
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100 | M360ExecuteRISC (M360_CR_RST); |
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101 | |
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102 | /* |
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103 | * Step 10: Write PEPAR |
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104 | * SINTOUT standard M68000 family interrupt level encoding |
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105 | * CF1MODE=10 (BCLRO* output) |
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106 | * No RAS1* double drive |
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107 | * A31 - A28 |
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108 | * AMUX output |
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109 | * CAS2* - CAS3* |
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110 | * CAS0* - CAS1* |
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111 | * CS7* |
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112 | * AVEC* |
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113 | */ |
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114 | m360.pepar = 0x3440; |
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115 | |
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116 | /* |
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117 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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118 | */ |
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119 | /* |
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120 | * 512 addresses per DRAM page (256K DRAM chips) |
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121 | * 70 nsec DRAM |
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122 | * 180 nsec ROM (3 wait states) |
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123 | */ |
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124 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN | |
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125 | M360_GMR_RCYC(0) | M360_GMR_PGS(1) | |
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126 | M360_GMR_DPS_32BIT | M360_GMR_NCS | |
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127 | M360_GMR_TSS40; |
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128 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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129 | M360_MEMC_BR_V; |
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130 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | |
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131 | M360_MEMC_OR_32BIT; |
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132 | |
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133 | /* |
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134 | * Step 12: Initialize the system RAM |
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135 | */ |
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136 | /* |
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137 | * Set up option/base registers |
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138 | * 1M DRAM |
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139 | * 70 nsec DRAM |
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140 | * Enable burst mode |
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141 | * No parity checking |
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142 | * Wait for chips to power up |
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143 | * Perform 8 read cycles |
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144 | */ |
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145 | ramSize = 1 * 1024 * 1024; |
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146 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) | |
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147 | M360_MEMC_OR_1MB | |
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148 | M360_MEMC_OR_DRAM; |
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149 | m360.memc[1].br = (unsigned long)&RamBase | |
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150 | M360_MEMC_BR_BACK40 | |
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151 | M360_MEMC_BR_V; |
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152 | for (i = 0; i < 50000; i++) |
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153 | continue; |
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154 | for (i = 0; i < 8; ++i) |
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155 | *((volatile unsigned long *)(unsigned long)&RamBase); |
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156 | |
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157 | /* |
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158 | * Step 13: Copy the exception vector table to system RAM |
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159 | */ |
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160 | m68k_get_vbr (vbr); |
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161 | for (i = 0; i < 256; ++i) |
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162 | M68Kvec[i] = vbr[i]; |
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163 | m68k_set_vbr (M68Kvec); |
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164 | |
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165 | /* |
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166 | * Step 14: More system initialization |
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167 | * SDCR (Serial DMA configuration register) |
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168 | * Enable SDMA during FREEZE |
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169 | * Give SDMA priority over all interrupt handlers |
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170 | * Set DMA arbiration level to 4 |
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171 | * CICR (CPM interrupt configuration register): |
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172 | * SCC1 requests at SCCa position |
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173 | * SCC2 requests at SCCb position |
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174 | * SCC3 requests at SCCc position |
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175 | * SCC4 requests at SCCd position |
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176 | * Interrupt request level 4 |
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177 | * Maintain original priority order |
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178 | * Vector base 128 |
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179 | * SCCs priority grouped at top of table |
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180 | */ |
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181 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
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182 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
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183 | (4 << 13) | (0x1F << 8) | (128); |
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184 | |
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185 | /* |
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186 | * Step 15: Set module configuration register |
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187 | * Bus request MC68040 Arbitration ID 3 |
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188 | * Bus asynchronous timing mode (work around bug in Rev. B) |
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189 | * Arbitration asynchronous timing mode |
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190 | * Disable timers during FREEZE |
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191 | * Disable bus monitor during FREEZE |
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192 | * BCLRO* arbitration level 3 |
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193 | * No show cycles |
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194 | * User/supervisor access |
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195 | * Bus clear in arbitration ID level 3 |
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196 | * SIM60 interrupt sources higher priority than CPM |
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197 | */ |
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198 | m360.mcr = 0x6000EC3F; |
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199 | |
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200 | #elif (defined (M68360_ATLAS_HSB)) |
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201 | /* |
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202 | ****************************************** |
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203 | * Standalone Motorola 68360 -- ATLAS HSB * |
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204 | ****************************************** |
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205 | */ |
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206 | |
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207 | /* |
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208 | * Step 6: Is this a power-up reset? |
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209 | * For now we just ignore this and do *all* the steps |
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210 | * Someday we might want to: |
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211 | * if (Hard, Loss of Clock, Power-up) |
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212 | * Do all steps |
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213 | * else if (Double bus fault, watchdog or soft reset) |
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214 | * Skip to step 12 |
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215 | * else (must be a CPU32+ reset command) |
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216 | * Skip to step 14 |
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217 | */ |
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218 | |
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219 | /* |
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220 | * Step 7: Deal with clock synthesizer |
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221 | * HARDWARE: |
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222 | * Change if you're not using an external 25 MHz oscillator. |
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223 | */ |
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224 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
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225 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
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226 | no LPSTOP slowdown, PLL X1 */ |
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227 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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228 | |
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229 | /* |
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230 | * Step 8: Initialize system protection |
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231 | * Enable watchdog |
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232 | * Watchdog causes system reset |
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233 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
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234 | * Enable double bus fault monitor |
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235 | * Enable bus monitor for external cycles |
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236 | * 1024 clocks for external timeout |
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237 | */ |
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238 | m360.sypcr = 0xEC; |
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239 | |
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240 | /* |
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241 | * Step 9: Clear parameter RAM and reset communication processor module |
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242 | */ |
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243 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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244 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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245 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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246 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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247 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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248 | } |
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249 | M360ExecuteRISC (M360_CR_RST); |
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250 | |
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251 | /* |
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252 | * Step 10: Write PEPAR |
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253 | * SINTOUT not used (CPU32+ mode) |
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254 | * CF1MODE=00 (CONFIG1 input) |
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255 | * RAS1* double drive |
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256 | * WE0* - WE3* |
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257 | * OE* output |
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258 | * CAS2* - CAS3* |
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259 | * CAS0* - CAS1* |
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260 | * CS7* |
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261 | * AVEC* |
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262 | * HARDWARE: |
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263 | * Change if you are using a different memory configuration |
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264 | * (static RAM, external address multiplexing, etc). |
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265 | */ |
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266 | m360.pepar = 0x0180; |
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267 | |
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268 | /* |
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269 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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270 | */ |
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271 | m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN | |
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272 | M360_GMR_RCYC(0) | M360_GMR_PGS(1) | |
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273 | M360_GMR_DPS_32BIT | M360_GMR_DWQ | |
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274 | M360_GMR_GAMX; |
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275 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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276 | M360_MEMC_BR_V; |
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277 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | |
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278 | M360_MEMC_OR_8BIT; |
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279 | |
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280 | /* |
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281 | * Step 12: Initialize the system RAM |
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282 | */ |
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283 | ramSize = 2 * 1024 * 1024; |
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284 | /* first bank 1MByte DRAM */ |
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285 | m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | |
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286 | M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; |
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287 | m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V; |
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288 | |
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289 | /* second bank 1MByte DRAM */ |
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290 | m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | |
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291 | M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; |
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292 | m360.memc[2].br = ((unsigned long)&RamBase + 0x100000) | |
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293 | M360_MEMC_BR_V; |
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294 | |
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295 | /* flash rom socket U6 on CS5 */ |
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296 | m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP | |
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297 | M360_MEMC_BR_V; |
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298 | m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | |
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299 | M360_MEMC_OR_8BIT; |
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300 | |
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301 | /* CSRs on CS7 */ |
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302 | m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB | |
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303 | M360_MEMC_OR_8BIT; |
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304 | m360.memc[7].br = ATLASHSB_ESR | 0x01; |
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305 | for (i = 0; i < 50000; i++) |
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306 | continue; |
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307 | for (i = 0; i < 8; ++i) |
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308 | *((volatile unsigned long *)(unsigned long)&RamBase); |
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309 | |
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310 | /* |
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311 | * Step 13: Copy the exception vector table to system RAM |
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312 | */ |
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313 | m68k_get_vbr (vbr); |
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314 | for (i = 0; i < 256; ++i) |
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315 | M68Kvec[i] = vbr[i]; |
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316 | m68k_set_vbr (M68Kvec); |
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317 | |
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318 | /* |
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319 | * Step 14: More system initialization |
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320 | * SDCR (Serial DMA configuration register) |
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321 | * Enable SDMA during FREEZE |
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322 | * Give SDMA priority over all interrupt handlers |
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323 | * Set DMA arbiration level to 4 |
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324 | * CICR (CPM interrupt configuration register): |
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325 | * SCC1 requests at SCCa position |
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326 | * SCC2 requests at SCCb position |
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327 | * SCC3 requests at SCCc position |
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328 | * SCC4 requests at SCCd position |
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329 | * Interrupt request level 4 |
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330 | * Maintain original priority order |
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331 | * Vector base 128 |
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332 | * SCCs priority grouped at top of table |
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333 | */ |
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334 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
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335 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
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336 | (4 << 13) | (0x1F << 8) | (128); |
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337 | |
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338 | /* |
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339 | * Step 15: Set module configuration register |
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340 | * Disable timers during FREEZE |
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341 | * Enable bus monitor during FREEZE |
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342 | * BCLRO* arbitration level 3 |
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343 | */ |
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344 | |
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345 | #elif defined(PGH360) |
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346 | /* |
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347 | * Step 6: Is this a power-up reset? |
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348 | * For now we just ignore this and do *all* the steps |
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349 | * Someday we might want to: |
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350 | * if (Hard, Loss of Clock, Power-up) |
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351 | * Do all steps |
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352 | * else if (Double bus fault, watchdog or soft reset) |
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353 | * Skip to step 12 |
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354 | * else (must be a CPU32+ reset command) |
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355 | * Skip to step 14 |
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356 | */ |
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357 | |
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358 | /* |
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359 | * Step 7: Deal with clock synthesizer |
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360 | * HARDWARE: |
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361 | * Change if you're not using an external 25 MHz oscillator. |
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362 | */ |
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363 | m360.clkocr = 0x8e; /* No more writes, CLKO1=1/3, CLKO2=off */ |
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364 | /* |
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365 | * adjust crystal to average between 4.19 MHz and 4.00 MHz |
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366 | * reprogram pll |
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367 | */ |
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368 | m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1; |
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369 | /* LPSTOP slowdown, PLL /128*??? */ |
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370 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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371 | |
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372 | /* |
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373 | * Step 8: Initialize system protection |
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374 | * Enable watchdog |
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375 | * Watchdog causes system reset |
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376 | * 128 sec. watchdog timeout |
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377 | * Enable double bus fault monitor |
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378 | * Enable bus monitor external |
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379 | * 128 clocks for external timeout |
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380 | */ |
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381 | m360.sypcr = 0xEF; |
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382 | /* |
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383 | * also initialize the SWP bit in PITR to 1 |
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384 | */ |
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385 | m360.pitr |= 0x0200; |
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386 | /* |
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387 | * and trigger SWSR twice to ensure, that interval starts right now |
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388 | */ |
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389 | m360.swsr = 0x55; |
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390 | m360.swsr = 0xAA; |
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391 | m360.swsr = 0x55; |
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392 | m360.swsr = 0xAA; |
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393 | /* |
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394 | * Step 9: Clear parameter RAM and reset communication processor module |
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395 | */ |
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396 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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397 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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398 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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399 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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400 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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401 | } |
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402 | M360ExecuteRISC (M360_CR_RST); |
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403 | |
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404 | /* |
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405 | * Step 10: Write PEPAR |
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406 | * SINTOUT not used (CPU32+ mode) |
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407 | * CF1MODE=00 (CONFIG1 input) |
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408 | * IPIPE1 |
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409 | * WE0-3 |
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410 | * OE* output |
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411 | * CAS2* / CAS3* |
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412 | * CAS0* / CAS1* |
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413 | * CS7* |
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414 | * AVEC* |
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415 | * HARDWARE: |
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416 | * Change if you are using a different memory configuration |
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417 | * (static RAM, external address multiplexing, etc). |
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418 | */ |
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419 | m360.pepar = 0x0080; |
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420 | /* |
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421 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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422 | * no DRAM support |
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423 | * HARDWARE: |
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424 | * Change if you are using a different memory configuration |
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425 | */ |
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426 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN | M360_GMR_RCYC(0) | |
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427 | M360_GMR_PGS(6) | M360_GMR_DPS_32BIT | M360_GMR_DWQ | |
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428 | M360_GMR_GAMX; |
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429 | |
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430 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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431 | M360_MEMC_BR_V; |
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432 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB | |
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433 | M360_MEMC_OR_8BIT; |
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434 | |
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435 | /* |
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436 | * Step 12: Initialize the system RAM |
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437 | * Set up option/base registers |
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438 | * 16 MB DRAM |
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439 | * 1 wait state |
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440 | * HARDWARE: |
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441 | * Change if you are using a different memory configuration |
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442 | * NOTE: no Page mode possible for EDO RAMs (?) |
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443 | */ |
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444 | ramSize = 16 * 1024 * 1024; |
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445 | m360.memc[7].or = M360_MEMC_OR_TCYC(1) | M360_MEMC_OR_16MB | |
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446 | M360_MEMC_OR_FCMC(0) | /* M360_MEMC_OR_PGME | */ |
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447 | M360_MEMC_OR_32BIT | M360_MEMC_OR_DRAM; |
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448 | m360.memc[7].br = (unsigned long)&RamBase | M360_MEMC_BR_V; |
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449 | |
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450 | /* |
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451 | * FIXME: here we should wait for 8 refresh cycles... |
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452 | */ |
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453 | /* |
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454 | * Step 12a: test the ram, if wanted |
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455 | * FIXME: when do we call this? |
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456 | * -> only during firmware execution |
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457 | * -> perform intesive test only on request |
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458 | * -> ensure, that results are stored properly |
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459 | */ |
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460 | #if 0 /* FIXME: activate RAM tests again */ |
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461 | { |
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462 | void *ram_base, *ram_end, *code_loc; |
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463 | extern char ramtest_start,ramtest_end; |
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464 | ram_base = &ramtest_start; |
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465 | ram_end = &ramtest_end; |
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466 | code_loc = (void *)ramtest_exec; |
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467 | if ((ram_base < ram_end) && |
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468 | !((ram_base <= code_loc) && (code_loc < ram_end))) { |
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469 | ramtest_exec(ram_base,ram_end); |
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470 | } |
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471 | } |
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472 | #endif |
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473 | /* |
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474 | * Step 13: Copy the exception vector table to system RAM |
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475 | */ |
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476 | m68k_get_vbr (vbr); |
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477 | for (i = 0; i < 256; ++i) |
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478 | M68Kvec[i] = vbr[i]; |
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479 | m68k_set_vbr (M68Kvec); |
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480 | |
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481 | /* |
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482 | * Step 14: More system initialization |
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483 | * SDCR (Serial DMA configuration register) |
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484 | * Disable SDMA during FREEZE |
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485 | * Give SDMA priority over all interrupt handlers |
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486 | * Set DMA arbiration level to 4 |
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487 | * CICR (CPM interrupt configuration register): |
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488 | * SCC1 requests at SCCa position |
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489 | * SCC2 requests at SCCb position |
---|
490 | * SCC3 requests at SCCc position |
---|
491 | * SCC4 requests at SCCd position |
---|
492 | * Interrupt request level 4 |
---|
493 | * Maintain original priority order |
---|
494 | * Vector base 128 |
---|
495 | * SCCs priority grouped at top of table |
---|
496 | */ |
---|
497 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
---|
498 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
---|
499 | (4 << 13) | (0x1F << 8) | (128); |
---|
500 | |
---|
501 | /* |
---|
502 | * Step 15: Set module configuration register |
---|
503 | * Disable timers during FREEZE |
---|
504 | * Enable bus monitor during FREEZE |
---|
505 | * BCLRO* arbitration level 3 |
---|
506 | * No show cycles |
---|
507 | * User/supervisor access |
---|
508 | * Bus clear interupt service level 7 |
---|
509 | * SIM60 interrupt sources higher priority than CPM |
---|
510 | */ |
---|
511 | m360.mcr = 0x4C7F; |
---|
512 | |
---|
513 | #elif (defined (GEN68360_WITH_SRAM)) |
---|
514 | /* |
---|
515 | *************************************************** |
---|
516 | * Generic Standalone Motorola 68360 * |
---|
517 | * As described in MC68360 User's Manual * |
---|
518 | * But uses SRAM instead of DRAM * |
---|
519 | * CS0* - 512kx8 flash memory * |
---|
520 | * CS1* - 512kx32 static RAM * |
---|
521 | * CS2* - 512kx32 static RAM * |
---|
522 | *************************************************** |
---|
523 | */ |
---|
524 | |
---|
525 | /* |
---|
526 | * Step 7: Deal with clock synthesizer |
---|
527 | * HARDWARE: |
---|
528 | * Change if you're not using an external oscillator which |
---|
529 | * oscillates at the system clock rate. |
---|
530 | */ |
---|
531 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
---|
532 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
---|
533 | no LPSTOP slowdown, PLL X1 */ |
---|
534 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
---|
535 | |
---|
536 | /* |
---|
537 | * Step 8: Initialize system protection |
---|
538 | * Enable watchdog |
---|
539 | * Watchdog causes system reset |
---|
540 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
---|
541 | * Enable double bus fault monitor |
---|
542 | * Enable bus monitor for external cycles |
---|
543 | * 1024 clocks for external timeout |
---|
544 | */ |
---|
545 | m360.sypcr = 0xEC; |
---|
546 | |
---|
547 | /* |
---|
548 | * Step 9: Clear parameter RAM and reset communication processor module |
---|
549 | */ |
---|
550 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
---|
551 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
---|
552 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
---|
553 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
---|
554 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
---|
555 | } |
---|
556 | M360ExecuteRISC (M360_CR_RST); |
---|
557 | |
---|
558 | /* |
---|
559 | * Step 10: Write PEPAR |
---|
560 | * SINTOUT not used (CPU32+ mode) |
---|
561 | * CF1MODE=00 (CONFIG1 input) |
---|
562 | * IPIPE1* |
---|
563 | * WE0* - WE3* |
---|
564 | * OE* output |
---|
565 | * CAS2* - CAS3* |
---|
566 | * CAS0* - CAS1* |
---|
567 | * CS7* |
---|
568 | * AVEC* |
---|
569 | * HARDWARE: |
---|
570 | * Change if you are using a different memory configuration |
---|
571 | * (static RAM, external address multiplexing, etc). |
---|
572 | */ |
---|
573 | m360.pepar = 0x0080; |
---|
574 | |
---|
575 | /* |
---|
576 | * Step 11: Set up GMR |
---|
577 | * |
---|
578 | */ |
---|
579 | m360.gmr = 0x0; |
---|
580 | |
---|
581 | /* |
---|
582 | * Step 11a: Remap 512Kx8 flash memory on CS0* |
---|
583 | * 2 wait states |
---|
584 | * Make it read-only for now |
---|
585 | */ |
---|
586 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
---|
587 | M360_MEMC_BR_V; |
---|
588 | m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | |
---|
589 | M360_MEMC_OR_8BIT; |
---|
590 | /* |
---|
591 | * Step 12: Set up main memory |
---|
592 | * 512Kx32 SRAM on CS1* |
---|
593 | * 512Kx32 SRAM on CS2* |
---|
594 | * 0 wait states |
---|
595 | */ |
---|
596 | ramSize = 4 * 1024 * 1024; |
---|
597 | m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V; |
---|
598 | m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | |
---|
599 | M360_MEMC_OR_32BIT; |
---|
600 | m360.memc[2].br = ((unsigned long)&RamBase + 0x200000) | M360_MEMC_BR_V; |
---|
601 | m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | |
---|
602 | M360_MEMC_OR_32BIT; |
---|
603 | /* |
---|
604 | * Step 13: Copy the exception vector table to system RAM |
---|
605 | */ |
---|
606 | m68k_get_vbr (vbr); |
---|
607 | for (i = 0; i < 256; ++i) |
---|
608 | M68Kvec[i] = vbr[i]; |
---|
609 | m68k_set_vbr (M68Kvec); |
---|
610 | |
---|
611 | /* |
---|
612 | * Step 14: More system initialization |
---|
613 | * SDCR (Serial DMA configuration register) |
---|
614 | * Enable SDMA during FREEZE |
---|
615 | * Give SDMA priority over all interrupt handlers |
---|
616 | * Set DMA arbiration level to 4 |
---|
617 | * CICR (CPM interrupt configuration register): |
---|
618 | * SCC1 requests at SCCa position |
---|
619 | * SCC2 requests at SCCb position |
---|
620 | * SCC3 requests at SCCc position |
---|
621 | * SCC4 requests at SCCd position |
---|
622 | * Interrupt request level 4 |
---|
623 | * Maintain original priority order |
---|
624 | * Vector base 128 |
---|
625 | * SCCs priority grouped at top of table |
---|
626 | */ |
---|
627 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
---|
628 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
---|
629 | (4 << 13) | (0x1F << 8) | (128); |
---|
630 | |
---|
631 | /* |
---|
632 | * Step 15: Set module configuration register |
---|
633 | * Disable timers during FREEZE |
---|
634 | * Enable bus monitor during FREEZE |
---|
635 | * BCLRO* arbitration level 3 |
---|
636 | * No show cycles |
---|
637 | * User/supervisor access |
---|
638 | * Bus clear interrupt service level 7 |
---|
639 | * SIM60 interrupt sources higher priority than CPM |
---|
640 | */ |
---|
641 | m360.mcr = 0x4C7F; |
---|
642 | |
---|
643 | #else |
---|
644 | /* |
---|
645 | *************************************************** |
---|
646 | * Generic Standalone Motorola 68360 * |
---|
647 | * As described in MC68360 User's Manual * |
---|
648 | * Atlas ACE360 * |
---|
649 | *************************************************** |
---|
650 | */ |
---|
651 | |
---|
652 | /* |
---|
653 | * Step 6: Is this a power-up reset? |
---|
654 | * For now we just ignore this and do *all* the steps |
---|
655 | * Someday we might want to: |
---|
656 | * if (Hard, Loss of Clock, Power-up) |
---|
657 | * Do all steps |
---|
658 | * else if (Double bus fault, watchdog or soft reset) |
---|
659 | * Skip to step 12 |
---|
660 | * else (must be a CPU32+ reset command) |
---|
661 | * Skip to step 14 |
---|
662 | */ |
---|
663 | |
---|
664 | /* |
---|
665 | * Step 7: Deal with clock synthesizer |
---|
666 | * HARDWARE: |
---|
667 | * Change if you're not using an external 25 MHz oscillator. |
---|
668 | */ |
---|
669 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
---|
670 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
---|
671 | no LPSTOP slowdown, PLL X1 */ |
---|
672 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
---|
673 | |
---|
674 | /* |
---|
675 | * Step 8: Initialize system protection |
---|
676 | * Enable watchdog |
---|
677 | * Watchdog causes system reset |
---|
678 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
---|
679 | * Enable double bus fault monitor |
---|
680 | * Enable bus monitor for external cycles |
---|
681 | * 1024 clocks for external timeout |
---|
682 | */ |
---|
683 | m360.sypcr = 0xEC; |
---|
684 | |
---|
685 | /* |
---|
686 | * Step 9: Clear parameter RAM and reset communication processor module |
---|
687 | */ |
---|
688 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
---|
689 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
---|
690 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
---|
691 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
---|
692 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
---|
693 | } |
---|
694 | M360ExecuteRISC (M360_CR_RST); |
---|
695 | |
---|
696 | /* |
---|
697 | * Step 10: Write PEPAR |
---|
698 | * SINTOUT not used (CPU32+ mode) |
---|
699 | * CF1MODE=00 (CONFIG1 input) |
---|
700 | * RAS1* double drive |
---|
701 | * WE0* - WE3* |
---|
702 | * OE* output |
---|
703 | * CAS2* - CAS3* |
---|
704 | * CAS0* - CAS1* |
---|
705 | * CS7* |
---|
706 | * AVEC* |
---|
707 | * HARDWARE: |
---|
708 | * Change if you are using a different memory configuration |
---|
709 | * (static RAM, external address multiplexing, etc). |
---|
710 | */ |
---|
711 | m360.pepar = 0x0180; |
---|
712 | |
---|
713 | /* |
---|
714 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
---|
715 | * 32-bit DRAM |
---|
716 | * Internal DRAM address multiplexing |
---|
717 | * 60 nsec DRAM |
---|
718 | * 180 nsec ROM (3 wait states) |
---|
719 | * 15.36 usec DRAM refresh interval |
---|
720 | * The DRAM page size selection is not modified since this |
---|
721 | * startup code may be running in a bootstrap PROM or in |
---|
722 | * a program downloaded by the bootstrap PROM. |
---|
723 | */ |
---|
724 | m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) | |
---|
725 | M360_GMR_RFEN | M360_GMR_RCYC(0) | |
---|
726 | M360_GMR_DPS_32BIT | M360_GMR_NCS | |
---|
727 | M360_GMR_GAMX; |
---|
728 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
---|
729 | M360_MEMC_BR_V; |
---|
730 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | |
---|
731 | M360_MEMC_OR_8BIT; |
---|
732 | |
---|
733 | /* |
---|
734 | * Step 12: Initialize the system RAM |
---|
735 | * Do this only if the DRAM has not already been set up |
---|
736 | */ |
---|
737 | if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) { |
---|
738 | /* |
---|
739 | * Set up GMR DRAM page size, option and base registers |
---|
740 | * Assume 16Mbytes of DRAM |
---|
741 | * 60 nsec DRAM |
---|
742 | */ |
---|
743 | m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5); |
---|
744 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) | |
---|
745 | M360_MEMC_OR_16MB | |
---|
746 | M360_MEMC_OR_DRAM; |
---|
747 | m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V; |
---|
748 | |
---|
749 | /* |
---|
750 | * Wait for chips to power up |
---|
751 | * Perform 8 read cycles |
---|
752 | */ |
---|
753 | for (i = 0; i < 50000; i++) |
---|
754 | continue; |
---|
755 | for (i = 0; i < 8; ++i) |
---|
756 | *((volatile unsigned long *)(unsigned long)&RamBase); |
---|
757 | |
---|
758 | /* |
---|
759 | * Determine memory size (1, 4, or 16 Mbytes) |
---|
760 | * Set GMR DRAM page size appropriately. |
---|
761 | * The OR is left at 16 Mbytes. The bootstrap PROM places its |
---|
762 | * .data and .bss segments at the top of the 16 Mbyte space. |
---|
763 | * A 1 Mbyte or 4 Mbyte DRAM will show up several times in |
---|
764 | * the memory map, but will work with the same bootstrap PROM. |
---|
765 | */ |
---|
766 | *(volatile char *)&RamBase = 0; |
---|
767 | *((volatile char *)&RamBase+0x00C01800) = 1; |
---|
768 | if (*(volatile char *)&RamBase) { |
---|
769 | m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1); |
---|
770 | } |
---|
771 | else { |
---|
772 | *((volatile char *)&RamBase+0x00801000) = 1; |
---|
773 | if (*(volatile char *)&RamBase) { |
---|
774 | m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3); |
---|
775 | } |
---|
776 | } |
---|
777 | |
---|
778 | /* |
---|
779 | * Enable parity checking |
---|
780 | */ |
---|
781 | m360.memc[1].br |= M360_MEMC_BR_PAREN; |
---|
782 | } |
---|
783 | switch (m360.gmr & 0x001C0000) { |
---|
784 | default: ramSize = 4 * 1024 * 1024; break; |
---|
785 | case M360_GMR_PGS(1): ramSize = 1 * 1024 * 1024; break; |
---|
786 | case M360_GMR_PGS(3): ramSize = 4 * 1024 * 1024; break; |
---|
787 | case M360_GMR_PGS(5): ramSize = 16 * 1024 * 1024; break; |
---|
788 | } |
---|
789 | |
---|
790 | /* |
---|
791 | * Step 13: Copy the exception vector table to system RAM |
---|
792 | */ |
---|
793 | m68k_get_vbr (vbr); |
---|
794 | for (i = 0; i < 256; ++i) |
---|
795 | M68Kvec[i] = vbr[i]; |
---|
796 | m68k_set_vbr (M68Kvec); |
---|
797 | |
---|
798 | /* |
---|
799 | * Step 14: More system initialization |
---|
800 | * SDCR (Serial DMA configuration register) |
---|
801 | * Enable SDMA during FREEZE |
---|
802 | * Give SDMA priority over all interrupt handlers |
---|
803 | * Set DMA arbiration level to 4 |
---|
804 | * CICR (CPM interrupt configuration register): |
---|
805 | * SCC1 requests at SCCa position |
---|
806 | * SCC2 requests at SCCb position |
---|
807 | * SCC3 requests at SCCc position |
---|
808 | * SCC4 requests at SCCd position |
---|
809 | * Interrupt request level 4 |
---|
810 | * Maintain original priority order |
---|
811 | * Vector base 128 |
---|
812 | * SCCs priority grouped at top of table |
---|
813 | */ |
---|
814 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
---|
815 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
---|
816 | (4 << 13) | (0x1F << 8) | (128); |
---|
817 | |
---|
818 | /* |
---|
819 | * Step 15: Set module configuration register |
---|
820 | * Disable timers during FREEZE |
---|
821 | * Enable bus monitor during FREEZE |
---|
822 | * BCLRO* arbitration level 3 |
---|
823 | * No show cycles |
---|
824 | * User/supervisor access |
---|
825 | * Bus clear interrupt service level 7 |
---|
826 | * SIM60 interrupt sources higher priority than CPM |
---|
827 | */ |
---|
828 | m360.mcr = 0x4C7F; |
---|
829 | #endif |
---|
830 | |
---|
831 | /* |
---|
832 | * Copy data, clear BSS, switch stacks and call main() |
---|
833 | * Must pass ramSize as argument since the data/bss segment |
---|
834 | * may be overwritten. |
---|
835 | */ |
---|
836 | _CopyDataClearBSSAndStart (ramSize); |
---|
837 | } |
---|