source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ 53cb8234

4.104.115
Last change on this file since 53cb8234 was 53cb8234, checked in by Joel Sherrill <joel.sherrill@…>, on 09/16/08 at 22:15:59

2008-09-16 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, include/bsp.h, startup/init68360.c, startup/linkcmds, startup/linkcmds.bootp, startup/linkcmds.prom: Use top level shared bsp_get_work_area() implementation.
  • Property mode set to 100644
File size: 23.5 KB
Line 
1/*
2 * MC68360 support routines
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
15#include <rtems/m68k/m68360.h>
16
17
18/*
19 * Declare the m360 structure here for the benefit of the debugger
20 */
21
22volatile m360_t m360;
23
24/*
25 * Send a command to the CPM RISC processer
26 */
27
28void M360ExecuteRISC(uint16_t         command)
29{
30        uint16_t         sr;
31
32        m68k_disable_interrupts (sr);
33        while (m360.cr & M360_CR_FLG)
34                continue;
35        m360.cr = command | M360_CR_FLG;
36        m68k_enable_interrupts (sr);
37}
38
39/*
40 * Initialize MC68360
41 */
42void _Init68360 (void)
43{
44        int i;
45        m68k_isr_entry *vbr;
46        unsigned long ramSize;
47        extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
48        extern void *RamBase;
49        extern void *_RomBase;  /* From linkcmds */
50
51#if (defined (__mc68040__))
52        /*
53         *******************************************
54         * Motorola 68040 and companion-mode 68360 *
55         *******************************************
56         */
57
58        /*
59         * Step 6: Is this a power-up reset?
60         * For now we just ignore this and do *all* the steps
61         * Someday we might want to:
62         *      if (Hard, Loss of Clock, Power-up)
63         *              Do all steps
64         *      else if (Double bus fault, watchdog or soft reset)
65         *              Skip to step 12
66         *      else (must be a reset command)
67         *              Skip to step 14
68         */
69
70        /*
71         * Step 7: Deal with clock synthesizer
72         * HARDWARE:
73         *      Change if you're not using an external 25 MHz oscillator.
74         */
75        m360.clkocr = 0x83;     /* No more writes, full-power CLKO2 */
76        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
77                                   no LPSTOP slowdown, PLL X1 */
78        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
79
80        /*
81         * Step 8: Initialize system protection
82         *      Enable watchdog
83         *      Watchdog causes system reset
84         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
85         *      Enable double bus fault monitor
86         *      Enable bus monitor for external cycles
87         *      1024 clocks for external timeout
88         */
89        m360.sypcr = 0xEC;
90
91        /*
92         * Step 9: Clear parameter RAM and reset communication processor module
93         */
94        for (i = 0 ; i < 192  ; i += sizeof (long)) {
95                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
96                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
97                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
98                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
99        }
100        M360ExecuteRISC (M360_CR_RST);
101
102        /*
103         * Step 10: Write PEPAR
104         *      SINTOUT standard M68000 family interrupt level encoding
105         *      CF1MODE=10 (BCLRO* output)
106         *      No RAS1* double drive
107         *      A31 - A28
108         *      AMUX output
109         *      CAS2* - CAS3*
110         *      CAS0* - CAS1*
111         *      CS7*
112         *      AVEC*
113         */
114        m360.pepar = 0x3440;
115
116        /*
117         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
118         */
119        /*
120         * 512 addresses per DRAM page (256K DRAM chips)
121         * 70 nsec DRAM
122         * 180 nsec ROM (3 wait states)
123         */
124        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
125                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
126                                M360_GMR_DPS_32BIT | M360_GMR_NCS |
127                                M360_GMR_TSS40;
128        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
129                                                        M360_MEMC_BR_V;
130        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
131                                                M360_MEMC_OR_32BIT;
132
133        /*
134         * Step 12: Initialize the system RAM
135         */
136        /*
137         *      Set up option/base registers
138         *              1M DRAM
139         *              70 nsec DRAM
140         *      Enable burst mode
141         *      No parity checking
142         *      Wait for chips to power up
143         *      Perform 8 read cycles
144         */
145        ramSize = 1 * 1024 * 1024;
146        m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
147                                        M360_MEMC_OR_1MB |
148                                        M360_MEMC_OR_DRAM;
149        m360.memc[1].br = (unsigned long)&RamBase |
150                                        M360_MEMC_BR_BACK40 |
151                                        M360_MEMC_BR_V;
152        for (i = 0; i < 50000; i++)
153                continue;
154        for (i = 0; i < 8; ++i)
155                *((volatile unsigned long *)(unsigned long)&RamBase);
156
157        /*
158         * Step 13: Copy  the exception vector table to system RAM
159         */
160        m68k_get_vbr (vbr);
161        for (i = 0; i < 256; ++i)
162                M68Kvec[i] = vbr[i];
163        m68k_set_vbr (M68Kvec);
164
165        /*
166         * Step 14: More system initialization
167         * SDCR (Serial DMA configuration register)
168         *      Enable SDMA during FREEZE
169         *      Give SDMA priority over all interrupt handlers
170         *      Set DMA arbiration level to 4
171         * CICR (CPM interrupt configuration register):
172         *      SCC1 requests at SCCa position
173         *      SCC2 requests at SCCb position
174         *      SCC3 requests at SCCc position
175         *      SCC4 requests at SCCd position
176         *      Interrupt request level 4
177         *      Maintain original priority order
178         *      Vector base 128
179         *      SCCs priority grouped at top of table
180         */
181        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
182        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
183                                                (4 << 13) | (0x1F << 8) | (128);
184
185        /*
186         * Step 15: Set module configuration register
187         *      Bus request MC68040 Arbitration ID 3
188         *      Bus asynchronous timing mode (work around bug in Rev. B)
189         *      Arbitration asynchronous timing mode
190         *      Disable timers during FREEZE
191         *      Disable bus monitor during FREEZE
192         *      BCLRO* arbitration level 3
193         *      No show cycles
194         *      User/supervisor access
195         *      Bus clear in arbitration ID level  3
196         *      SIM60 interrupt sources higher priority than CPM
197         */
198        m360.mcr = 0x6000EC3F;
199
200#elif (defined (M68360_ATLAS_HSB))
201        /*
202         ******************************************
203         * Standalone Motorola 68360 -- ATLAS HSB *
204         ******************************************
205         */
206
207        /*
208         * Step 6: Is this a power-up reset?
209         * For now we just ignore this and do *all* the steps
210         * Someday we might want to:
211         *      if (Hard, Loss of Clock, Power-up)
212         *              Do all steps
213         *      else if (Double bus fault, watchdog or soft reset)
214         *              Skip to step 12
215         *      else (must be a CPU32+ reset command)
216         *              Skip to step 14
217         */
218
219        /*
220         * Step 7: Deal with clock synthesizer
221         * HARDWARE:
222         *      Change if you're not using an external 25 MHz oscillator.
223         */
224        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
225        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
226                                   no LPSTOP slowdown, PLL X1 */
227        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
228
229        /*
230         * Step 8: Initialize system protection
231         *      Enable watchdog
232         *      Watchdog causes system reset
233         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
234         *      Enable double bus fault monitor
235         *      Enable bus monitor for external cycles
236         *      1024 clocks for external timeout
237         */
238        m360.sypcr = 0xEC;
239
240        /*
241         * Step 9: Clear parameter RAM and reset communication processor module
242         */
243        for (i = 0 ; i < 192  ; i += sizeof (long)) {
244                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
245                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
246                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
247                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
248        }
249        M360ExecuteRISC (M360_CR_RST);
250
251        /*
252         * Step 10: Write PEPAR
253         *      SINTOUT not used (CPU32+ mode)
254         *      CF1MODE=00 (CONFIG1 input)
255         *      RAS1* double drive
256         *      WE0* - WE3*
257         *      OE* output
258         *      CAS2* - CAS3*
259         *      CAS0* - CAS1*
260         *      CS7*
261         *      AVEC*
262         * HARDWARE:
263         *      Change if you are using a different memory configuration
264         *      (static RAM, external address multiplexing, etc).
265         */
266        m360.pepar = 0x0180;
267
268        /*
269         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
270         */
271        m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
272                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
273                                M360_GMR_DPS_32BIT | M360_GMR_DWQ |
274                                M360_GMR_GAMX;
275        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
276                                                                M360_MEMC_BR_V;
277        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
278                                                        M360_MEMC_OR_8BIT;
279
280        /*
281         * Step 12: Initialize the system RAM
282         */
283        ramSize = 2 * 1024 * 1024;
284        /* first bank 1MByte DRAM */
285        m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
286                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
287        m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
288
289        /* second bank 1MByte DRAM */
290        m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
291                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
292        m360.memc[2].br = ((unsigned long)&RamBase + 0x100000) |
293                                        M360_MEMC_BR_V;
294
295        /* flash rom socket U6 on CS5 */
296        m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
297                                                                M360_MEMC_BR_V;
298        m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
299                                                                M360_MEMC_OR_8BIT;
300
301        /* CSRs on CS7 */
302        m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
303                                        M360_MEMC_OR_8BIT;
304        m360.memc[7].br = ATLASHSB_ESR | 0x01;
305        for (i = 0; i < 50000; i++)
306                continue;
307        for (i = 0; i < 8; ++i)
308                *((volatile unsigned long *)(unsigned long)&RamBase);
309
310        /*
311         * Step 13: Copy  the exception vector table to system RAM
312         */
313        m68k_get_vbr (vbr);
314        for (i = 0; i < 256; ++i)
315                M68Kvec[i] = vbr[i];
316        m68k_set_vbr (M68Kvec);
317
318        /*
319         * Step 14: More system initialization
320         * SDCR (Serial DMA configuration register)
321         *      Enable SDMA during FREEZE
322         *      Give SDMA priority over all interrupt handlers
323         *      Set DMA arbiration level to 4
324         * CICR (CPM interrupt configuration register):
325         *      SCC1 requests at SCCa position
326         *      SCC2 requests at SCCb position
327         *      SCC3 requests at SCCc position
328         *      SCC4 requests at SCCd position
329         *      Interrupt request level 4
330         *      Maintain original priority order
331         *      Vector base 128
332         *      SCCs priority grouped at top of table
333         */
334        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
335        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
336                                                (4 << 13) | (0x1F << 8) | (128);
337
338        /*
339         * Step 15: Set module configuration register
340         *      Disable timers during FREEZE
341         *      Enable bus monitor during FREEZE
342         *      BCLRO* arbitration level 3
343         */
344
345#elif defined(PGH360)
346        /*
347         * Step 6: Is this a power-up reset?
348         * For now we just ignore this and do *all* the steps
349         * Someday we might want to:
350         *      if (Hard, Loss of Clock, Power-up)
351         *              Do all steps
352         *      else if (Double bus fault, watchdog or soft reset)
353         *              Skip to step 12
354         *      else (must be a CPU32+ reset command)
355         *              Skip to step 14
356         */
357
358        /*
359         * Step 7: Deal with clock synthesizer
360         * HARDWARE:
361         *      Change if you're not using an external 25 MHz oscillator.
362         */
363        m360.clkocr = 0x8e;     /* No more writes, CLKO1=1/3, CLKO2=off */
364        /*
365         * adjust crystal to average between 4.19 MHz and 4.00 MHz
366         * reprogram pll
367         */
368        m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
369                                        /* LPSTOP slowdown, PLL /128*??? */
370        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
371
372        /*
373         * Step 8: Initialize system protection
374         *      Enable watchdog
375         *      Watchdog causes system reset
376         *      128 sec. watchdog timeout
377         *      Enable double bus fault monitor
378         *      Enable bus monitor external
379         *      128 clocks for external timeout
380         */
381        m360.sypcr = 0xEF;
382        /*
383         * also initialize the SWP bit in PITR to 1
384         */
385        m360.pitr |= 0x0200;
386        /*
387         * and trigger SWSR twice to ensure, that interval starts right now
388         */
389        m360.swsr = 0x55;
390        m360.swsr = 0xAA;
391        m360.swsr = 0x55;
392        m360.swsr = 0xAA;
393        /*
394         * Step 9: Clear parameter RAM and reset communication processor module
395         */
396        for (i = 0 ; i < 192  ; i += sizeof (long)) {
397                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
398                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
399                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
400                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
401        }
402        M360ExecuteRISC (M360_CR_RST);
403
404        /*
405         * Step 10: Write PEPAR
406         *      SINTOUT not used (CPU32+ mode)
407         *      CF1MODE=00 (CONFIG1 input)
408         *      IPIPE1
409         *      WE0-3
410         *      OE* output
411         *      CAS2* / CAS3*
412         *      CAS0* / CAS1*
413         *      CS7*
414         *      AVEC*
415         * HARDWARE:
416         *      Change if you are using a different memory configuration
417         *      (static RAM, external address multiplexing, etc).
418         */
419        m360.pepar = 0x0080;
420        /*
421         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
422         *      no DRAM support
423         * HARDWARE:
424         *      Change if you are using a different memory configuration
425         */
426        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN      | M360_GMR_RCYC(0) |
427                   M360_GMR_PGS(6)   | M360_GMR_DPS_32BIT | M360_GMR_DWQ     |
428                   M360_GMR_GAMX;
429
430        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
431                                                        M360_MEMC_BR_V;
432        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
433                                                        M360_MEMC_OR_8BIT;
434
435        /*
436         * Step 12: Initialize the system RAM
437         *      Set up option/base registers
438         *              16 MB DRAM
439         *              1 wait state
440         * HARDWARE:
441         *      Change if you are using a different memory configuration
442         *      NOTE: no Page mode possible for EDO RAMs (?)
443         */
444        ramSize = 16 * 1024 * 1024;
445        m360.memc[7].or = M360_MEMC_OR_TCYC(1)  | M360_MEMC_OR_16MB |
446                          M360_MEMC_OR_FCMC(0)  | /* M360_MEMC_OR_PGME | */
447                          M360_MEMC_OR_32BIT    | M360_MEMC_OR_DRAM;
448        m360.memc[7].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
449
450        /*
451         * FIXME: here we should wait for 8 refresh cycles...
452         */
453        /*
454         * Step 12a: test the ram, if wanted
455         * FIXME: when do we call this?
456         * -> only during firmware execution
457         * -> perform intesive test only on request
458         * -> ensure, that results are stored properly
459         */
460#if 0 /* FIXME: activate RAM tests again */
461        {
462          void *ram_base, *ram_end, *code_loc;
463          extern char ramtest_start,ramtest_end;
464          ram_base = &ramtest_start;
465          ram_end  = &ramtest_end;
466          code_loc = (void *)ramtest_exec;
467          if ((ram_base < ram_end) &&
468            !((ram_base <= code_loc) && (code_loc < ram_end))) {           
469            ramtest_exec(ram_base,ram_end);
470          }
471        }
472#endif
473        /*
474         * Step 13: Copy  the exception vector table to system RAM
475         */
476        m68k_get_vbr (vbr);
477        for (i = 0; i < 256; ++i)
478                M68Kvec[i] = vbr[i];
479        m68k_set_vbr (M68Kvec);
480       
481        /*
482         * Step 14: More system initialization
483         * SDCR (Serial DMA configuration register)
484         *      Disable SDMA during FREEZE
485         *      Give SDMA priority over all interrupt handlers
486         *      Set DMA arbiration level to 4
487         * CICR (CPM interrupt configuration register):
488         *      SCC1 requests at SCCa position
489         *      SCC2 requests at SCCb position
490         *      SCC3 requests at SCCc position
491         *      SCC4 requests at SCCd position
492         *      Interrupt request level 4
493         *      Maintain original priority order
494         *      Vector base 128
495         *      SCCs priority grouped at top of table
496         */
497        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
498        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
499                                                (4 << 13) | (0x1F << 8) | (128);
500
501        /*
502         * Step 15: Set module configuration register
503         *      Disable timers during FREEZE
504         *      Enable bus monitor during FREEZE
505         *      BCLRO* arbitration level 3
506         *      No show cycles
507         *      User/supervisor access
508         *      Bus clear interupt service level 7
509         *      SIM60 interrupt sources higher priority than CPM
510         */
511        m360.mcr = 0x4C7F;
512
513#elif (defined (GEN68360_WITH_SRAM))
514   /*
515    ***************************************************
516    * Generic Standalone Motorola 68360               *
517    *           As described in MC68360 User's Manual *
518    * But uses SRAM instead of DRAM                   *
519    *  CS0* - 512kx8 flash memory                     *
520    *  CS1* - 512kx32 static RAM                      *
521    *  CS2* - 512kx32 static RAM                      *
522    ***************************************************
523    */
524
525   /*
526    * Step 7: Deal with clock synthesizer
527    * HARDWARE:
528    * Change if you're not using an external oscillator which
529    * oscillates at the system clock rate.
530    */
531   m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
532   m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
533                              no LPSTOP slowdown, PLL X1 */
534   m360.cdvcr = 0x8000;    /* No more writes, no clock division */
535
536   /*
537    * Step 8: Initialize system protection
538    * Enable watchdog
539    * Watchdog causes system reset
540    * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
541    * Enable double bus fault monitor
542    * Enable bus monitor for external cycles
543    * 1024 clocks for external timeout
544    */
545    m360.sypcr = 0xEC;
546
547   /*
548    * Step 9: Clear parameter RAM and reset communication processor module
549    */
550   for (i = 0 ; i < 192  ; i += sizeof (long)) {
551      *((long *)((char *)&m360 + 0xC00 + i)) = 0;
552      *((long *)((char *)&m360 + 0xD00 + i)) = 0;
553      *((long *)((char *)&m360 + 0xE00 + i)) = 0;
554      *((long *)((char *)&m360 + 0xF00 + i)) = 0;
555   }
556   M360ExecuteRISC (M360_CR_RST);
557
558   /*
559    * Step 10: Write PEPAR
560    * SINTOUT not used (CPU32+ mode)
561    * CF1MODE=00 (CONFIG1 input)
562    * IPIPE1*
563    * WE0* - WE3*
564    * OE* output
565    * CAS2* - CAS3*
566    * CAS0* - CAS1*
567    * CS7*
568    * AVEC*
569    * HARDWARE:
570    * Change if you are using a different memory configuration
571    * (static RAM, external address multiplexing, etc).
572    */
573   m360.pepar = 0x0080;
574
575   /*
576    * Step 11: Set up GMR
577    *
578    */
579   m360.gmr = 0x0;
580
581   /*
582    * Step 11a: Remap 512Kx8 flash memory on CS0*
583    * 2 wait states
584    * Make it read-only for now
585    */
586   m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
587                                                   M360_MEMC_BR_V;
588   m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
589                                                   M360_MEMC_OR_8BIT;
590   /*
591    * Step 12: Set up main memory
592    * 512Kx32 SRAM on CS1*
593    * 512Kx32 SRAM on CS2*
594    * 0 wait states
595    */
596   ramSize = 4 * 1024 * 1024;
597   m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
598   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
599                                                   M360_MEMC_OR_32BIT;
600   m360.memc[2].br = ((unsigned long)&RamBase + 0x200000) | M360_MEMC_BR_V;
601   m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
602                                                   M360_MEMC_OR_32BIT;
603   /*
604    * Step 13: Copy  the exception vector table to system RAM
605    */
606   m68k_get_vbr (vbr);
607   for (i = 0; i < 256; ++i)
608           M68Kvec[i] = vbr[i];
609   m68k_set_vbr (M68Kvec);
610
611   /*
612    * Step 14: More system initialization
613    * SDCR (Serial DMA configuration register)
614    * Enable SDMA during FREEZE
615    * Give SDMA priority over all interrupt handlers
616    * Set DMA arbiration level to 4
617    * CICR (CPM interrupt configuration register):
618    * SCC1 requests at SCCa position
619    * SCC2 requests at SCCb position
620    * SCC3 requests at SCCc position
621    * SCC4 requests at SCCd position
622    * Interrupt request level 4
623    * Maintain original priority order
624    * Vector base 128
625    * SCCs priority grouped at top of table
626    */
627   m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
628   m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
629                  (4 << 13) | (0x1F << 8) | (128);
630
631   /*
632    * Step 15: Set module configuration register
633    * Disable timers during FREEZE
634    * Enable bus monitor during FREEZE
635    * BCLRO* arbitration level 3
636    * No show cycles
637    * User/supervisor access
638    * Bus clear interrupt service level 7
639    * SIM60 interrupt sources higher priority than CPM
640    */
641   m360.mcr = 0x4C7F;
642
643#else
644        /*
645         ***************************************************
646         * Generic Standalone Motorola 68360               *
647         *           As described in MC68360 User's Manual *
648         *           Atlas ACE360                          *
649         ***************************************************
650         */
651
652        /*
653         * Step 6: Is this a power-up reset?
654         * For now we just ignore this and do *all* the steps
655         * Someday we might want to:
656         *      if (Hard, Loss of Clock, Power-up)
657         *              Do all steps
658         *      else if (Double bus fault, watchdog or soft reset)
659         *              Skip to step 12
660         *      else (must be a CPU32+ reset command)
661         *              Skip to step 14
662         */
663
664        /*
665         * Step 7: Deal with clock synthesizer
666         * HARDWARE:
667         *      Change if you're not using an external 25 MHz oscillator.
668         */
669        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
670        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
671                                   no LPSTOP slowdown, PLL X1 */
672        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
673
674        /*
675         * Step 8: Initialize system protection
676         *      Enable watchdog
677         *      Watchdog causes system reset
678         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
679         *      Enable double bus fault monitor
680         *      Enable bus monitor for external cycles
681         *      1024 clocks for external timeout
682         */
683        m360.sypcr = 0xEC;
684
685        /*
686         * Step 9: Clear parameter RAM and reset communication processor module
687         */
688        for (i = 0 ; i < 192  ; i += sizeof (long)) {
689                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
690                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
691                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
692                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
693        }
694        M360ExecuteRISC (M360_CR_RST);
695
696        /*
697         * Step 10: Write PEPAR
698         *      SINTOUT not used (CPU32+ mode)
699         *      CF1MODE=00 (CONFIG1 input)
700         *      RAS1* double drive
701         *      WE0* - WE3*
702         *      OE* output
703         *      CAS2* - CAS3*
704         *      CAS0* - CAS1*
705         *      CS7*
706         *      AVEC*
707         * HARDWARE:
708         *      Change if you are using a different memory configuration
709         *      (static RAM, external address multiplexing, etc).
710         */
711        m360.pepar = 0x0180;
712
713        /*
714         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
715         *      32-bit DRAM
716         *      Internal DRAM address multiplexing
717         *      60 nsec DRAM
718         *      180 nsec ROM (3 wait states)
719         *      15.36 usec DRAM refresh interval
720         *      The DRAM page size selection is not modified since this
721         *      startup code may be running in a bootstrap PROM or in
722         *      a program downloaded by the bootstrap PROM.
723         */
724        m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
725                                        M360_GMR_RFEN | M360_GMR_RCYC(0) |
726                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
727                                        M360_GMR_GAMX;
728        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
729                                                                M360_MEMC_BR_V;
730        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
731                                                        M360_MEMC_OR_8BIT;
732
733        /*
734         * Step 12: Initialize the system RAM
735         * Do this only if the DRAM has not already been set up
736         */
737        if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
738                /*
739                 * Set up GMR DRAM page size, option and  base registers
740                 *      Assume 16Mbytes of DRAM
741                 *      60 nsec DRAM
742                 */
743                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
744                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
745                                                M360_MEMC_OR_16MB |
746                                                M360_MEMC_OR_DRAM;
747                m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
748
749                /*
750                 * Wait for chips to power up
751                 *      Perform 8 read cycles
752                 */
753                for (i = 0; i < 50000; i++)
754                        continue;
755                for (i = 0; i < 8; ++i)
756                        *((volatile unsigned long *)(unsigned long)&RamBase);
757
758                /*
759                 * Determine memory size (1, 4, or 16 Mbytes)
760                 * Set GMR DRAM page size appropriately.
761                 * The OR is left at 16 Mbytes.  The bootstrap PROM places its
762                 * .data and .bss segments at the top of the 16 Mbyte space.
763                 * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
764                 * the memory map, but will work with the same bootstrap PROM.
765                 */
766                *(volatile char *)&RamBase = 0;
767                *((volatile char *)&RamBase+0x00C01800) = 1;
768                if (*(volatile char *)&RamBase) {
769                        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
770                }
771                else {
772                        *((volatile char *)&RamBase+0x00801000) = 1;
773                        if (*(volatile char *)&RamBase) {
774                                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
775                        }
776                }
777
778                /*
779                 * Enable parity checking
780                 */
781                m360.memc[1].br |= M360_MEMC_BR_PAREN;
782        }
783        switch (m360.gmr & 0x001C0000) {
784        default:                ramSize =  4 * 1024 * 1024;     break;
785        case M360_GMR_PGS(1):   ramSize =  1 * 1024 * 1024;     break;
786        case M360_GMR_PGS(3):   ramSize =  4 * 1024 * 1024;     break;
787        case M360_GMR_PGS(5):   ramSize = 16 * 1024 * 1024;     break;
788        }
789
790        /*
791         * Step 13: Copy  the exception vector table to system RAM
792         */
793        m68k_get_vbr (vbr);
794        for (i = 0; i < 256; ++i)
795                M68Kvec[i] = vbr[i];
796        m68k_set_vbr (M68Kvec);
797
798        /*
799         * Step 14: More system initialization
800         * SDCR (Serial DMA configuration register)
801         *      Enable SDMA during FREEZE
802         *      Give SDMA priority over all interrupt handlers
803         *      Set DMA arbiration level to 4
804         * CICR (CPM interrupt configuration register):
805         *      SCC1 requests at SCCa position
806         *      SCC2 requests at SCCb position
807         *      SCC3 requests at SCCc position
808         *      SCC4 requests at SCCd position
809         *      Interrupt request level 4
810         *      Maintain original priority order
811         *      Vector base 128
812         *      SCCs priority grouped at top of table
813         */
814        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
815        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
816                                                (4 << 13) | (0x1F << 8) | (128);
817
818        /*
819         * Step 15: Set module configuration register
820         *      Disable timers during FREEZE
821         *      Enable bus monitor during FREEZE
822         *      BCLRO* arbitration level 3
823         *      No show cycles
824         *      User/supervisor access
825         *      Bus clear interrupt service level 7
826         *      SIM60 interrupt sources higher priority than CPM
827         */
828        m360.mcr = 0x4C7F;
829#endif
830
831        /*
832         * Copy data, clear BSS, switch stacks and call main()
833         * Must pass ramSize as argument since the data/bss segment
834         * may be overwritten.
835         */
836        _CopyDataClearBSSAndStart (ramSize);
837}
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