source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ 3e7b167

4.104.114.84.95
Last change on this file since 3e7b167 was 996a9cb4, checked in by Joel Sherrill <joel.sherrill@…>, on 05/01/96 at 15:25:33

Updates from Eric Norum.

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 * MC68360 support routines
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
15#include <m68360.h>
16
17/*
18 * Send a command to the CPM RISC processer
19 */
20
21void M360ExecuteRISC(rtems_unsigned16 command)
22{
23        rtems_unsigned16 sr;
24
25        m68k_disable_interrupts (sr);
26        while (m360.cr & M360_CR_FLG)
27                continue;
28        m360.cr = command | M360_CR_FLG;
29        m68k_enable_interrupts (sr);
30}
31
32/*
33 * Initialize MC68360
34 */
35
36void _Init68360 (void)
37{
38        int i;
39        extern void *_RomBase, *_RamBase;
40        m68k_isr_entry *vbr;
41        extern void _CopyDataClearBSSAndStart (void);
42
43        /*
44         * Step 6: Is this a power-up reset?
45         * For now we just ignore this and do *all* the steps
46         * Someday we might want to:
47         *      if (Hard, Loss of Clock, Power-up)
48         *              Do all steps
49         *      else if (Double bus fault, watchdog or soft reset)
50         *              Skip to step 12
51         *      else (must be a CPU32+ reset command)
52         *              Skip to step 14
53         */
54
55        /*
56         * Step 7: Deal with clock synthesizer
57         * HARDWARE:
58         *      Change if you're not using an external 25 MHz oscillator.
59         */
60        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
61        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,  */
62                                        /* no LPSTOP slowdown, PLL X1 */
63        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
64
65        /*
66         * Step 8: Initialize system protection
67         *      Disable watchdog FIXME: Should use watchdog!!!!
68         *      Watchdog causes system reset
69         *      Fastest watchdog timeout
70         *      Enable double bus fault monitor
71         *      Enable bus monitor external
72         *      128 clocks for external timeout
73         */
74        m360.sypcr = 0x4F;
75
76        /*
77         * Step 9: Clear parameter RAM and reset communication processor module
78         */
79        for (i = 0 ; i < 192  ; i += sizeof (long)) {
80                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
81                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
82                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
83                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
84        }
85        M360ExecuteRISC (M360_CR_RST);
86
87        /*
88         * Step 10: Write PEPAR
89         *      SINTOUT not used (CPU32+ mode)
90         *      CF1MODE=00 (CONFIG1 input)
91         *      RAS1* double drive
92         *      A31-A28
93         *      OE* output
94         *      CAS2* / CAS3*
95         *      CAS0* / CAS1*
96         *      CS7*
97         *      AVEC*
98         * HARDWARE:
99         *      Change if you are using a different memory configuration
100         *      (static RAM, external address multiplexing, etc).
101         */
102        m360.pepar = 0x0100;
103
104        /*
105         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
106         *      1024 addresses per DRAM page (1M DRAM chips)
107         *      60 nsec DRAM
108         *      180 nsec ROM (3 wait states)
109         * HARDWARE:
110         *      Change if you are using a different memory configuration
111         */
112        m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | M360_GMR_RCYC(0) |
113                        M360_GMR_PGS(3) | M360_GMR_DPS_32BIT | M360_GMR_NCS |
114                        M360_GMR_GAMX;
115        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
116                                                        M360_MEMC_BR_V;
117        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
118                                                        M360_MEMC_OR_8BIT;
119
120        /*
121         * Step 12: Initialize the system RAM
122         *      Set up option/base registers
123         *              4 MB DRAM
124         *              60 nsec DRAM
125         *      Wait for chips to power up
126         *      Perform 8 read cycles
127         *      Set all parity bits to correct state
128         *      Enable parity checking
129         * HARDWARE:
130         *      Change if you are using a different memory configuration
131         */
132        m360.memc[1].or = M360_MEMC_OR_TCYC(0) | M360_MEMC_OR_4MB |
133                                M360_MEMC_OR_DRAM;
134        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
135        for (i = 0; i < 50000; i++)
136                continue;
137        for (i = 0; i < 8; ++i)
138                *((volatile unsigned long *)(unsigned long)&_RamBase);
139        for (i = 0 ; i < 4*1024*1024 ; i += sizeof (unsigned long)) {
140                volatile unsigned long *lp;
141                lp = (unsigned long *)((unsigned char *)&_RamBase + i);
142                *lp = *lp;
143        }
144        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_PAREN |
145                                                                M360_MEMC_BR_V;
146
147        /*
148         * Step 13: Copy  the exception vector table to system RAM
149         */
150        m68k_get_vbr (vbr);
151        for (i = 0; i < 256; ++i)
152                M68Kvec[i] = vbr[i];
153        m68k_set_vbr (M68Kvec);
154       
155        /*
156         * Step 14: More system initialization
157         * SDCR (Serial DMA configuratin register)
158         *      Give SDMA priority over all interrupt handlers
159         *      Set DMA arbiration level to 4
160         * CICR (CPM interrupt configuration register):
161         *      SCC1 requests at SCCa position
162         *      SCC2 requests at SCCb position
163         *      SCC3 requests at SCCc position
164         *      SCC4 requests at SCCd position
165         *      Interrupt request level 4
166         *      Maintain original priority order
167         *      Vector base 128
168         *      SCCs priority grouped at top of table
169         */
170        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
171        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
172                                                (4 << 13) | (0x1F << 8) | (128);
173
174        /*
175         * Step 15: Set module configuration register
176         *      Disable timers during FREEZE
177         *      Enable bus monitor during FREEZE
178         *      BCLRO* arbitration level 3
179         *      No show cycles
180         *      User/supervisor access
181         *      Bus clear interupt service level 7
182         *      SIM60 interrupt sources higher priority than CPM
183         */
184        m360.mcr = 0x4C7F;
185
186        /*
187         * Copy data, clear BSS, switch stacks and call main()
188         */
189        _CopyDataClearBSSAndStart ();
190}
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