source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ 21ee1c8

4.115
Last change on this file since 21ee1c8 was 21ee1c8, checked in by Joel Sherrill <joel.sherrill@…>, on 10/20/14 at 15:57:44

m68k/gen68360: Fix warnings

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Line 
1/*
2 * MC68360 support routines
3 */
4
5/*
6 * W. Eric Norum
7 * Saskatchewan Accelerator Laboratory
8 * University of Saskatchewan
9 * Saskatoon, Saskatchewan, CANADA
10 * eric@skatter.usask.ca
11 */
12
13#include <bsp.h>
14#include <rtems/m68k/m68360.h>
15
16extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
17extern void *RamBase;
18extern void *_RomBase;  /* From linkcmds */
19
20/*
21 * Declare the m360 structure here for the benefit of the debugger
22 */
23
24volatile m360_t m360;
25
26/*
27 * Send a command to the CPM RISC processer
28 */
29
30void M360ExecuteRISC(uint16_t         command)
31{
32  uint16_t         sr;
33
34  m68k_disable_interrupts (sr);
35  while (m360.cr & M360_CR_FLG)
36    continue;
37  m360.cr = command | M360_CR_FLG;
38  m68k_enable_interrupts (sr);
39}
40
41/*
42 * Initialize MC68360
43 */
44void _Init68360 (void)
45{
46  int i;
47  rtems_isr_entry *vbr;
48  unsigned long ramSize;
49
50#if (defined (__mc68040__))
51  volatile unsigned long *RamBase_p;
52
53  RamBase_p = (volatile unsigned long *)&RamBase;
54
55  /*
56   *******************************************
57   * Motorola 68040 and companion-mode 68360 *
58   *******************************************
59   */
60
61  /*
62   * Step 6: Is this a power-up reset?
63   * For now we just ignore this and do *all* the steps
64   * Someday we might want to:
65   *  if (Hard, Loss of Clock, Power-up)
66   *    Do all steps
67   *  else if (Double bus fault, watchdog or soft reset)
68   *    Skip to step 12
69   *  else (must be a reset command)
70   *    Skip to step 14
71   */
72
73  /*
74   * Step 7: Deal with clock synthesizer
75   * HARDWARE:
76   *  Change if you're not using an external 25 MHz oscillator.
77   */
78  m360.clkocr = 0x83;  /* No more writes, full-power CLKO2 */
79  m360.pllcr = 0xD000;  /* PLL, no writes, no prescale,
80           no LPSTOP slowdown, PLL X1 */
81  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
82
83  /*
84   * Step 8: Initialize system protection
85   *  Enable watchdog
86   *  Watchdog causes system reset
87   *  Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
88   *  Enable double bus fault monitor
89   *  Enable bus monitor for external cycles
90   *  1024 clocks for external timeout
91   */
92  m360.sypcr = 0xEC;
93
94  /*
95   * Step 9: Clear parameter RAM and reset communication processor module
96   */
97  for (i = 0 ; i < 192  ; i += sizeof (long)) {
98    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
99    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
100    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
101    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
102  }
103  M360ExecuteRISC (M360_CR_RST);
104
105  /*
106   * Step 10: Write PEPAR
107   *  SINTOUT standard M68000 family interrupt level encoding
108   *  CF1MODE=10 (BCLRO* output)
109   *  No RAS1* double drive
110   *  A31 - A28
111   *  AMUX output
112   *  CAS2* - CAS3*
113   *  CAS0* - CAS1*
114   *  CS7*
115   *  AVEC*
116   */
117  m360.pepar = 0x3440;
118
119  /*
120   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
121   */
122  /*
123   * 512 addresses per DRAM page (256K DRAM chips)
124   * 70 nsec DRAM
125   * 180 nsec ROM (3 wait states)
126   */
127  m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
128        M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
129        M360_GMR_DPS_32BIT | M360_GMR_NCS |
130        M360_GMR_TSS40;
131  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
132              M360_MEMC_BR_V;
133  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
134            M360_MEMC_OR_32BIT;
135
136  /*
137   * Step 12: Initialize the system RAM
138   */
139  /*
140   *  Set up option/base registers
141   *    1M DRAM
142   *    70 nsec DRAM
143   *  Enable burst mode
144   *  No parity checking
145   *  Wait for chips to power up
146   *  Perform 8 read cycles
147   */
148  ramSize = 1 * 1024 * 1024;
149  m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
150          M360_MEMC_OR_1MB |
151          M360_MEMC_OR_DRAM;
152  m360.memc[1].br = (unsigned long)&RamBase |
153          M360_MEMC_BR_BACK40 |
154          M360_MEMC_BR_V;
155  for (i = 0; i < 50000; i++)
156    continue;
157  for (i = 0; i < 8; ++i) {
158    unsigned long rambase_value;
159    rambase_value = *RamBase_p;
160    (void) rambase_value; /* avoid set but not used warning */
161  }
162
163  /*
164   * Step 13: Copy  the exception vector table to system RAM
165   */
166  m68k_get_vbr (vbr);
167  for (i = 0; i < 256; ++i)
168    M68Kvec[i] = vbr[i];
169  m68k_set_vbr (M68Kvec);
170
171  /*
172   * Step 14: More system initialization
173   * SDCR (Serial DMA configuration register)
174   *  Enable SDMA during FREEZE
175   *  Give SDMA priority over all interrupt handlers
176   *  Set DMA arbiration level to 4
177   * CICR (CPM interrupt configuration register):
178   *  SCC1 requests at SCCa position
179   *  SCC2 requests at SCCb position
180   *  SCC3 requests at SCCc position
181   *  SCC4 requests at SCCd position
182   *  Interrupt request level 4
183   *  Maintain original priority order
184   *  Vector base 128
185   *  SCCs priority grouped at top of table
186   */
187  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
188  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
189            (4 << 13) | (0x1F << 8) | (128);
190
191  /*
192   * Step 15: Set module configuration register
193   *  Bus request MC68040 Arbitration ID 3
194   *  Bus asynchronous timing mode (work around bug in Rev. B)
195   *  Arbitration asynchronous timing mode
196   *  Disable timers during FREEZE
197   *  Disable bus monitor during FREEZE
198   *  BCLRO* arbitration level 3
199   *  No show cycles
200   *  User/supervisor access
201   *  Bus clear in arbitration ID level  3
202   *  SIM60 interrupt sources higher priority than CPM
203   */
204  m360.mcr = 0x6000EC3F;
205
206#elif (defined (M68360_ATLAS_HSB))
207  /*
208   ******************************************
209   * Standalone Motorola 68360 -- ATLAS HSB *
210   ******************************************
211   */
212
213  /*
214   * Step 6: Is this a power-up reset?
215   * For now we just ignore this and do *all* the steps
216   * Someday we might want to:
217   *  if (Hard, Loss of Clock, Power-up)
218   *    Do all steps
219   *  else if (Double bus fault, watchdog or soft reset)
220   *    Skip to step 12
221   *  else (must be a CPU32+ reset command)
222   *    Skip to step 14
223   */
224
225  /*
226   * Step 7: Deal with clock synthesizer
227   * HARDWARE:
228   *  Change if you're not using an external 25 MHz oscillator.
229   */
230  m360.clkocr = 0x8F;  /* No more writes, no clock outputs */
231  m360.pllcr = 0xD000;  /* PLL, no writes, no prescale,
232           no LPSTOP slowdown, PLL X1 */
233  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
234
235  /*
236   * Step 8: Initialize system protection
237   *  Enable watchdog
238   *  Watchdog causes system reset
239   *  Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
240   *  Enable double bus fault monitor
241   *  Enable bus monitor for external cycles
242   *  1024 clocks for external timeout
243   */
244  m360.sypcr = 0xEC;
245
246  /*
247   * Step 9: Clear parameter RAM and reset communication processor module
248   */
249  for (i = 0 ; i < 192  ; i += sizeof (long)) {
250    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
251    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
252    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
253    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
254  }
255  M360ExecuteRISC (M360_CR_RST);
256
257  /*
258   * Step 10: Write PEPAR
259   *  SINTOUT not used (CPU32+ mode)
260   *  CF1MODE=00 (CONFIG1 input)
261   *  RAS1* double drive
262   *  WE0* - WE3*
263   *  OE* output
264   *  CAS2* - CAS3*
265   *  CAS0* - CAS1*
266   *  CS7*
267   *  AVEC*
268   * HARDWARE:
269   *  Change if you are using a different memory configuration
270   *  (static RAM, external address multiplexing, etc).
271   */
272  m360.pepar = 0x0180;
273
274  /*
275   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
276   */
277  m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
278        M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
279        M360_GMR_DPS_32BIT | M360_GMR_DWQ |
280        M360_GMR_GAMX;
281  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
282                M360_MEMC_BR_V;
283  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
284              M360_MEMC_OR_8BIT;
285
286  /*
287   * Step 12: Initialize the system RAM
288   */
289  ramSize = 2 * 1024 * 1024;
290  /* first bank 1MByte DRAM */
291  m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
292          M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
293  m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
294
295  /* second bank 1MByte DRAM */
296  m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
297          M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
298  m360.memc[2].br = ((unsigned long)&RamBase + 0x100000) |
299          M360_MEMC_BR_V;
300
301  /* flash rom socket U6 on CS5 */
302  m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
303                M360_MEMC_BR_V;
304  m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
305                M360_MEMC_OR_8BIT;
306
307  /* CSRs on CS7 */
308  m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
309          M360_MEMC_OR_8BIT;
310  m360.memc[7].br = ATLASHSB_ESR | 0x01;
311  for (i = 0; i < 50000; i++)
312    continue;
313  for (i = 0; i < 8; ++i)
314    *((volatile unsigned long *)(unsigned long)&RamBase);
315
316  /*
317   * Step 13: Copy  the exception vector table to system RAM
318   */
319  m68k_get_vbr (vbr);
320  for (i = 0; i < 256; ++i)
321    M68Kvec[i] = vbr[i];
322  m68k_set_vbr (M68Kvec);
323
324  /*
325   * Step 14: More system initialization
326   * SDCR (Serial DMA configuration register)
327   *  Enable SDMA during FREEZE
328   *  Give SDMA priority over all interrupt handlers
329   *  Set DMA arbiration level to 4
330   * CICR (CPM interrupt configuration register):
331   *  SCC1 requests at SCCa position
332   *  SCC2 requests at SCCb position
333   *  SCC3 requests at SCCc position
334   *  SCC4 requests at SCCd position
335   *  Interrupt request level 4
336   *  Maintain original priority order
337   *  Vector base 128
338   *  SCCs priority grouped at top of table
339   */
340  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
341  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
342            (4 << 13) | (0x1F << 8) | (128);
343
344  /*
345   * Step 15: Set module configuration register
346   *  Disable timers during FREEZE
347   *  Enable bus monitor during FREEZE
348   *  BCLRO* arbitration level 3
349   */
350
351#elif defined(PGH360)
352  /*
353   * Step 6: Is this a power-up reset?
354   * For now we just ignore this and do *all* the steps
355   * Someday we might want to:
356   *  if (Hard, Loss of Clock, Power-up)
357   *    Do all steps
358   *  else if (Double bus fault, watchdog or soft reset)
359   *    Skip to step 12
360   *  else (must be a CPU32+ reset command)
361   *    Skip to step 14
362   */
363
364  /*
365   * Step 7: Deal with clock synthesizer
366   * HARDWARE:
367   *  Change if you're not using an external 25 MHz oscillator.
368   */
369  m360.clkocr = 0x8e;  /* No more writes, CLKO1=1/3, CLKO2=off */
370  /*
371   * adjust crystal to average between 4.19 MHz and 4.00 MHz
372   * reprogram pll
373   */
374  m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
375          /* LPSTOP slowdown, PLL /128*??? */
376  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
377
378  /*
379   * Step 8: Initialize system protection
380   *  Enable watchdog
381   *  Watchdog causes system reset
382   *  128 sec. watchdog timeout
383   *  Enable double bus fault monitor
384   *  Enable bus monitor external
385   *  128 clocks for external timeout
386   */
387  m360.sypcr = 0xEF;
388  /*
389   * also initialize the SWP bit in PITR to 1
390   */
391  m360.pitr |= 0x0200;
392  /*
393   * and trigger SWSR twice to ensure, that interval starts right now
394   */
395  m360.swsr = 0x55;
396  m360.swsr = 0xAA;
397  m360.swsr = 0x55;
398  m360.swsr = 0xAA;
399  /*
400   * Step 9: Clear parameter RAM and reset communication processor module
401   */
402  for (i = 0 ; i < 192  ; i += sizeof (long)) {
403    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
404    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
405    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
406    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
407  }
408  M360ExecuteRISC (M360_CR_RST);
409
410  /*
411   * Step 10: Write PEPAR
412   *  SINTOUT not used (CPU32+ mode)
413   *  CF1MODE=00 (CONFIG1 input)
414   *  IPIPE1
415   *  WE0-3
416   *  OE* output
417   *  CAS2* / CAS3*
418   *  CAS0* / CAS1*
419   *  CS7*
420   *  AVEC*
421   * HARDWARE:
422   *  Change if you are using a different memory configuration
423   *  (static RAM, external address multiplexing, etc).
424   */
425  m360.pepar = 0x0080;
426  /*
427   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
428   *  no DRAM support
429   * HARDWARE:
430   *  Change if you are using a different memory configuration
431   */
432  m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN      | M360_GMR_RCYC(0) |
433       M360_GMR_PGS(6)   | M360_GMR_DPS_32BIT | M360_GMR_DWQ     |
434             M360_GMR_GAMX;
435
436  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
437              M360_MEMC_BR_V;
438  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
439              M360_MEMC_OR_8BIT;
440
441  /*
442   * Step 12: Initialize the system RAM
443   *  Set up option/base registers
444   *    16 MB DRAM
445   *    1 wait state
446   * HARDWARE:
447   *  Change if you are using a different memory configuration
448   *      NOTE: no Page mode possible for EDO RAMs (?)
449   */
450  ramSize = 16 * 1024 * 1024;
451  m360.memc[7].or = M360_MEMC_OR_TCYC(1)  | M360_MEMC_OR_16MB |
452        M360_MEMC_OR_FCMC(0)  | /* M360_MEMC_OR_PGME | */
453                          M360_MEMC_OR_32BIT    | M360_MEMC_OR_DRAM;
454  m360.memc[7].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
455
456  /*
457   * FIXME: here we should wait for 8 refresh cycles...
458   */
459  /*
460   * Step 12a: test the ram, if wanted
461   * FIXME: when do we call this?
462   * -> only during firmware execution
463   * -> perform intesive test only on request
464   * -> ensure, that results are stored properly
465   */
466#if 0 /* FIXME: activate RAM tests again */
467  {
468    void *ram_base, *ram_end, *code_loc;
469    extern char ramtest_start,ramtest_end;
470    ram_base = &ramtest_start;
471    ram_end  = &ramtest_end;
472    code_loc = (void *)ramtest_exec;
473    if ((ram_base < ram_end) &&
474      !((ram_base <= code_loc) && (code_loc < ram_end))) {
475      ramtest_exec(ram_base,ram_end);
476    }
477  }
478#endif
479  /*
480   * Step 13: Copy  the exception vector table to system RAM
481   */
482  m68k_get_vbr (vbr);
483  for (i = 0; i < 256; ++i)
484    M68Kvec[i] = vbr[i];
485  m68k_set_vbr (M68Kvec);
486
487  /*
488   * Step 14: More system initialization
489   * SDCR (Serial DMA configuration register)
490   *  Disable SDMA during FREEZE
491   *  Give SDMA priority over all interrupt handlers
492   *  Set DMA arbiration level to 4
493   * CICR (CPM interrupt configuration register):
494   *  SCC1 requests at SCCa position
495   *  SCC2 requests at SCCb position
496   *  SCC3 requests at SCCc position
497   *  SCC4 requests at SCCd position
498   *  Interrupt request level 4
499   *  Maintain original priority order
500   *  Vector base 128
501   *  SCCs priority grouped at top of table
502   */
503  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
504  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
505            (4 << 13) | (0x1F << 8) | (128);
506
507  /*
508   * Step 15: Set module configuration register
509   *  Disable timers during FREEZE
510   *  Enable bus monitor during FREEZE
511   *  BCLRO* arbitration level 3
512   *  No show cycles
513   *  User/supervisor access
514   *  Bus clear interupt service level 7
515   *  SIM60 interrupt sources higher priority than CPM
516   */
517  m360.mcr = 0x4C7F;
518
519#elif (defined (GEN68360_WITH_SRAM))
520   /*
521    ***************************************************
522    * Generic Standalone Motorola 68360               *
523    *           As described in MC68360 User's Manual *
524    * But uses SRAM instead of DRAM                   *
525    *  CS0* - 512kx8 flash memory                     *
526    *  CS1* - 512kx32 static RAM                      *
527    *  CS2* - 512kx32 static RAM                      *
528    ***************************************************
529    */
530
531   /*
532    * Step 7: Deal with clock synthesizer
533    * HARDWARE:
534    * Change if you're not using an external oscillator which
535    * oscillates at the system clock rate.
536    */
537   m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
538   m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
539                              no LPSTOP slowdown, PLL X1 */
540   m360.cdvcr = 0x8000;    /* No more writes, no clock division */
541
542   /*
543    * Step 8: Initialize system protection
544    * Enable watchdog
545    * Watchdog causes system reset
546    * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
547    * Enable double bus fault monitor
548    * Enable bus monitor for external cycles
549    * 1024 clocks for external timeout
550    */
551    m360.sypcr = 0xEC;
552
553   /*
554    * Step 9: Clear parameter RAM and reset communication processor module
555    */
556   for (i = 0 ; i < 192  ; i += sizeof (long)) {
557      *((long *)((char *)&m360 + 0xC00 + i)) = 0;
558      *((long *)((char *)&m360 + 0xD00 + i)) = 0;
559      *((long *)((char *)&m360 + 0xE00 + i)) = 0;
560      *((long *)((char *)&m360 + 0xF00 + i)) = 0;
561   }
562   M360ExecuteRISC (M360_CR_RST);
563
564   /*
565    * Step 10: Write PEPAR
566    * SINTOUT not used (CPU32+ mode)
567    * CF1MODE=00 (CONFIG1 input)
568    * IPIPE1*
569    * WE0* - WE3*
570    * OE* output
571    * CAS2* - CAS3*
572    * CAS0* - CAS1*
573    * CS7*
574    * AVEC*
575    * HARDWARE:
576    * Change if you are using a different memory configuration
577    * (static RAM, external address multiplexing, etc).
578    */
579   m360.pepar = 0x0080;
580
581   /*
582    * Step 11: Set up GMR
583    *
584    */
585   m360.gmr = 0x0;
586
587   /*
588    * Step 11a: Remap 512Kx8 flash memory on CS0*
589    * 2 wait states
590    * Make it read-only for now
591    */
592   m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
593                                                   M360_MEMC_BR_V;
594   m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
595                                                   M360_MEMC_OR_8BIT;
596   /*
597    * Step 12: Set up main memory
598    * 512Kx32 SRAM on CS1*
599    * 512Kx32 SRAM on CS2*
600    * 0 wait states
601    */
602   ramSize = 4 * 1024 * 1024;
603   m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
604   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
605                                                   M360_MEMC_OR_32BIT;
606   m360.memc[2].br = ((unsigned long)&RamBase + 0x200000) | M360_MEMC_BR_V;
607   m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
608                                                   M360_MEMC_OR_32BIT;
609   /*
610    * Step 13: Copy  the exception vector table to system RAM
611    */
612   m68k_get_vbr (vbr);
613   for (i = 0; i < 256; ++i)
614           M68Kvec[i] = vbr[i];
615   m68k_set_vbr (M68Kvec);
616
617   /*
618    * Step 14: More system initialization
619    * SDCR (Serial DMA configuration register)
620    * Enable SDMA during FREEZE
621    * Give SDMA priority over all interrupt handlers
622    * Set DMA arbiration level to 4
623    * CICR (CPM interrupt configuration register):
624    * SCC1 requests at SCCa position
625    * SCC2 requests at SCCb position
626    * SCC3 requests at SCCc position
627    * SCC4 requests at SCCd position
628    * Interrupt request level 4
629    * Maintain original priority order
630    * Vector base 128
631    * SCCs priority grouped at top of table
632    */
633   m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
634   m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
635                  (4 << 13) | (0x1F << 8) | (128);
636
637   /*
638    * Step 15: Set module configuration register
639    * Disable timers during FREEZE
640    * Enable bus monitor during FREEZE
641    * BCLRO* arbitration level 3
642    * No show cycles
643    * User/supervisor access
644    * Bus clear interrupt service level 7
645    * SIM60 interrupt sources higher priority than CPM
646    */
647   m360.mcr = 0x4C7F;
648
649#else
650  volatile unsigned long *RamBase_p;
651
652  RamBase_p = (volatile unsigned long *)&RamBase;
653  /*
654   ***************************************************
655   * Generic Standalone Motorola 68360               *
656   *           As described in MC68360 User's Manual *
657   *           Atlas ACE360                          *
658   ***************************************************
659   */
660
661  /*
662   * Step 6: Is this a power-up reset?
663   * For now we just ignore this and do *all* the steps
664   * Someday we might want to:
665   *  if (Hard, Loss of Clock, Power-up)
666   *    Do all steps
667   *  else if (Double bus fault, watchdog or soft reset)
668   *    Skip to step 12
669   *  else (must be a CPU32+ reset command)
670   *    Skip to step 14
671   */
672
673  /*
674   * Step 7: Deal with clock synthesizer
675   * HARDWARE:
676   *  Change if you're not using an external 25 MHz oscillator.
677   */
678  m360.clkocr = 0x8F;  /* No more writes, no clock outputs */
679  m360.pllcr = 0xD000;  /* PLL, no writes, no prescale,
680           no LPSTOP slowdown, PLL X1 */
681  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
682
683  /*
684   * Step 8: Initialize system protection
685   *  Enable watchdog
686   *  Watchdog causes system reset
687   *  Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
688   *  Enable double bus fault monitor
689   *  Enable bus monitor for external cycles
690   *  1024 clocks for external timeout
691   */
692  m360.sypcr = 0xEC;
693
694  /*
695   * Step 9: Clear parameter RAM and reset communication processor module
696   */
697  for (i = 0 ; i < 192  ; i += sizeof (long)) {
698    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
699    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
700    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
701    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
702  }
703  M360ExecuteRISC (M360_CR_RST);
704
705  /*
706   * Step 10: Write PEPAR
707   *  SINTOUT not used (CPU32+ mode)
708   *  CF1MODE=00 (CONFIG1 input)
709   *  RAS1* double drive
710   *  WE0* - WE3*
711   *  OE* output
712   *  CAS2* - CAS3*
713   *  CAS0* - CAS1*
714   *  CS7*
715   *  AVEC*
716   * HARDWARE:
717   *  Change if you are using a different memory configuration
718   *  (static RAM, external address multiplexing, etc).
719   */
720  m360.pepar = 0x0180;
721
722  /*
723   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
724   *  32-bit DRAM
725   *  Internal DRAM address multiplexing
726   *  60 nsec DRAM
727   *  180 nsec ROM (3 wait states)
728   *  15.36 usec DRAM refresh interval
729   *  The DRAM page size selection is not modified since this
730   *  startup code may be running in a bootstrap PROM or in
731   *  a program downloaded by the bootstrap PROM.
732   */
733  m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
734          M360_GMR_RFEN | M360_GMR_RCYC(0) |
735          M360_GMR_DPS_32BIT | M360_GMR_NCS |
736          M360_GMR_GAMX;
737  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
738                M360_MEMC_BR_V;
739  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
740              M360_MEMC_OR_8BIT;
741
742  /*
743   * Step 12: Initialize the system RAM
744   * Do this only if the DRAM has not already been set up
745   */
746  if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
747    /*
748     * Set up GMR DRAM page size, option and  base registers
749     *  Assume 16Mbytes of DRAM
750     *  60 nsec DRAM
751     */
752    m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
753    m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
754            M360_MEMC_OR_16MB |
755            M360_MEMC_OR_DRAM;
756    m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
757
758    /*
759     * Wait for chips to power up
760     *  Perform 8 read cycles
761     */
762    for (i = 0; i < 50000; i++)
763      continue;
764    for (i = 0; i < 8; ++i)
765      *RamBase_p;
766
767    /*
768     * Determine memory size (1, 4, or 16 Mbytes)
769     * Set GMR DRAM page size appropriately.
770     * The OR is left at 16 Mbytes.  The bootstrap PROM places its
771     * .data and .bss segments at the top of the 16 Mbyte space.
772     * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
773     * the memory map, but will work with the same bootstrap PROM.
774     */
775    *(volatile char *)&RamBase = 0;
776    *((volatile char *)&RamBase+0x00C01800) = 1;
777    if (*(volatile char *)&RamBase) {
778      m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
779    }
780    else {
781      *((volatile char *)&RamBase+0x00801000) = 1;
782      if (*(volatile char *)&RamBase) {
783        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
784      }
785    }
786
787    /*
788     * Enable parity checking
789     */
790    m360.memc[1].br |= M360_MEMC_BR_PAREN;
791  }
792  switch (m360.gmr & 0x001C0000) {
793  default:    ramSize =  4 * 1024 * 1024;  break;
794  case M360_GMR_PGS(1):  ramSize =  1 * 1024 * 1024;  break;
795  case M360_GMR_PGS(3):  ramSize =  4 * 1024 * 1024;  break;
796  case M360_GMR_PGS(5):  ramSize = 16 * 1024 * 1024;  break;
797  }
798
799  /*
800   * Step 13: Copy  the exception vector table to system RAM
801   */
802  m68k_get_vbr (vbr);
803  for (i = 0; i < 256; ++i)
804    M68Kvec[i] = vbr[i];
805  m68k_set_vbr (M68Kvec);
806
807  /*
808   * Step 14: More system initialization
809   * SDCR (Serial DMA configuration register)
810   *  Enable SDMA during FREEZE
811   *  Give SDMA priority over all interrupt handlers
812   *  Set DMA arbiration level to 4
813   * CICR (CPM interrupt configuration register):
814   *  SCC1 requests at SCCa position
815   *  SCC2 requests at SCCb position
816   *  SCC3 requests at SCCc position
817   *  SCC4 requests at SCCd position
818   *  Interrupt request level 4
819   *  Maintain original priority order
820   *  Vector base 128
821   *  SCCs priority grouped at top of table
822   */
823  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
824  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
825            (4 << 13) | (0x1F << 8) | (128);
826
827  /*
828   * Step 15: Set module configuration register
829   *  Disable timers during FREEZE
830   *  Enable bus monitor during FREEZE
831   *  BCLRO* arbitration level 3
832   *  No show cycles
833   *  User/supervisor access
834   *  Bus clear interrupt service level 7
835   *  SIM60 interrupt sources higher priority than CPM
836   */
837  m360.mcr = 0x4C7F;
838#endif
839
840  /*
841   * Copy data, clear BSS, switch stacks and call main()
842   * Must pass ramSize as argument since the data/bss segment
843   * may be overwritten.
844   */
845  _CopyDataClearBSSAndStart (ramSize);
846}
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