[d54de3f] | 1 | /* |
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| 2 | * MC68360 support routines |
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| 3 | * |
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| 4 | * W. Eric Norum |
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| 5 | * Saskatchewan Accelerator Laboratory |
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| 6 | * University of Saskatchewan |
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| 7 | * Saskatoon, Saskatchewan, CANADA |
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| 8 | * eric@skatter.usask.ca |
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| 9 | * |
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| 10 | * $Id$ |
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| 11 | */ |
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| 12 | |
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| 13 | #include <rtems.h> |
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| 14 | #include <bsp.h> |
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[424f3027] | 15 | #include <rtems/m68k/m68360.h> |
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[d54de3f] | 16 | |
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| 17 | /* |
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| 18 | * Send a command to the CPM RISC processer |
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| 19 | */ |
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| 20 | |
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[2d971fc] | 21 | void M360ExecuteRISC(uint16_t command) |
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[d54de3f] | 22 | { |
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[2d971fc] | 23 | uint16_t sr; |
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[d54de3f] | 24 | |
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| 25 | m68k_disable_interrupts (sr); |
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| 26 | while (m360.cr & M360_CR_FLG) |
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| 27 | continue; |
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| 28 | m360.cr = command | M360_CR_FLG; |
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| 29 | m68k_enable_interrupts (sr); |
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| 30 | } |
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| 31 | |
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| 32 | /* |
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| 33 | * Initialize MC68360 |
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| 34 | */ |
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| 35 | void _Init68360 (void) |
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| 36 | { |
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| 37 | int i; |
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| 38 | m68k_isr_entry *vbr; |
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[c0ebf02] | 39 | unsigned long ramSize; |
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| 40 | extern void _CopyDataClearBSSAndStart (unsigned long ramSize); |
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[c95013a0] | 41 | extern char _RamBase[]; |
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[b3e3a5fd] | 42 | extern void *_RomBase; /* From linkcmds */ |
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[d54de3f] | 43 | |
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[98bcbda3] | 44 | #if (defined (__mc68040__)) |
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[d54de3f] | 45 | /* |
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| 46 | ******************************************* |
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| 47 | * Motorola 68040 and companion-mode 68360 * |
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| 48 | ******************************************* |
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| 49 | */ |
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| 50 | |
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| 51 | /* |
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| 52 | * Step 6: Is this a power-up reset? |
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| 53 | * For now we just ignore this and do *all* the steps |
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| 54 | * Someday we might want to: |
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| 55 | * if (Hard, Loss of Clock, Power-up) |
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| 56 | * Do all steps |
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| 57 | * else if (Double bus fault, watchdog or soft reset) |
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| 58 | * Skip to step 12 |
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| 59 | * else (must be a reset command) |
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| 60 | * Skip to step 14 |
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| 61 | */ |
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| 62 | |
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| 63 | /* |
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| 64 | * Step 7: Deal with clock synthesizer |
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| 65 | * HARDWARE: |
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| 66 | * Change if you're not using an external 25 MHz oscillator. |
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| 67 | */ |
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| 68 | m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */ |
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| 69 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
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| 70 | no LPSTOP slowdown, PLL X1 */ |
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| 71 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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| 72 | |
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| 73 | /* |
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| 74 | * Step 8: Initialize system protection |
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| 75 | * Enable watchdog |
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| 76 | * Watchdog causes system reset |
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| 77 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
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| 78 | * Enable double bus fault monitor |
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| 79 | * Enable bus monitor for external cycles |
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| 80 | * 1024 clocks for external timeout |
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| 81 | */ |
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| 82 | m360.sypcr = 0xEC; |
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| 83 | |
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| 84 | /* |
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| 85 | * Step 9: Clear parameter RAM and reset communication processor module |
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| 86 | */ |
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| 87 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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| 88 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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| 89 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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| 90 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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| 91 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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| 92 | } |
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| 93 | M360ExecuteRISC (M360_CR_RST); |
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| 94 | |
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| 95 | /* |
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| 96 | * Step 10: Write PEPAR |
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| 97 | * SINTOUT standard M68000 family interrupt level encoding |
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| 98 | * CF1MODE=10 (BCLRO* output) |
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| 99 | * No RAS1* double drive |
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| 100 | * A31 - A28 |
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| 101 | * AMUX output |
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| 102 | * CAS2* - CAS3* |
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| 103 | * CAS0* - CAS1* |
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| 104 | * CS7* |
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| 105 | * AVEC* |
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| 106 | */ |
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| 107 | m360.pepar = 0x3440; |
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| 108 | |
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| 109 | /* |
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| 110 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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| 111 | */ |
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| 112 | /* |
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| 113 | * 512 addresses per DRAM page (256K DRAM chips) |
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| 114 | * 70 nsec DRAM |
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| 115 | * 180 nsec ROM (3 wait states) |
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| 116 | */ |
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[6128a4a] | 117 | m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN | |
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[d54de3f] | 118 | M360_GMR_RCYC(0) | M360_GMR_PGS(1) | |
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| 119 | M360_GMR_DPS_32BIT | M360_GMR_NCS | |
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| 120 | M360_GMR_TSS40; |
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| 121 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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| 122 | M360_MEMC_BR_V; |
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| 123 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | |
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| 124 | M360_MEMC_OR_32BIT; |
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| 125 | |
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| 126 | /* |
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| 127 | * Step 12: Initialize the system RAM |
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| 128 | */ |
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| 129 | /* |
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| 130 | * Set up option/base registers |
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| 131 | * 1M DRAM |
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| 132 | * 70 nsec DRAM |
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| 133 | * Enable burst mode |
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| 134 | * No parity checking |
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| 135 | * Wait for chips to power up |
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| 136 | * Perform 8 read cycles |
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| 137 | */ |
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[c0ebf02] | 138 | ramSize = 1 * 1024 * 1024; |
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[d54de3f] | 139 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) | |
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| 140 | M360_MEMC_OR_1MB | |
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| 141 | M360_MEMC_OR_DRAM; |
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| 142 | m360.memc[1].br = (unsigned long)&_RamBase | |
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| 143 | M360_MEMC_BR_BACK40 | |
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| 144 | M360_MEMC_BR_V; |
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| 145 | for (i = 0; i < 50000; i++) |
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| 146 | continue; |
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| 147 | for (i = 0; i < 8; ++i) |
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| 148 | *((volatile unsigned long *)(unsigned long)&_RamBase); |
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| 149 | |
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| 150 | /* |
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| 151 | * Step 13: Copy the exception vector table to system RAM |
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| 152 | */ |
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| 153 | m68k_get_vbr (vbr); |
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| 154 | for (i = 0; i < 256; ++i) |
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| 155 | M68Kvec[i] = vbr[i]; |
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| 156 | m68k_set_vbr (M68Kvec); |
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[6128a4a] | 157 | |
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[d54de3f] | 158 | /* |
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| 159 | * Step 14: More system initialization |
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| 160 | * SDCR (Serial DMA configuration register) |
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| 161 | * Enable SDMA during FREEZE |
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| 162 | * Give SDMA priority over all interrupt handlers |
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| 163 | * Set DMA arbiration level to 4 |
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| 164 | * CICR (CPM interrupt configuration register): |
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| 165 | * SCC1 requests at SCCa position |
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| 166 | * SCC2 requests at SCCb position |
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| 167 | * SCC3 requests at SCCc position |
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| 168 | * SCC4 requests at SCCd position |
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| 169 | * Interrupt request level 4 |
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| 170 | * Maintain original priority order |
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| 171 | * Vector base 128 |
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| 172 | * SCCs priority grouped at top of table |
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| 173 | */ |
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| 174 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
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| 175 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
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| 176 | (4 << 13) | (0x1F << 8) | (128); |
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| 177 | |
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| 178 | /* |
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| 179 | * Step 15: Set module configuration register |
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| 180 | * Bus request MC68040 Arbitration ID 3 |
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| 181 | * Bus asynchronous timing mode (work around bug in Rev. B) |
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| 182 | * Arbitration asynchronous timing mode |
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| 183 | * Disable timers during FREEZE |
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| 184 | * Disable bus monitor during FREEZE |
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| 185 | * BCLRO* arbitration level 3 |
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| 186 | * No show cycles |
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| 187 | * User/supervisor access |
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| 188 | * Bus clear in arbitration ID level 3 |
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| 189 | * SIM60 interrupt sources higher priority than CPM |
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| 190 | */ |
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| 191 | m360.mcr = 0x6000EC3F; |
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| 192 | |
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| 193 | #elif (defined (M68360_ATLAS_HSB)) |
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| 194 | /* |
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| 195 | ****************************************** |
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| 196 | * Standalone Motorola 68360 -- ATLAS HSB * |
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| 197 | ****************************************** |
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| 198 | */ |
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| 199 | |
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| 200 | /* |
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| 201 | * Step 6: Is this a power-up reset? |
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| 202 | * For now we just ignore this and do *all* the steps |
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| 203 | * Someday we might want to: |
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| 204 | * if (Hard, Loss of Clock, Power-up) |
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| 205 | * Do all steps |
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| 206 | * else if (Double bus fault, watchdog or soft reset) |
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| 207 | * Skip to step 12 |
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| 208 | * else (must be a CPU32+ reset command) |
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| 209 | * Skip to step 14 |
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| 210 | */ |
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| 211 | |
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| 212 | /* |
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| 213 | * Step 7: Deal with clock synthesizer |
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| 214 | * HARDWARE: |
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| 215 | * Change if you're not using an external 25 MHz oscillator. |
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| 216 | */ |
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| 217 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
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| 218 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
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| 219 | no LPSTOP slowdown, PLL X1 */ |
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| 220 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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| 221 | |
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| 222 | /* |
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| 223 | * Step 8: Initialize system protection |
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| 224 | * Enable watchdog |
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| 225 | * Watchdog causes system reset |
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| 226 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
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| 227 | * Enable double bus fault monitor |
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| 228 | * Enable bus monitor for external cycles |
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| 229 | * 1024 clocks for external timeout |
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| 230 | */ |
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| 231 | m360.sypcr = 0xEC; |
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| 232 | |
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| 233 | /* |
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| 234 | * Step 9: Clear parameter RAM and reset communication processor module |
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| 235 | */ |
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| 236 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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| 237 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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| 238 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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| 239 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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| 240 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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| 241 | } |
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| 242 | M360ExecuteRISC (M360_CR_RST); |
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| 243 | |
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| 244 | /* |
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| 245 | * Step 10: Write PEPAR |
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| 246 | * SINTOUT not used (CPU32+ mode) |
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| 247 | * CF1MODE=00 (CONFIG1 input) |
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| 248 | * RAS1* double drive |
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| 249 | * WE0* - WE3* |
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| 250 | * OE* output |
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| 251 | * CAS2* - CAS3* |
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| 252 | * CAS0* - CAS1* |
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| 253 | * CS7* |
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| 254 | * AVEC* |
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| 255 | * HARDWARE: |
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| 256 | * Change if you are using a different memory configuration |
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| 257 | * (static RAM, external address multiplexing, etc). |
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| 258 | */ |
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| 259 | m360.pepar = 0x0180; |
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| 260 | |
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| 261 | /* |
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| 262 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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| 263 | */ |
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[6128a4a] | 264 | m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN | |
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| 265 | M360_GMR_RCYC(0) | M360_GMR_PGS(1) | |
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[d54de3f] | 266 | M360_GMR_DPS_32BIT | M360_GMR_DWQ | |
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| 267 | M360_GMR_GAMX; |
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| 268 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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| 269 | M360_MEMC_BR_V; |
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| 270 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | |
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| 271 | M360_MEMC_OR_8BIT; |
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| 272 | |
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| 273 | /* |
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| 274 | * Step 12: Initialize the system RAM |
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| 275 | */ |
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[c0ebf02] | 276 | ramSize = 2 * 1024 * 1024; |
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[d54de3f] | 277 | /* first bank 1MByte DRAM */ |
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| 278 | m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | |
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| 279 | M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; |
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| 280 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; |
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| 281 | |
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| 282 | /* second bank 1MByte DRAM */ |
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| 283 | m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | |
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| 284 | M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; |
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| 285 | m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) | |
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| 286 | M360_MEMC_BR_V; |
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| 287 | |
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| 288 | /* flash rom socket U6 on CS5 */ |
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| 289 | m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP | |
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| 290 | M360_MEMC_BR_V; |
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| 291 | m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | |
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| 292 | M360_MEMC_OR_8BIT; |
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| 293 | |
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| 294 | /* CSRs on CS7 */ |
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| 295 | m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB | |
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| 296 | M360_MEMC_OR_8BIT; |
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| 297 | m360.memc[7].br = ATLASHSB_ESR | 0x01; |
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| 298 | for (i = 0; i < 50000; i++) |
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| 299 | continue; |
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| 300 | for (i = 0; i < 8; ++i) |
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| 301 | *((volatile unsigned long *)(unsigned long)&_RamBase); |
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| 302 | |
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| 303 | /* |
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| 304 | * Step 13: Copy the exception vector table to system RAM |
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| 305 | */ |
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| 306 | m68k_get_vbr (vbr); |
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| 307 | for (i = 0; i < 256; ++i) |
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| 308 | M68Kvec[i] = vbr[i]; |
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| 309 | m68k_set_vbr (M68Kvec); |
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[6128a4a] | 310 | |
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[d54de3f] | 311 | /* |
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| 312 | * Step 14: More system initialization |
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| 313 | * SDCR (Serial DMA configuration register) |
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| 314 | * Enable SDMA during FREEZE |
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| 315 | * Give SDMA priority over all interrupt handlers |
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| 316 | * Set DMA arbiration level to 4 |
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| 317 | * CICR (CPM interrupt configuration register): |
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| 318 | * SCC1 requests at SCCa position |
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| 319 | * SCC2 requests at SCCb position |
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| 320 | * SCC3 requests at SCCc position |
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| 321 | * SCC4 requests at SCCd position |
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| 322 | * Interrupt request level 4 |
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| 323 | * Maintain original priority order |
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| 324 | * Vector base 128 |
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| 325 | * SCCs priority grouped at top of table |
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| 326 | */ |
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| 327 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
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| 328 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
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| 329 | (4 << 13) | (0x1F << 8) | (128); |
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| 330 | |
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| 331 | /* |
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| 332 | * Step 15: Set module configuration register |
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| 333 | * Disable timers during FREEZE |
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| 334 | * Enable bus monitor during FREEZE |
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| 335 | * BCLRO* arbitration level 3 |
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[c0ebf02] | 336 | */ |
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[66fe6be6] | 337 | |
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| 338 | #elif (defined (GEN68360_WITH_SRAM)) |
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| 339 | /* |
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| 340 | *************************************************** |
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| 341 | * Generic Standalone Motorola 68360 * |
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| 342 | * As described in MC68360 User's Manual * |
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| 343 | * But uses SRAM instead of DRAM * |
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| 344 | * CS0* - 512kx8 flash memory * |
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| 345 | * CS1* - 512kx32 static RAM * |
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[df49c60] | 346 | * CS2* - 512kx32 static RAM * |
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[66fe6be6] | 347 | *************************************************** |
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| 348 | */ |
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| 349 | |
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| 350 | /* |
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| 351 | * Step 7: Deal with clock synthesizer |
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| 352 | * HARDWARE: |
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| 353 | * Change if you're not using an external oscillator which |
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| 354 | * oscillates at the system clock rate. |
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| 355 | */ |
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| 356 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
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| 357 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
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| 358 | no LPSTOP slowdown, PLL X1 */ |
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| 359 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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| 360 | |
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| 361 | /* |
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| 362 | * Step 8: Initialize system protection |
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| 363 | * Enable watchdog |
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| 364 | * Watchdog causes system reset |
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| 365 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
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| 366 | * Enable double bus fault monitor |
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| 367 | * Enable bus monitor for external cycles |
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| 368 | * 1024 clocks for external timeout |
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| 369 | */ |
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[6128a4a] | 370 | m360.sypcr = 0xEC; |
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[66fe6be6] | 371 | |
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| 372 | /* |
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| 373 | * Step 9: Clear parameter RAM and reset communication processor module |
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| 374 | */ |
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| 375 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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| 376 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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| 377 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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| 378 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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[6128a4a] | 379 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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| 380 | } |
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[66fe6be6] | 381 | M360ExecuteRISC (M360_CR_RST); |
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| 382 | |
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| 383 | /* |
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| 384 | * Step 10: Write PEPAR |
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| 385 | * SINTOUT not used (CPU32+ mode) |
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| 386 | * CF1MODE=00 (CONFIG1 input) |
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| 387 | * IPIPE1* |
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| 388 | * WE0* - WE3* |
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| 389 | * OE* output |
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| 390 | * CAS2* - CAS3* |
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| 391 | * CAS0* - CAS1* |
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| 392 | * CS7* |
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| 393 | * AVEC* |
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| 394 | * HARDWARE: |
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| 395 | * Change if you are using a different memory configuration |
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| 396 | * (static RAM, external address multiplexing, etc). |
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| 397 | */ |
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| 398 | m360.pepar = 0x0080; |
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| 399 | |
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| 400 | /* |
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| 401 | * Step 11: Set up GMR |
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[6128a4a] | 402 | * |
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[66fe6be6] | 403 | */ |
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| 404 | m360.gmr = 0x0; |
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| 405 | |
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| 406 | /* |
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| 407 | * Step 11a: Remap 512Kx8 flash memory on CS0* |
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[6128a4a] | 408 | * 2 wait states |
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| 409 | * Make it read-only for now |
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[66fe6be6] | 410 | */ |
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[6128a4a] | 411 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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[66fe6be6] | 412 | M360_MEMC_BR_V; |
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| 413 | m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | |
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| 414 | M360_MEMC_OR_8BIT; |
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| 415 | /* |
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| 416 | * Step 12: Set up main memory |
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| 417 | * 512Kx32 SRAM on CS1* |
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[df49c60] | 418 | * 512Kx32 SRAM on CS2* |
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[66fe6be6] | 419 | * 0 wait states |
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| 420 | */ |
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[df49c60] | 421 | ramSize = 4 * 1024 * 1024; |
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[66fe6be6] | 422 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; |
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| 423 | m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | |
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[6128a4a] | 424 | M360_MEMC_OR_32BIT; |
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[df49c60] | 425 | m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V; |
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| 426 | m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | |
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[6128a4a] | 427 | M360_MEMC_OR_32BIT; |
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[66fe6be6] | 428 | /* |
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| 429 | * Step 13: Copy the exception vector table to system RAM |
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| 430 | */ |
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| 431 | m68k_get_vbr (vbr); |
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| 432 | for (i = 0; i < 256; ++i) |
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| 433 | M68Kvec[i] = vbr[i]; |
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| 434 | m68k_set_vbr (M68Kvec); |
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| 435 | |
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| 436 | /* |
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| 437 | * Step 14: More system initialization |
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| 438 | * SDCR (Serial DMA configuration register) |
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| 439 | * Enable SDMA during FREEZE |
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| 440 | * Give SDMA priority over all interrupt handlers |
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| 441 | * Set DMA arbiration level to 4 |
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| 442 | * CICR (CPM interrupt configuration register): |
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| 443 | * SCC1 requests at SCCa position |
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| 444 | * SCC2 requests at SCCb position |
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| 445 | * SCC3 requests at SCCc position |
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| 446 | * SCC4 requests at SCCd position |
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| 447 | * Interrupt request level 4 |
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| 448 | * Maintain original priority order |
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| 449 | * Vector base 128 |
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| 450 | * SCCs priority grouped at top of table |
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| 451 | */ |
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| 452 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
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| 453 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
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| 454 | (4 << 13) | (0x1F << 8) | (128); |
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| 455 | |
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| 456 | /* |
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| 457 | * Step 15: Set module configuration register |
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| 458 | * Disable timers during FREEZE |
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| 459 | * Enable bus monitor during FREEZE |
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| 460 | * BCLRO* arbitration level 3 |
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| 461 | * No show cycles |
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| 462 | * User/supervisor access |
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| 463 | * Bus clear interrupt service level 7 |
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| 464 | * SIM60 interrupt sources higher priority than CPM |
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| 465 | */ |
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| 466 | m360.mcr = 0x4C7F; |
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[d54de3f] | 467 | |
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| 468 | #else |
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| 469 | /* |
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| 470 | *************************************************** |
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| 471 | * Generic Standalone Motorola 68360 * |
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| 472 | * As described in MC68360 User's Manual * |
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| 473 | * Atlas ACE360 * |
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| 474 | *************************************************** |
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| 475 | */ |
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| 476 | |
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| 477 | /* |
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| 478 | * Step 6: Is this a power-up reset? |
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| 479 | * For now we just ignore this and do *all* the steps |
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| 480 | * Someday we might want to: |
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| 481 | * if (Hard, Loss of Clock, Power-up) |
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| 482 | * Do all steps |
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| 483 | * else if (Double bus fault, watchdog or soft reset) |
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| 484 | * Skip to step 12 |
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| 485 | * else (must be a CPU32+ reset command) |
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| 486 | * Skip to step 14 |
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| 487 | */ |
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| 488 | |
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| 489 | /* |
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| 490 | * Step 7: Deal with clock synthesizer |
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| 491 | * HARDWARE: |
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| 492 | * Change if you're not using an external 25 MHz oscillator. |
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| 493 | */ |
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| 494 | m360.clkocr = 0x8F; /* No more writes, no clock outputs */ |
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| 495 | m360.pllcr = 0xD000; /* PLL, no writes, no prescale, |
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| 496 | no LPSTOP slowdown, PLL X1 */ |
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| 497 | m360.cdvcr = 0x8000; /* No more writes, no clock division */ |
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| 498 | |
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| 499 | /* |
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| 500 | * Step 8: Initialize system protection |
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| 501 | * Enable watchdog |
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| 502 | * Watchdog causes system reset |
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| 503 | * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator) |
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| 504 | * Enable double bus fault monitor |
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| 505 | * Enable bus monitor for external cycles |
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| 506 | * 1024 clocks for external timeout |
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| 507 | */ |
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| 508 | m360.sypcr = 0xEC; |
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| 509 | |
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| 510 | /* |
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| 511 | * Step 9: Clear parameter RAM and reset communication processor module |
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| 512 | */ |
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| 513 | for (i = 0 ; i < 192 ; i += sizeof (long)) { |
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| 514 | *((long *)((char *)&m360 + 0xC00 + i)) = 0; |
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| 515 | *((long *)((char *)&m360 + 0xD00 + i)) = 0; |
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| 516 | *((long *)((char *)&m360 + 0xE00 + i)) = 0; |
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| 517 | *((long *)((char *)&m360 + 0xF00 + i)) = 0; |
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| 518 | } |
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| 519 | M360ExecuteRISC (M360_CR_RST); |
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| 520 | |
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| 521 | /* |
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| 522 | * Step 10: Write PEPAR |
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| 523 | * SINTOUT not used (CPU32+ mode) |
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| 524 | * CF1MODE=00 (CONFIG1 input) |
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| 525 | * RAS1* double drive |
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| 526 | * WE0* - WE3* |
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| 527 | * OE* output |
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| 528 | * CAS2* - CAS3* |
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| 529 | * CAS0* - CAS1* |
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| 530 | * CS7* |
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| 531 | * AVEC* |
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| 532 | * HARDWARE: |
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| 533 | * Change if you are using a different memory configuration |
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| 534 | * (static RAM, external address multiplexing, etc). |
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| 535 | */ |
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| 536 | m360.pepar = 0x0180; |
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| 537 | |
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| 538 | /* |
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| 539 | * Step 11: Remap Chip Select 0 (CS0*), set up GMR |
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[98bcbda3] | 540 | * 32-bit DRAM |
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| 541 | * Internal DRAM address multiplexing |
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| 542 | * 60 nsec DRAM |
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| 543 | * 180 nsec ROM (3 wait states) |
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| 544 | * 15.36 usec DRAM refresh interval |
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| 545 | * The DRAM page size selection is not modified since this |
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| 546 | * startup code may be running in a bootstrap PROM or in |
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| 547 | * a program downloaded by the bootstrap PROM. |
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| 548 | */ |
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[6128a4a] | 549 | m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) | |
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| 550 | M360_GMR_RFEN | M360_GMR_RCYC(0) | |
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| 551 | M360_GMR_DPS_32BIT | M360_GMR_NCS | |
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[d54de3f] | 552 | M360_GMR_GAMX; |
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| 553 | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | |
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| 554 | M360_MEMC_BR_V; |
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| 555 | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | |
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| 556 | M360_MEMC_OR_8BIT; |
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| 557 | |
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| 558 | /* |
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| 559 | * Step 12: Initialize the system RAM |
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[98bcbda3] | 560 | * Do this only if the DRAM has not already been set up |
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| 561 | */ |
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| 562 | if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) { |
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| 563 | /* |
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| 564 | * Set up GMR DRAM page size, option and base registers |
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| 565 | * Assume 16Mbytes of DRAM |
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| 566 | * 60 nsec DRAM |
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| 567 | */ |
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| 568 | m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5); |
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[d54de3f] | 569 | m360.memc[1].or = M360_MEMC_OR_TCYC(0) | |
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[98bcbda3] | 570 | M360_MEMC_OR_16MB | |
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| 571 | M360_MEMC_OR_DRAM; |
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| 572 | m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; |
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| 573 | |
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| 574 | /* |
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| 575 | * Wait for chips to power up |
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| 576 | * Perform 8 read cycles |
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| 577 | */ |
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| 578 | for (i = 0; i < 50000; i++) |
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| 579 | continue; |
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| 580 | for (i = 0; i < 8; ++i) |
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| 581 | *((volatile unsigned long *)(unsigned long)&_RamBase); |
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| 582 | |
---|
| 583 | /* |
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| 584 | * Determine memory size (1, 4, or 16 Mbytes) |
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| 585 | * Set GMR DRAM page size appropriately. |
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| 586 | * The OR is left at 16 Mbytes. The bootstrap PROM places its |
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| 587 | * .data and .bss segments at the top of the 16 Mbyte space. |
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| 588 | * A 1 Mbyte or 4 Mbyte DRAM will show up several times in |
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| 589 | * the memory map, but will work with the same bootstrap PROM. |
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| 590 | */ |
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| 591 | *(volatile char *)&_RamBase = 0; |
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| 592 | *((volatile char *)&_RamBase+0x00C01800) = 1; |
---|
| 593 | if (*(volatile char *)&_RamBase) { |
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| 594 | m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1); |
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| 595 | } |
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| 596 | else { |
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| 597 | *((volatile char *)&_RamBase+0x00801000) = 1; |
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| 598 | if (*(volatile char *)&_RamBase) { |
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| 599 | m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3); |
---|
| 600 | } |
---|
| 601 | } |
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| 602 | |
---|
| 603 | /* |
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| 604 | * Enable parity checking |
---|
| 605 | */ |
---|
| 606 | m360.memc[1].br |= M360_MEMC_BR_PAREN; |
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[d54de3f] | 607 | } |
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[c0ebf02] | 608 | switch (m360.gmr & 0x001C0000) { |
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| 609 | default: ramSize = 4 * 1024 * 1024; break; |
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| 610 | case M360_GMR_PGS(1): ramSize = 1 * 1024 * 1024; break; |
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| 611 | case M360_GMR_PGS(3): ramSize = 4 * 1024 * 1024; break; |
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| 612 | case M360_GMR_PGS(5): ramSize = 16 * 1024 * 1024; break; |
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| 613 | } |
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[d54de3f] | 614 | |
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| 615 | /* |
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| 616 | * Step 13: Copy the exception vector table to system RAM |
---|
| 617 | */ |
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| 618 | m68k_get_vbr (vbr); |
---|
| 619 | for (i = 0; i < 256; ++i) |
---|
| 620 | M68Kvec[i] = vbr[i]; |
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| 621 | m68k_set_vbr (M68Kvec); |
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[6128a4a] | 622 | |
---|
[d54de3f] | 623 | /* |
---|
| 624 | * Step 14: More system initialization |
---|
| 625 | * SDCR (Serial DMA configuration register) |
---|
| 626 | * Enable SDMA during FREEZE |
---|
| 627 | * Give SDMA priority over all interrupt handlers |
---|
| 628 | * Set DMA arbiration level to 4 |
---|
| 629 | * CICR (CPM interrupt configuration register): |
---|
| 630 | * SCC1 requests at SCCa position |
---|
| 631 | * SCC2 requests at SCCb position |
---|
| 632 | * SCC3 requests at SCCc position |
---|
| 633 | * SCC4 requests at SCCd position |
---|
| 634 | * Interrupt request level 4 |
---|
| 635 | * Maintain original priority order |
---|
| 636 | * Vector base 128 |
---|
| 637 | * SCCs priority grouped at top of table |
---|
| 638 | */ |
---|
| 639 | m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; |
---|
| 640 | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | |
---|
| 641 | (4 << 13) | (0x1F << 8) | (128); |
---|
| 642 | |
---|
| 643 | /* |
---|
| 644 | * Step 15: Set module configuration register |
---|
| 645 | * Disable timers during FREEZE |
---|
| 646 | * Enable bus monitor during FREEZE |
---|
| 647 | * BCLRO* arbitration level 3 |
---|
| 648 | * No show cycles |
---|
| 649 | * User/supervisor access |
---|
| 650 | * Bus clear interrupt service level 7 |
---|
| 651 | * SIM60 interrupt sources higher priority than CPM |
---|
| 652 | */ |
---|
| 653 | m360.mcr = 0x4C7F; |
---|
| 654 | #endif |
---|
| 655 | |
---|
| 656 | /* |
---|
| 657 | * Copy data, clear BSS, switch stacks and call main() |
---|
[c0ebf02] | 658 | * Must pass ramSize as argument since the data/bss segment |
---|
| 659 | * may be overwritten. |
---|
[d54de3f] | 660 | */ |
---|
[c0ebf02] | 661 | _CopyDataClearBSSAndStart (ramSize); |
---|
[d54de3f] | 662 | } |
---|