source: rtems/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @ b3e3a5fd

4.104.114.84.95
Last change on this file since b3e3a5fd was b3e3a5fd, checked in by Joel Sherrill <joel.sherrill@…>, on 03/11/05 at 20:06:37

2005-03-11 Joel Sherrill <joel@…>

  • startup/init68360.c: Add _RomBase declaration.
  • Property mode set to 100644
File size: 18.7 KB
RevLine 
[d54de3f]1/*
2 * MC68360 support routines
3 *
4 * W. Eric Norum
5 * Saskatchewan Accelerator Laboratory
6 * University of Saskatchewan
7 * Saskatoon, Saskatchewan, CANADA
8 * eric@skatter.usask.ca
9 *
10 *  $Id$
11 */
12
13#include <rtems.h>
14#include <bsp.h>
[424f3027]15#include <rtems/m68k/m68360.h>
[d54de3f]16
17/*
18 * Send a command to the CPM RISC processer
19 */
20
[2d971fc]21void M360ExecuteRISC(uint16_t         command)
[d54de3f]22{
[2d971fc]23        uint16_t         sr;
[d54de3f]24
25        m68k_disable_interrupts (sr);
26        while (m360.cr & M360_CR_FLG)
27                continue;
28        m360.cr = command | M360_CR_FLG;
29        m68k_enable_interrupts (sr);
30}
31
32/*
33 * Initialize MC68360
34 */
35void _Init68360 (void)
36{
37        int i;
38        m68k_isr_entry *vbr;
[c0ebf02]39        unsigned long ramSize;
40        extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
[c95013a0]41        extern char _RamBase[];
[b3e3a5fd]42        extern void *_RomBase;  /* From linkcmds */
[d54de3f]43
[98bcbda3]44#if (defined (__mc68040__))
[d54de3f]45        /*
46         *******************************************
47         * Motorola 68040 and companion-mode 68360 *
48         *******************************************
49         */
50
51        /*
52         * Step 6: Is this a power-up reset?
53         * For now we just ignore this and do *all* the steps
54         * Someday we might want to:
55         *      if (Hard, Loss of Clock, Power-up)
56         *              Do all steps
57         *      else if (Double bus fault, watchdog or soft reset)
58         *              Skip to step 12
59         *      else (must be a reset command)
60         *              Skip to step 14
61         */
62
63        /*
64         * Step 7: Deal with clock synthesizer
65         * HARDWARE:
66         *      Change if you're not using an external 25 MHz oscillator.
67         */
68        m360.clkocr = 0x83;     /* No more writes, full-power CLKO2 */
69        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
70                                   no LPSTOP slowdown, PLL X1 */
71        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
72
73        /*
74         * Step 8: Initialize system protection
75         *      Enable watchdog
76         *      Watchdog causes system reset
77         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
78         *      Enable double bus fault monitor
79         *      Enable bus monitor for external cycles
80         *      1024 clocks for external timeout
81         */
82        m360.sypcr = 0xEC;
83
84        /*
85         * Step 9: Clear parameter RAM and reset communication processor module
86         */
87        for (i = 0 ; i < 192  ; i += sizeof (long)) {
88                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
89                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
90                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
91                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
92        }
93        M360ExecuteRISC (M360_CR_RST);
94
95        /*
96         * Step 10: Write PEPAR
97         *      SINTOUT standard M68000 family interrupt level encoding
98         *      CF1MODE=10 (BCLRO* output)
99         *      No RAS1* double drive
100         *      A31 - A28
101         *      AMUX output
102         *      CAS2* - CAS3*
103         *      CAS0* - CAS1*
104         *      CS7*
105         *      AVEC*
106         */
107        m360.pepar = 0x3440;
108
109        /*
110         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
111         */
112        /*
113         * 512 addresses per DRAM page (256K DRAM chips)
114         * 70 nsec DRAM
115         * 180 nsec ROM (3 wait states)
116         */
[6128a4a]117        m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
[d54de3f]118                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
119                                M360_GMR_DPS_32BIT | M360_GMR_NCS |
120                                M360_GMR_TSS40;
121        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
122                                                        M360_MEMC_BR_V;
123        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
124                                                M360_MEMC_OR_32BIT;
125
126        /*
127         * Step 12: Initialize the system RAM
128         */
129        /*
130         *      Set up option/base registers
131         *              1M DRAM
132         *              70 nsec DRAM
133         *      Enable burst mode
134         *      No parity checking
135         *      Wait for chips to power up
136         *      Perform 8 read cycles
137         */
[c0ebf02]138        ramSize = 1 * 1024 * 1024;
[d54de3f]139        m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
140                                        M360_MEMC_OR_1MB |
141                                        M360_MEMC_OR_DRAM;
142        m360.memc[1].br = (unsigned long)&_RamBase |
143                                        M360_MEMC_BR_BACK40 |
144                                        M360_MEMC_BR_V;
145        for (i = 0; i < 50000; i++)
146                continue;
147        for (i = 0; i < 8; ++i)
148                *((volatile unsigned long *)(unsigned long)&_RamBase);
149
150        /*
151         * Step 13: Copy  the exception vector table to system RAM
152         */
153        m68k_get_vbr (vbr);
154        for (i = 0; i < 256; ++i)
155                M68Kvec[i] = vbr[i];
156        m68k_set_vbr (M68Kvec);
[6128a4a]157
[d54de3f]158        /*
159         * Step 14: More system initialization
160         * SDCR (Serial DMA configuration register)
161         *      Enable SDMA during FREEZE
162         *      Give SDMA priority over all interrupt handlers
163         *      Set DMA arbiration level to 4
164         * CICR (CPM interrupt configuration register):
165         *      SCC1 requests at SCCa position
166         *      SCC2 requests at SCCb position
167         *      SCC3 requests at SCCc position
168         *      SCC4 requests at SCCd position
169         *      Interrupt request level 4
170         *      Maintain original priority order
171         *      Vector base 128
172         *      SCCs priority grouped at top of table
173         */
174        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
175        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
176                                                (4 << 13) | (0x1F << 8) | (128);
177
178        /*
179         * Step 15: Set module configuration register
180         *      Bus request MC68040 Arbitration ID 3
181         *      Bus asynchronous timing mode (work around bug in Rev. B)
182         *      Arbitration asynchronous timing mode
183         *      Disable timers during FREEZE
184         *      Disable bus monitor during FREEZE
185         *      BCLRO* arbitration level 3
186         *      No show cycles
187         *      User/supervisor access
188         *      Bus clear in arbitration ID level  3
189         *      SIM60 interrupt sources higher priority than CPM
190         */
191        m360.mcr = 0x6000EC3F;
192
193#elif (defined (M68360_ATLAS_HSB))
194        /*
195         ******************************************
196         * Standalone Motorola 68360 -- ATLAS HSB *
197         ******************************************
198         */
199
200        /*
201         * Step 6: Is this a power-up reset?
202         * For now we just ignore this and do *all* the steps
203         * Someday we might want to:
204         *      if (Hard, Loss of Clock, Power-up)
205         *              Do all steps
206         *      else if (Double bus fault, watchdog or soft reset)
207         *              Skip to step 12
208         *      else (must be a CPU32+ reset command)
209         *              Skip to step 14
210         */
211
212        /*
213         * Step 7: Deal with clock synthesizer
214         * HARDWARE:
215         *      Change if you're not using an external 25 MHz oscillator.
216         */
217        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
218        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
219                                   no LPSTOP slowdown, PLL X1 */
220        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
221
222        /*
223         * Step 8: Initialize system protection
224         *      Enable watchdog
225         *      Watchdog causes system reset
226         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
227         *      Enable double bus fault monitor
228         *      Enable bus monitor for external cycles
229         *      1024 clocks for external timeout
230         */
231        m360.sypcr = 0xEC;
232
233        /*
234         * Step 9: Clear parameter RAM and reset communication processor module
235         */
236        for (i = 0 ; i < 192  ; i += sizeof (long)) {
237                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
238                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
239                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
240                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
241        }
242        M360ExecuteRISC (M360_CR_RST);
243
244        /*
245         * Step 10: Write PEPAR
246         *      SINTOUT not used (CPU32+ mode)
247         *      CF1MODE=00 (CONFIG1 input)
248         *      RAS1* double drive
249         *      WE0* - WE3*
250         *      OE* output
251         *      CAS2* - CAS3*
252         *      CAS0* - CAS1*
253         *      CS7*
254         *      AVEC*
255         * HARDWARE:
256         *      Change if you are using a different memory configuration
257         *      (static RAM, external address multiplexing, etc).
258         */
259        m360.pepar = 0x0180;
260
261        /*
262         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
263         */
[6128a4a]264        m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
265                                M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
[d54de3f]266                                M360_GMR_DPS_32BIT | M360_GMR_DWQ |
267                                M360_GMR_GAMX;
268        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
269                                                                M360_MEMC_BR_V;
270        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
271                                                        M360_MEMC_OR_8BIT;
272
273        /*
274         * Step 12: Initialize the system RAM
275         */
[c0ebf02]276        ramSize = 2 * 1024 * 1024;
[d54de3f]277        /* first bank 1MByte DRAM */
278        m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
279                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
280        m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
281
282        /* second bank 1MByte DRAM */
283        m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
284                                        M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
285        m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
286                                        M360_MEMC_BR_V;
287
288        /* flash rom socket U6 on CS5 */
289        m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
290                                                                M360_MEMC_BR_V;
291        m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
292                                                                M360_MEMC_OR_8BIT;
293
294        /* CSRs on CS7 */
295        m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
296                                        M360_MEMC_OR_8BIT;
297        m360.memc[7].br = ATLASHSB_ESR | 0x01;
298        for (i = 0; i < 50000; i++)
299                continue;
300        for (i = 0; i < 8; ++i)
301                *((volatile unsigned long *)(unsigned long)&_RamBase);
302
303        /*
304         * Step 13: Copy  the exception vector table to system RAM
305         */
306        m68k_get_vbr (vbr);
307        for (i = 0; i < 256; ++i)
308                M68Kvec[i] = vbr[i];
309        m68k_set_vbr (M68Kvec);
[6128a4a]310
[d54de3f]311        /*
312         * Step 14: More system initialization
313         * SDCR (Serial DMA configuration register)
314         *      Enable SDMA during FREEZE
315         *      Give SDMA priority over all interrupt handlers
316         *      Set DMA arbiration level to 4
317         * CICR (CPM interrupt configuration register):
318         *      SCC1 requests at SCCa position
319         *      SCC2 requests at SCCb position
320         *      SCC3 requests at SCCc position
321         *      SCC4 requests at SCCd position
322         *      Interrupt request level 4
323         *      Maintain original priority order
324         *      Vector base 128
325         *      SCCs priority grouped at top of table
326         */
327        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
328        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
329                                                (4 << 13) | (0x1F << 8) | (128);
330
331        /*
332         * Step 15: Set module configuration register
333         *      Disable timers during FREEZE
334         *      Enable bus monitor during FREEZE
335         *      BCLRO* arbitration level 3
[c0ebf02]336         */
[66fe6be6]337
338#elif (defined (GEN68360_WITH_SRAM))
339   /*
340    ***************************************************
341    * Generic Standalone Motorola 68360               *
342    *           As described in MC68360 User's Manual *
343    * But uses SRAM instead of DRAM                   *
344    *  CS0* - 512kx8 flash memory                     *
345    *  CS1* - 512kx32 static RAM                      *
[df49c60]346    *  CS2* - 512kx32 static RAM                      *
[66fe6be6]347    ***************************************************
348    */
349
350   /*
351    * Step 7: Deal with clock synthesizer
352    * HARDWARE:
353    * Change if you're not using an external oscillator which
354    * oscillates at the system clock rate.
355    */
356   m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
357   m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
358                              no LPSTOP slowdown, PLL X1 */
359   m360.cdvcr = 0x8000;    /* No more writes, no clock division */
360
361   /*
362    * Step 8: Initialize system protection
363    * Enable watchdog
364    * Watchdog causes system reset
365    * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
366    * Enable double bus fault monitor
367    * Enable bus monitor for external cycles
368    * 1024 clocks for external timeout
369    */
[6128a4a]370    m360.sypcr = 0xEC;
[66fe6be6]371
372   /*
373    * Step 9: Clear parameter RAM and reset communication processor module
374    */
375   for (i = 0 ; i < 192  ; i += sizeof (long)) {
376      *((long *)((char *)&m360 + 0xC00 + i)) = 0;
377      *((long *)((char *)&m360 + 0xD00 + i)) = 0;
378      *((long *)((char *)&m360 + 0xE00 + i)) = 0;
[6128a4a]379      *((long *)((char *)&m360 + 0xF00 + i)) = 0;
380   }
[66fe6be6]381   M360ExecuteRISC (M360_CR_RST);
382
383   /*
384    * Step 10: Write PEPAR
385    * SINTOUT not used (CPU32+ mode)
386    * CF1MODE=00 (CONFIG1 input)
387    * IPIPE1*
388    * WE0* - WE3*
389    * OE* output
390    * CAS2* - CAS3*
391    * CAS0* - CAS1*
392    * CS7*
393    * AVEC*
394    * HARDWARE:
395    * Change if you are using a different memory configuration
396    * (static RAM, external address multiplexing, etc).
397    */
398   m360.pepar = 0x0080;
399
400   /*
401    * Step 11: Set up GMR
[6128a4a]402    *
[66fe6be6]403    */
404   m360.gmr = 0x0;
405
406   /*
407    * Step 11a: Remap 512Kx8 flash memory on CS0*
[6128a4a]408    * 2 wait states
409    * Make it read-only for now
[66fe6be6]410    */
[6128a4a]411   m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
[66fe6be6]412                                                   M360_MEMC_BR_V;
413   m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
414                                                   M360_MEMC_OR_8BIT;
415   /*
416    * Step 12: Set up main memory
417    * 512Kx32 SRAM on CS1*
[df49c60]418    * 512Kx32 SRAM on CS2*
[66fe6be6]419    * 0 wait states
420    */
[df49c60]421   ramSize = 4 * 1024 * 1024;
[66fe6be6]422   m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
423   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
[6128a4a]424                                                   M360_MEMC_OR_32BIT;
[df49c60]425   m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V;
426   m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
[6128a4a]427                                                   M360_MEMC_OR_32BIT;
[66fe6be6]428   /*
429    * Step 13: Copy  the exception vector table to system RAM
430    */
431   m68k_get_vbr (vbr);
432   for (i = 0; i < 256; ++i)
433           M68Kvec[i] = vbr[i];
434   m68k_set_vbr (M68Kvec);
435
436   /*
437    * Step 14: More system initialization
438    * SDCR (Serial DMA configuration register)
439    * Enable SDMA during FREEZE
440    * Give SDMA priority over all interrupt handlers
441    * Set DMA arbiration level to 4
442    * CICR (CPM interrupt configuration register):
443    * SCC1 requests at SCCa position
444    * SCC2 requests at SCCb position
445    * SCC3 requests at SCCc position
446    * SCC4 requests at SCCd position
447    * Interrupt request level 4
448    * Maintain original priority order
449    * Vector base 128
450    * SCCs priority grouped at top of table
451    */
452   m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
453   m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
454                  (4 << 13) | (0x1F << 8) | (128);
455
456   /*
457    * Step 15: Set module configuration register
458    * Disable timers during FREEZE
459    * Enable bus monitor during FREEZE
460    * BCLRO* arbitration level 3
461    * No show cycles
462    * User/supervisor access
463    * Bus clear interrupt service level 7
464    * SIM60 interrupt sources higher priority than CPM
465    */
466   m360.mcr = 0x4C7F;
[d54de3f]467
468#else
469        /*
470         ***************************************************
471         * Generic Standalone Motorola 68360               *
472         *           As described in MC68360 User's Manual *
473         *           Atlas ACE360                          *
474         ***************************************************
475         */
476
477        /*
478         * Step 6: Is this a power-up reset?
479         * For now we just ignore this and do *all* the steps
480         * Someday we might want to:
481         *      if (Hard, Loss of Clock, Power-up)
482         *              Do all steps
483         *      else if (Double bus fault, watchdog or soft reset)
484         *              Skip to step 12
485         *      else (must be a CPU32+ reset command)
486         *              Skip to step 14
487         */
488
489        /*
490         * Step 7: Deal with clock synthesizer
491         * HARDWARE:
492         *      Change if you're not using an external 25 MHz oscillator.
493         */
494        m360.clkocr = 0x8F;     /* No more writes, no clock outputs */
495        m360.pllcr = 0xD000;    /* PLL, no writes, no prescale,
496                                   no LPSTOP slowdown, PLL X1 */
497        m360.cdvcr = 0x8000;    /* No more writes, no clock division */
498
499        /*
500         * Step 8: Initialize system protection
501         *      Enable watchdog
502         *      Watchdog causes system reset
503         *      Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
504         *      Enable double bus fault monitor
505         *      Enable bus monitor for external cycles
506         *      1024 clocks for external timeout
507         */
508        m360.sypcr = 0xEC;
509
510        /*
511         * Step 9: Clear parameter RAM and reset communication processor module
512         */
513        for (i = 0 ; i < 192  ; i += sizeof (long)) {
514                *((long *)((char *)&m360 + 0xC00 + i)) = 0;
515                *((long *)((char *)&m360 + 0xD00 + i)) = 0;
516                *((long *)((char *)&m360 + 0xE00 + i)) = 0;
517                *((long *)((char *)&m360 + 0xF00 + i)) = 0;
518        }
519        M360ExecuteRISC (M360_CR_RST);
520
521        /*
522         * Step 10: Write PEPAR
523         *      SINTOUT not used (CPU32+ mode)
524         *      CF1MODE=00 (CONFIG1 input)
525         *      RAS1* double drive
526         *      WE0* - WE3*
527         *      OE* output
528         *      CAS2* - CAS3*
529         *      CAS0* - CAS1*
530         *      CS7*
531         *      AVEC*
532         * HARDWARE:
533         *      Change if you are using a different memory configuration
534         *      (static RAM, external address multiplexing, etc).
535         */
536        m360.pepar = 0x0180;
537
538        /*
539         * Step 11: Remap Chip Select 0 (CS0*), set up GMR
[98bcbda3]540         *      32-bit DRAM
541         *      Internal DRAM address multiplexing
542         *      60 nsec DRAM
543         *      180 nsec ROM (3 wait states)
544         *      15.36 usec DRAM refresh interval
545         *      The DRAM page size selection is not modified since this
546         *      startup code may be running in a bootstrap PROM or in
547         *      a program downloaded by the bootstrap PROM.
548         */
[6128a4a]549        m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
550                                        M360_GMR_RFEN | M360_GMR_RCYC(0) |
551                                        M360_GMR_DPS_32BIT | M360_GMR_NCS |
[d54de3f]552                                        M360_GMR_GAMX;
553        m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
554                                                                M360_MEMC_BR_V;
555        m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
556                                                        M360_MEMC_OR_8BIT;
557
558        /*
559         * Step 12: Initialize the system RAM
[98bcbda3]560         * Do this only if the DRAM has not already been set up
561         */
562        if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
563                /*
564                 * Set up GMR DRAM page size, option and  base registers
565                 *      Assume 16Mbytes of DRAM
566                 *      60 nsec DRAM
567                 */
568                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
[d54de3f]569                m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
[98bcbda3]570                                                M360_MEMC_OR_16MB |
571                                                M360_MEMC_OR_DRAM;
572                m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
573
574                /*
575                 * Wait for chips to power up
576                 *      Perform 8 read cycles
577                 */
578                for (i = 0; i < 50000; i++)
579                        continue;
580                for (i = 0; i < 8; ++i)
581                        *((volatile unsigned long *)(unsigned long)&_RamBase);
582
583                /*
584                 * Determine memory size (1, 4, or 16 Mbytes)
585                 * Set GMR DRAM page size appropriately.
586                 * The OR is left at 16 Mbytes.  The bootstrap PROM places its
587                 * .data and .bss segments at the top of the 16 Mbyte space.
588                 * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
589                 * the memory map, but will work with the same bootstrap PROM.
590                 */
591                *(volatile char *)&_RamBase = 0;
592                *((volatile char *)&_RamBase+0x00C01800) = 1;
593                if (*(volatile char *)&_RamBase) {
594                        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
595                }
596                else {
597                        *((volatile char *)&_RamBase+0x00801000) = 1;
598                        if (*(volatile char *)&_RamBase) {
599                                m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
600                        }
601                }
602
603                /*
604                 * Enable parity checking
605                 */
606                m360.memc[1].br |= M360_MEMC_BR_PAREN;
[d54de3f]607        }
[c0ebf02]608        switch (m360.gmr & 0x001C0000) {
609        default:                ramSize =  4 * 1024 * 1024;     break;
610        case M360_GMR_PGS(1):   ramSize =  1 * 1024 * 1024;     break;
611        case M360_GMR_PGS(3):   ramSize =  4 * 1024 * 1024;     break;
612        case M360_GMR_PGS(5):   ramSize = 16 * 1024 * 1024;     break;
613        }
[d54de3f]614
615        /*
616         * Step 13: Copy  the exception vector table to system RAM
617         */
618        m68k_get_vbr (vbr);
619        for (i = 0; i < 256; ++i)
620                M68Kvec[i] = vbr[i];
621        m68k_set_vbr (M68Kvec);
[6128a4a]622
[d54de3f]623        /*
624         * Step 14: More system initialization
625         * SDCR (Serial DMA configuration register)
626         *      Enable SDMA during FREEZE
627         *      Give SDMA priority over all interrupt handlers
628         *      Set DMA arbiration level to 4
629         * CICR (CPM interrupt configuration register):
630         *      SCC1 requests at SCCa position
631         *      SCC2 requests at SCCb position
632         *      SCC3 requests at SCCc position
633         *      SCC4 requests at SCCd position
634         *      Interrupt request level 4
635         *      Maintain original priority order
636         *      Vector base 128
637         *      SCCs priority grouped at top of table
638         */
639        m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
640        m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
641                                                (4 << 13) | (0x1F << 8) | (128);
642
643        /*
644         * Step 15: Set module configuration register
645         *      Disable timers during FREEZE
646         *      Enable bus monitor during FREEZE
647         *      BCLRO* arbitration level 3
648         *      No show cycles
649         *      User/supervisor access
650         *      Bus clear interrupt service level 7
651         *      SIM60 interrupt sources higher priority than CPM
652         */
653        m360.mcr = 0x4C7F;
654#endif
655
656        /*
657         * Copy data, clear BSS, switch stacks and call main()
[c0ebf02]658         * Must pass ramSize as argument since the data/bss segment
659         * may be overwritten.
[d54de3f]660         */
[c0ebf02]661        _CopyDataClearBSSAndStart (ramSize);
[d54de3f]662}
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