| 1 | /* |
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| 2 | * This file contains the entry point for the application. |
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| 3 | * The name of this entry point is compiler dependent. |
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| 4 | * It jumps to the BSP which is responsible for performing |
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| 5 | * all initialization. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1998. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * Copyright assigned to U.S. Government, 1994. |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may in |
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| 12 | * the file LICENSE in this distribution or at |
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| 13 | * http://www.OARcorp.com/rtems/license.html. |
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| 14 | * |
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| 15 | * Based on the `gen68360' board support package, and covered by the |
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| 16 | * original distribution terms. |
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| 17 | * |
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| 18 | * Geoffroy Montel |
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| 19 | * France Telecom - CNET/DSM/TAM/CAT |
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| 20 | * 4, rue du Clos Courtel |
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| 21 | * 35512 CESSON-SEVIGNE |
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| 22 | * FRANCE |
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| 23 | * |
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| 24 | * e-mail: g_montel@yahoo.com |
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| 25 | * |
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| 26 | * $Id$ |
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| 27 | */ |
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| 28 | |
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| 29 | #include "asm.h" |
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| 30 | #include <m68340.inc> |
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| 31 | |
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| 32 | BEGIN_CODE |
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| 33 | /* |
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| 34 | * Step 1: Decide on Reset Stack Pointer and Initial Program Counter |
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| 35 | */ |
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| 36 | Entry: |
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| 37 | .long SYM(m340)+1024 | 0: Initial SSP |
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| 38 | .long start | 1: Initial PC |
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| 39 | .long SYM(_uhoh) | 2: Bus error |
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| 40 | .long SYM(_uhoh) | 3: Address error |
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| 41 | .long SYM(_uhoh) | 4: Illegal instruction |
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| 42 | .long SYM(_uhoh) | 5: Zero division |
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| 43 | .long SYM(_uhoh) | 6: CHK, CHK2 instruction |
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| 44 | .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions |
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| 45 | .long SYM(_uhoh) | 8: Privilege violation |
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| 46 | .long SYM(_uhoh) | 9: Trace |
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| 47 | .long SYM(_uhoh) | 10: Line 1010 emulator |
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| 48 | .long SYM(_uhoh) | 11: Line 1111 emulator |
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| 49 | .long SYM(_uhoh) | 12: Hardware breakpoint |
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| 50 | .long SYM(_uhoh) | 13: Reserved for coprocessor violation |
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| 51 | .long SYM(_uhoh) | 14: Format error |
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| 52 | .long SYM(_uhoh) | 15: Uninitialized interrupt |
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| 53 | .long SYM(_uhoh) | 16: Unassigned, reserved |
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| 54 | .long SYM(_uhoh) | 17: |
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| 55 | .long SYM(_uhoh) | 18: |
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| 56 | .long SYM(_uhoh) | 19: |
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| 57 | .long SYM(_uhoh) | 20: |
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| 58 | .long SYM(_uhoh) | 21: |
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| 59 | .long SYM(_uhoh) | 22: |
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| 60 | .long SYM(_uhoh) | 23: |
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| 61 | .long SYM(_spuriousInterrupt) | 24: Spurious interrupt |
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| 62 | .long SYM(_uhoh) | 25: Level 1 interrupt autovector |
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| 63 | .long SYM(_uhoh) | 26: Level 2 interrupt autovector |
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| 64 | .long SYM(_uhoh) | 27: Level 3 interrupt autovector |
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| 65 | .long SYM(_uhoh) | 28: Level 4 interrupt autovector |
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| 66 | .long SYM(_uhoh) | 29: Level 5 interrupt autovector |
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| 67 | .long SYM(_uhoh) | 30: Level 6 interrupt autovector |
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| 68 | .long SYM(_uhoh) | 31: Level 7 interrupt autovector |
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| 69 | .long SYM(_uhoh) | 32: Trap instruction (0-15) |
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| 70 | .long SYM(_uhoh) | 33: |
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| 71 | .long SYM(_uhoh) | 34: |
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| 72 | .long SYM(_uhoh) | 35: |
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| 73 | .long SYM(_uhoh) | 36: |
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| 74 | .long SYM(_uhoh) | 37: |
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| 75 | .long SYM(_uhoh) | 38: |
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| 76 | .long SYM(_uhoh) | 39: |
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| 77 | .long SYM(_uhoh) | 40: |
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| 78 | .long SYM(_uhoh) | 41: |
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| 79 | .long SYM(_uhoh) | 42: |
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| 80 | .long SYM(_uhoh) | 43: |
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| 81 | .long SYM(_uhoh) | 44: |
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| 82 | .long SYM(_uhoh) | 45: |
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| 83 | .long SYM(_uhoh) | 46: |
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| 84 | .long SYM(_uhoh) | 47: |
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| 85 | .long SYM(_uhoh) | 48: Reserved for coprocessor |
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| 86 | .long SYM(_uhoh) | 49: |
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| 87 | .long SYM(_uhoh) | 50: |
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| 88 | .long SYM(_uhoh) | 51: |
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| 89 | .long SYM(_uhoh) | 52: |
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| 90 | .long SYM(_uhoh) | 53: |
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| 91 | .long SYM(_uhoh) | 54: |
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| 92 | .long SYM(_uhoh) | 55: |
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| 93 | .long SYM(_uhoh) | 56: |
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| 94 | .long SYM(_uhoh) | 57: |
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| 95 | .long SYM(_uhoh) | 58: |
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| 96 | .long SYM(_uhoh) | 59: Unassigned, reserved |
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| 97 | .long SYM(_uhoh) | 60: |
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| 98 | .long SYM(_uhoh) | 61: |
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| 99 | .long SYM(_uhoh) | 62: |
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| 100 | .long SYM(_uhoh) | 63: |
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| 101 | .long SYM(_uhoh) | 64: User defined vectors (192) |
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| 102 | .long SYM(_uhoh) | 65: |
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| 103 | .long SYM(_uhoh) | 66: |
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| 104 | .long SYM(_uhoh) | 67: |
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| 105 | .long SYM(_uhoh) | 68: |
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| 106 | .long SYM(_uhoh) | 69: |
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| 107 | .long SYM(_uhoh) | 70: |
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| 108 | .long SYM(_uhoh) | 71: |
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| 109 | .long SYM(_uhoh) | 72: |
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| 110 | .long SYM(_uhoh) | 73: |
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| 111 | .long SYM(_uhoh) | 74: |
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| 112 | .long SYM(_uhoh) | 75: |
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| 113 | .long SYM(_uhoh) | 76: |
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| 114 | .long SYM(_uhoh) | 77: |
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| 115 | .long SYM(_uhoh) | 78: |
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| 116 | .long SYM(_uhoh) | 79: |
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| 117 | .long SYM(_uhoh) | 80: |
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| 118 | .long SYM(_uhoh) | 81: |
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| 119 | .long SYM(_uhoh) | 82: |
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| 120 | .long SYM(_uhoh) | 83: |
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| 121 | .long SYM(_uhoh) | 84: |
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| 122 | .long SYM(_uhoh) | 85: |
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| 123 | .long SYM(_uhoh) | 86: |
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| 124 | .long SYM(_uhoh) | 87: |
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| 125 | .long SYM(_uhoh) | 88: |
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| 126 | .long SYM(_uhoh) | 89: |
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| 127 | .long SYM(_uhoh) | 90: |
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| 128 | .long SYM(_uhoh) | 91: |
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| 129 | .long SYM(_uhoh) | 92: |
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| 130 | .long SYM(_uhoh) | 93: |
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| 131 | .long SYM(_uhoh) | 94: |
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| 132 | .long SYM(_uhoh) | 95: |
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| 133 | .long SYM(_uhoh) | 96: |
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| 134 | .long SYM(_uhoh) | 97: |
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| 135 | .long SYM(_uhoh) | 98: |
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| 136 | .long SYM(_uhoh) | 99: |
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| 137 | .long SYM(_uhoh) | 100: |
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| 138 | .long SYM(_uhoh) | 101: |
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| 139 | .long SYM(_uhoh) | 102: |
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| 140 | .long SYM(_uhoh) | 103: |
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| 141 | .long SYM(_uhoh) | 104: |
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| 142 | .long SYM(_uhoh) | 105: |
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| 143 | .long SYM(_uhoh) | 106: |
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| 144 | .long SYM(_uhoh) | 107: |
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| 145 | .long SYM(_uhoh) | 108: |
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| 146 | .long SYM(_uhoh) | 109: |
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| 147 | .long SYM(_uhoh) | 110: |
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| 148 | .long SYM(_uhoh) | 111: |
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| 149 | .long SYM(_uhoh) | 112: |
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| 150 | .long SYM(_uhoh) | 113: |
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| 151 | .long SYM(_uhoh) | 114: |
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| 152 | .long SYM(_uhoh) | 115: |
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| 153 | .long SYM(_uhoh) | 116: |
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| 154 | .long SYM(_uhoh) | 117: |
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| 155 | .long SYM(_uhoh) | 118: |
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| 156 | .long SYM(_uhoh) | 119: |
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| 157 | .long SYM(_uhoh) | 120: |
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| 158 | .long SYM(_uhoh) | 121: |
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| 159 | .long SYM(_uhoh) | 122: |
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| 160 | .long SYM(_uhoh) | 123: |
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| 161 | .long SYM(_uhoh) | 124: |
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| 162 | .long SYM(_uhoh) | 125: |
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| 163 | .long SYM(_uhoh) | 126: |
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| 164 | .long SYM(_uhoh) | 127: |
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| 165 | .long SYM(_uhoh) | 128: |
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| 166 | .long SYM(_uhoh) | 129: |
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| 167 | .long SYM(_uhoh) | 130: |
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| 168 | .long SYM(_uhoh) | 131: |
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| 169 | .long SYM(_uhoh) | 132: |
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| 170 | .long SYM(_uhoh) | 133: |
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| 171 | .long SYM(_uhoh) | 134: |
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| 172 | .long SYM(_uhoh) | 135: |
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| 173 | .long SYM(_uhoh) | 136: |
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| 174 | .long SYM(_uhoh) | 137: |
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| 175 | .long SYM(_uhoh) | 138: |
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| 176 | .long SYM(_uhoh) | 139: |
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| 177 | .long SYM(_uhoh) | 140: |
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| 178 | .long SYM(_uhoh) | 141: |
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| 179 | .long SYM(_uhoh) | 142: |
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| 180 | .long SYM(_uhoh) | 143: |
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| 181 | .long SYM(_uhoh) | 144: |
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| 182 | .long SYM(_uhoh) | 145: |
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| 183 | .long SYM(_uhoh) | 146: |
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| 184 | .long SYM(_uhoh) | 147: |
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| 185 | .long SYM(_uhoh) | 148: |
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| 186 | .long SYM(_uhoh) | 149: |
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| 187 | .long SYM(_uhoh) | 150: |
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| 188 | .long SYM(_uhoh) | 151: |
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| 189 | .long SYM(_uhoh) | 152: |
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| 190 | .long SYM(_uhoh) | 153: |
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| 191 | .long SYM(_uhoh) | 154: |
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| 192 | .long SYM(_uhoh) | 155: |
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| 193 | .long SYM(_uhoh) | 156: |
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| 194 | .long SYM(_uhoh) | 157: |
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| 195 | .long SYM(_uhoh) | 158: |
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| 196 | .long SYM(_uhoh) | 159: |
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| 197 | .long SYM(_uhoh) | 160: |
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| 198 | .long SYM(_uhoh) | 161: |
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| 199 | .long SYM(_uhoh) | 162: |
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| 200 | .long SYM(_uhoh) | 163: |
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| 201 | .long SYM(_uhoh) | 164: |
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| 202 | .long SYM(_uhoh) | 165: |
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| 203 | .long SYM(_uhoh) | 166: |
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| 204 | .long SYM(_uhoh) | 167: |
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| 205 | .long SYM(_uhoh) | 168: |
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| 206 | .long SYM(_uhoh) | 169: |
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| 207 | .long SYM(_uhoh) | 170: |
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| 208 | .long SYM(_uhoh) | 171: |
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| 209 | .long SYM(_uhoh) | 172: |
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| 210 | .long SYM(_uhoh) | 173: |
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| 211 | .long SYM(_uhoh) | 174: |
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| 212 | .long SYM(_uhoh) | 175: |
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| 213 | .long SYM(_uhoh) | 176: |
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| 214 | .long SYM(_uhoh) | 177: |
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| 215 | .long SYM(_uhoh) | 178: |
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| 216 | .long SYM(_uhoh) | 179: |
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| 217 | .long SYM(_uhoh) | 180: |
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| 218 | .long SYM(_uhoh) | 181: |
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| 219 | .long SYM(_uhoh) | 182: |
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| 220 | .long SYM(_uhoh) | 183: |
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| 221 | .long SYM(_uhoh) | 184: |
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| 222 | .long SYM(_uhoh) | 185: |
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| 223 | .long SYM(_uhoh) | 186: |
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| 224 | .long SYM(_uhoh) | 187: |
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| 225 | .long SYM(_uhoh) | 188: |
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| 226 | .long SYM(_uhoh) | 189: |
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| 227 | .long SYM(_uhoh) | 190: |
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| 228 | .long SYM(_uhoh) | 191: |
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| 229 | .long SYM(_uhoh) | 192: |
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| 230 | .long SYM(_uhoh) | 193: |
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| 231 | .long SYM(_uhoh) | 194: |
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| 232 | .long SYM(_uhoh) | 195: |
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| 233 | .long SYM(_uhoh) | 196: |
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| 234 | .long SYM(_uhoh) | 197: |
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| 235 | .long SYM(_uhoh) | 198: |
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| 236 | .long SYM(_uhoh) | 199: |
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| 237 | .long SYM(_uhoh) | 200: |
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| 238 | .long SYM(_uhoh) | 201: |
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| 239 | .long SYM(_uhoh) | 202: |
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| 240 | .long SYM(_uhoh) | 203: |
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| 241 | .long SYM(_uhoh) | 204: |
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| 242 | .long SYM(_uhoh) | 205: |
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| 243 | .long SYM(_uhoh) | 206: |
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| 244 | .long SYM(_uhoh) | 207: |
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| 245 | .long SYM(_uhoh) | 208: |
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| 246 | .long SYM(_uhoh) | 209: |
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| 247 | .long SYM(_uhoh) | 210: |
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| 248 | .long SYM(_uhoh) | 211: |
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| 249 | .long SYM(_uhoh) | 212: |
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| 250 | .long SYM(_uhoh) | 213: |
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| 251 | .long SYM(_uhoh) | 214: |
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| 252 | .long SYM(_uhoh) | 215: |
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| 253 | .long SYM(_uhoh) | 216: |
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| 254 | .long SYM(_uhoh) | 217: |
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| 255 | .long SYM(_uhoh) | 218: |
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| 256 | .long SYM(_uhoh) | 219: |
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| 257 | .long SYM(_uhoh) | 220: |
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| 258 | .long SYM(_uhoh) | 221: |
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| 259 | .long SYM(_uhoh) | 222: |
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| 260 | .long SYM(_uhoh) | 223: |
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| 261 | .long SYM(_uhoh) | 224: |
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| 262 | .long SYM(_uhoh) | 225: |
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| 263 | .long SYM(_uhoh) | 226: |
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| 264 | .long SYM(_uhoh) | 227: |
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| 265 | .long SYM(_uhoh) | 228: |
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| 266 | .long SYM(_uhoh) | 229: |
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| 267 | .long SYM(_uhoh) | 230: |
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| 268 | .long SYM(_uhoh) | 231: |
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| 269 | .long SYM(_uhoh) | 232: |
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| 270 | .long SYM(_uhoh) | 233: |
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| 271 | .long SYM(_uhoh) | 234: |
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| 272 | .long SYM(_uhoh) | 235: |
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| 273 | .long SYM(_uhoh) | 236: |
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| 274 | .long SYM(_uhoh) | 237: |
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| 275 | .long SYM(_uhoh) | 238: |
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| 276 | .long SYM(_uhoh) | 239: |
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| 277 | .long SYM(_uhoh) | 240: |
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| 278 | .long SYM(_uhoh) | 241: |
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| 279 | .long SYM(_uhoh) | 242: |
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| 280 | .long SYM(_uhoh) | 243: |
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| 281 | .long SYM(_uhoh) | 244: |
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| 282 | .long SYM(_uhoh) | 245: |
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| 283 | .long SYM(_uhoh) | 246: |
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| 284 | .long SYM(_uhoh) | 247: |
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| 285 | .long SYM(_uhoh) | 248: |
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| 286 | .long SYM(_uhoh) | 249: |
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| 287 | .long SYM(_uhoh) | 250: |
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| 288 | .long SYM(_uhoh) | 251: |
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| 289 | .long SYM(_uhoh) | 252: |
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| 290 | .long SYM(_uhoh) | 253: |
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| 291 | .long SYM(_uhoh) | 254: |
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| 292 | .long SYM(_uhoh) | 255: |
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| 293 | |
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| 294 | /* |
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| 295 | * Default trap handler |
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| 296 | * With an oscilloscope you can see AS* stop |
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| 297 | */ |
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| 298 | PUBLIC (_uhoh) |
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| 299 | SYM(_uhoh): nop | Leave spot for breakpoint |
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| 300 | stop #0x2700 | Stop with interrupts disabled |
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| 301 | bra.s SYM(_uhoh) | Stuck forever |
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| 302 | |
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| 303 | /* |
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| 304 | * Log, but otherwise ignore, spurious interrupts |
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| 305 | */ |
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| 306 | PUBLIC (_spuriousInterrupt) |
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| 307 | SYM(_spuriousInterrupt): |
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| 308 | addql #1,SYM(_M68kSpuriousInterruptCount) |
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| 309 | rte |
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| 310 | |
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| 311 | /* |
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| 312 | * Place the low-order 3 octets of the board's ethernet address at |
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| 313 | * a `well-known' fixed location relative to the startup location. |
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| 314 | */ |
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| 315 | .align 2 |
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| 316 | .word 0 | Padding |
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| 317 | ethernet_address_buffer: |
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| 318 | .word 0x08F3 | Default address |
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| 319 | .word 0xDEAD |
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| 320 | .word 0xCAFE |
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| 321 | |
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| 322 | /* -- equates -- */ |
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| 323 | .equ _PROM_Start, 0x01000000 /* CS0 */ |
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| 324 | .equ _BCCram_Start, 0x00000000 /* CS1 */ |
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| 325 | .equ _FLEX_Start, 0x08000000 /* CS2 */ |
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| 326 | .equ _I2C_Start, 0x02000000 /* CS3 */ |
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| 327 | .equ _EXTram_Start, 0x10000000 /* CS4 */ |
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| 328 | .equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ |
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| 329 | .equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ |
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| 330 | /* .equ _SPEED, 0xD700 25 Mhz */ |
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| 331 | /* .equ _SPEED, 0xCE00 16 Mhz */ |
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| 332 | |
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| 333 | BEGIN_DATA |
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| 334 | |
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| 335 | _crt0_init_stack: |
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| 336 | ds.l 0x1000 |
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| 337 | _crt0_init_stktop: |
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| 338 | |
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| 339 | |
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| 340 | BEGIN_CODE |
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| 341 | dc.l _crt0_init_stktop /* reset SP */ |
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| 342 | dc.l _crt0_cold_start /* reset PC */ |
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| 343 | dc.l _crt0_warm_start |
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| 344 | |
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| 345 | .ascii "BOOT XHM68K/Spectra for ASTECC PLATFORM" |
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| 346 | dc.w 0 |
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| 347 | |
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| 348 | .align 2 |
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| 349 | |
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| 350 | _table_cs: |
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| 351 | /* carte Astecc - 68340 */ |
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| 352 | dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ |
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| 353 | /* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ |
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| 354 | dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ |
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| 355 | /* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ |
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| 356 | dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ |
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| 357 | /* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ |
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| 358 | dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ |
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| 359 | dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ |
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| 360 | dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ |
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| 361 | dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ |
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| 362 | dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ |
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| 363 | |
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| 364 | /* |
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| 365 | * Initial PC |
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| 366 | */ |
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| 367 | .globl start |
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| 368 | start: |
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| 369 | |
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| 370 | _crt0_cold_start: |
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| 371 | moveq.l #0,d0 /* signal cold reset */ |
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| 372 | bra.s _crt0_common_start |
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| 373 | |
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| 374 | _crt0_warm_start: |
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| 375 | moveq.l #1,d0 /* signal warm reset */ |
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| 376 | |
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| 377 | _crt0_common_start: |
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| 378 | move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ |
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| 379 | movea.l #_crt0_init_stktop,sp /* set up initialization stack */ |
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| 380 | |
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| 381 | lea Entry,a0 /* Get base of vector table */ |
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| 382 | movec a0,vbr /* Set up the VBR */ |
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| 383 | |
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| 384 | moveq.l #0x07,d1 |
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| 385 | movec.l d1,dfc /* prepare access in CPU space */ |
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| 386 | move.l #(BASE_SIM+1),d1 |
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| 387 | moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ |
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| 388 | moveq.l #0x05,d1 |
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| 389 | movec.l d1,dfc |
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| 390 | |
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| 391 | movea.l #BASE_SIM,a0 |
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| 392 | |
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| 393 | /* -- disable Bus Monitor -- */ |
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| 394 | move.b #0,SIM_SYPCR(a0) /* system protection control register */ |
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| 395 | |
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| 396 | /* -- set frequency to 25.16 Mhz -- */ |
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| 397 | move.w #_SPEED,SIM_SYNCR(a0) /* clock */ |
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| 398 | |
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| 399 | sync_wait: |
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| 400 | btst.b #3,(SIM_SYNCR+1)(a0) |
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| 401 | beq sync_wait |
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| 402 | |
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| 403 | /* -- enable A31-A24 -- */ |
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| 404 | clr.b SIM_PPRA1(a0) |
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| 405 | |
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| 406 | /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ |
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| 407 | move.w #0x427F,SIM_MCR(a0) |
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| 408 | |
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| 409 | /* -- chip select initialization -- */ |
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| 410 | lea.l SIM_MASKH0(a0),a2 |
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| 411 | lea.l _table_cs(%pc),a1 |
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| 412 | |
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| 413 | moveq.l #0x07,d1 |
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| 414 | |
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| 415 | _b_cs: |
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| 416 | /* move.l (a1)+, (a2)+ */ |
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| 417 | move.l (a1)+, d2 |
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| 418 | move.l d2, (a2)+ |
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| 419 | dbra d1,_b_cs |
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| 420 | |
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| 421 | /* fill RAM if COLDSTART */ |
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| 422 | tst.l d0 |
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| 423 | bne _dont_fill |
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| 424 | |
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| 425 | movea.l #_EXTram_Start,a0 /* get start */ |
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| 426 | move.l #_EXTram_Size,d1 /* get size */ |
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| 427 | lsr.l #2,d1 /* ajust for long word */ |
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| 428 | |
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| 429 | _fill_loop: |
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| 430 | clr.l (a0)+ |
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| 431 | subq.l #1,d1 |
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| 432 | bne _fill_loop |
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| 433 | |
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| 434 | /* jsr __initcopy */ |
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| 435 | |
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| 436 | _dont_fill: |
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| 437 | jmp SYM(_Init68340) | Start C code (which never returns) |
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| 438 | |
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| 439 | /* |
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| 440 | * Copy DATA segment, clear BSS segment, set up real stack, |
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| 441 | * initialize heap, start C program. |
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| 442 | * Assume that DATA and BSS sizes are multiples of 4. |
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| 443 | */ |
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| 444 | PUBLIC (_CopyDataClearBSSAndStart) |
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| 445 | SYM(_CopyDataClearBSSAndStart): |
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| 446 | lea copy_start,a0 | Get start of DATA in RAM |
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| 447 | lea SYM(etext),a2 | Get start of DATA in ROM |
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| 448 | cmpl a0,a2 | Are they the same? |
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| 449 | beq.s NOCOPY | Yes, no copy necessary |
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| 450 | lea copy_end,a1 | Get end of DATA in RAM |
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| 451 | bra.s COPYLOOPTEST | Branch into copy loop |
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| 452 | COPYLOOP: |
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| 453 | movel a2@+,a0@+ | Copy word from ROM to RAM |
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| 454 | COPYLOOPTEST: |
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| 455 | cmpl a1,a0 | Done? |
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| 456 | bcs.s COPYLOOP | No, skip |
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| 457 | NOCOPY: |
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| 458 | |
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| 459 | lea clear_start,a0 | Get start of BSS |
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| 460 | lea clear_end,a1 | Get end of BSS |
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| 461 | clrl d0 | Value to set |
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| 462 | bra.s ZEROLOOPTEST | Branch into clear loop |
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| 463 | ZEROLOOP: |
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| 464 | movel d0,a0@+ | Clear a word |
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| 465 | ZEROLOOPTEST: |
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| 466 | cmpl a1,a0 | Done? |
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| 467 | bcs.s ZEROLOOP | No, skip |
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| 468 | |
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| 469 | movel #stack_init,a7 | set master stack pointer |
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| 470 | movel d0,a7@- | environp |
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| 471 | movel d0,a7@- | argv |
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| 472 | movel d0,a7@- | argc |
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| 473 | jsr SYM(boot_card) | Call C main |
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| 474 | |
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| 475 | PUBLIC (_mainDone) |
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| 476 | SYM(_mainDone): |
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| 477 | nop | Leave spot for breakpoint |
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| 478 | movew #1,a7 | Force a double bus error |
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| 479 | movel d0,a7@- | This should cause a RESET |
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| 480 | stop #0x2700 | Stop with interrupts disabled |
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| 481 | bra.s SYM(_mainDone) | Stuck forever |
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| 482 | |
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| 483 | .align 2 |
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| 484 | PUBLIC (_HeapSize) |
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| 485 | SYM (_HeapSize): |
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| 486 | .long HeapSize |
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| 487 | PUBLIC (_StackSize) |
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| 488 | SYM (_StackSize): |
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| 489 | .long StackSize |
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| 490 | END_CODE |
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| 491 | |
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| 492 | BEGIN_DATA_DCL |
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| 493 | .align 2 |
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| 494 | PUBLIC (environ) |
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| 495 | SYM (environ): |
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| 496 | .long 0 |
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| 497 | PUBLIC (_M68kSpuriousInterruptCount) |
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| 498 | SYM (_M68kSpuriousInterruptCount): |
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| 499 | .long 0 |
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| 500 | END_DATA_DCL |
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| 501 | |
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| 502 | END |
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| 503 | |
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