| 1 | /* |
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| 2 | * This file contains the entry point for the application. |
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| 3 | * The name of this entry point is compiler dependent. |
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| 4 | * It jumps to the BSP which is responsible for performing |
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| 5 | * all initialization. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1998. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * Copyright assigned to U.S. Government, 1994. |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may in |
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| 12 | * the file LICENSE in this distribution or at |
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| 13 | * http://www.OARcorp.com/rtems/license.html. |
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| 14 | * |
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| 15 | * Based on the `gen68360' board support package, and covered by the |
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| 16 | * original distribution terms. |
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| 17 | * |
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| 18 | * Geoffroy Montel |
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| 19 | * France Telecom - CNET/DSM/TAM/CAT |
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| 20 | * 4, rue du Clos Courtel |
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| 21 | * 35512 CESSON-SEVIGNE |
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| 22 | * FRANCE |
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| 23 | * |
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| 24 | * e-mail: g_montel@yahoo.com |
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| 25 | * |
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| 26 | * $Id$ |
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| 27 | */ |
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| 28 | |
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| 29 | #include "asm.h" |
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| 30 | #include <m68349.inc> |
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| 31 | |
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| 32 | #define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ |
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| 33 | |
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| 34 | BEGIN_CODE |
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| 35 | /* |
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| 36 | * Step 1: Decide on Reset Stack Pointer and Initial Program Counter |
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| 37 | */ |
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| 38 | Entry: |
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| 39 | .long SYM(m340)+1024 | 0: Initial SSP |
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| 40 | .long start | 1: Initial PC |
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| 41 | .long SYM(_uhoh) | 2: Bus error |
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| 42 | .long SYM(_uhoh) | 3: Address error |
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| 43 | .long SYM(_uhoh) | 4: Illegal instruction |
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| 44 | .long SYM(_uhoh) | 5: Zero division |
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| 45 | .long SYM(_uhoh) | 6: CHK, CHK2 instruction |
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| 46 | .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions |
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| 47 | .long SYM(_uhoh) | 8: Privilege violation |
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| 48 | .long SYM(_uhoh) | 9: Trace |
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| 49 | .long SYM(_uhoh) | 10: Line 1010 emulator |
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| 50 | .long SYM(_uhoh) | 11: Line 1111 emulator |
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| 51 | .long SYM(_uhoh) | 12: Hardware breakpoint |
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| 52 | .long SYM(_uhoh) | 13: Reserved for coprocessor violation |
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| 53 | .long SYM(_uhoh) | 14: Format error |
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| 54 | .long SYM(_uhoh) | 15: Uninitialized interrupt |
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| 55 | .long SYM(_uhoh) | 16: Unassigned, reserved |
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| 56 | .long SYM(_uhoh) | 17: |
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| 57 | .long SYM(_uhoh) | 18: |
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| 58 | .long SYM(_uhoh) | 19: |
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| 59 | .long SYM(_uhoh) | 20: |
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| 60 | .long SYM(_uhoh) | 21: |
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| 61 | .long SYM(_uhoh) | 22: |
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| 62 | .long SYM(_uhoh) | 23: |
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| 63 | .long SYM(_spuriousInterrupt) | 24: Spurious interrupt |
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| 64 | .long SYM(_uhoh) | 25: Level 1 interrupt autovector |
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| 65 | .long SYM(_uhoh) | 26: Level 2 interrupt autovector |
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| 66 | .long SYM(_uhoh) | 27: Level 3 interrupt autovector |
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| 67 | .long SYM(_uhoh) | 28: Level 4 interrupt autovector |
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| 68 | .long SYM(_uhoh) | 29: Level 5 interrupt autovector |
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| 69 | .long SYM(_uhoh) | 30: Level 6 interrupt autovector |
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| 70 | .long SYM(_uhoh) | 31: Level 7 interrupt autovector |
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| 71 | .long SYM(_uhoh) | 32: Trap instruction (0-15) |
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| 72 | .long SYM(_uhoh) | 33: |
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| 73 | .long SYM(_uhoh) | 34: |
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| 74 | .long SYM(_uhoh) | 35: |
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| 75 | .long SYM(_uhoh) | 36: |
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| 76 | .long SYM(_uhoh) | 37: |
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| 77 | .long SYM(_uhoh) | 38: |
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| 78 | .long SYM(_uhoh) | 39: |
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| 79 | .long SYM(_uhoh) | 40: |
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| 80 | .long SYM(_uhoh) | 41: |
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| 81 | .long SYM(_uhoh) | 42: |
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| 82 | .long SYM(_uhoh) | 43: |
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| 83 | .long SYM(_uhoh) | 44: |
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| 84 | .long SYM(_uhoh) | 45: |
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| 85 | .long SYM(_uhoh) | 46: |
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| 86 | .long SYM(_uhoh) | 47: |
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| 87 | .long SYM(_uhoh) | 48: Reserved for coprocessor |
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| 88 | .long SYM(_uhoh) | 49: |
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| 89 | .long SYM(_uhoh) | 50: |
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| 90 | .long SYM(_uhoh) | 51: |
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| 91 | .long SYM(_uhoh) | 52: |
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| 92 | .long SYM(_uhoh) | 53: |
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| 93 | .long SYM(_uhoh) | 54: |
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| 94 | .long SYM(_uhoh) | 55: |
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| 95 | .long SYM(_uhoh) | 56: |
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| 96 | .long SYM(_uhoh) | 57: |
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| 97 | .long SYM(_uhoh) | 58: |
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| 98 | .long SYM(_uhoh) | 59: Unassigned, reserved |
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| 99 | .long SYM(_uhoh) | 60: |
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| 100 | .long SYM(_uhoh) | 61: |
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| 101 | .long SYM(_uhoh) | 62: |
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| 102 | .long SYM(_uhoh) | 63: |
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| 103 | .long SYM(_uhoh) | 64: User defined vectors (192) |
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| 104 | .long SYM(_uhoh) | 65: |
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| 105 | .long SYM(_uhoh) | 66: |
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| 106 | .long SYM(_uhoh) | 67: |
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| 107 | .long SYM(_uhoh) | 68: |
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| 108 | .long SYM(_uhoh) | 69: |
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| 109 | .long SYM(_uhoh) | 70: |
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| 110 | .long SYM(_uhoh) | 71: |
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| 111 | .long SYM(_uhoh) | 72: |
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| 112 | .long SYM(_uhoh) | 73: |
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| 113 | .long SYM(_uhoh) | 74: |
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| 114 | .long SYM(_uhoh) | 75: |
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| 115 | .long SYM(_uhoh) | 76: |
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| 116 | .long SYM(_uhoh) | 77: |
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| 117 | .long SYM(_uhoh) | 78: |
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| 118 | .long SYM(_uhoh) | 79: |
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| 119 | .long SYM(_uhoh) | 80: |
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| 120 | .long SYM(_uhoh) | 81: |
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| 121 | .long SYM(_uhoh) | 82: |
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| 122 | .long SYM(_uhoh) | 83: |
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| 123 | .long SYM(_uhoh) | 84: |
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| 124 | .long SYM(_uhoh) | 85: |
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| 125 | .long SYM(_uhoh) | 86: |
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| 126 | .long SYM(_uhoh) | 87: |
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| 127 | .long SYM(_uhoh) | 88: |
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| 128 | .long SYM(_uhoh) | 89: |
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| 129 | .long SYM(_uhoh) | 90: |
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| 130 | .long SYM(_uhoh) | 91: |
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| 131 | .long SYM(_uhoh) | 92: |
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| 132 | .long SYM(_uhoh) | 93: |
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| 133 | .long SYM(_uhoh) | 94: |
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| 134 | .long SYM(_uhoh) | 95: |
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| 135 | .long SYM(_uhoh) | 96: |
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| 136 | .long SYM(_uhoh) | 97: |
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| 137 | .long SYM(_uhoh) | 98: |
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| 138 | .long SYM(_uhoh) | 99: |
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| 139 | .long SYM(_uhoh) | 100: |
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| 140 | .long SYM(_uhoh) | 101: |
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| 141 | .long SYM(_uhoh) | 102: |
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| 142 | .long SYM(_uhoh) | 103: |
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| 143 | .long SYM(_uhoh) | 104: |
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| 144 | .long SYM(_uhoh) | 105: |
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| 145 | .long SYM(_uhoh) | 106: |
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| 146 | .long SYM(_uhoh) | 107: |
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| 147 | .long SYM(_uhoh) | 108: |
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| 148 | .long SYM(_uhoh) | 109: |
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| 149 | .long SYM(_uhoh) | 110: |
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| 150 | .long SYM(_uhoh) | 111: |
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| 151 | .long SYM(_uhoh) | 112: |
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| 152 | .long SYM(_uhoh) | 113: |
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| 153 | .long SYM(_uhoh) | 114: |
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| 154 | .long SYM(_uhoh) | 115: |
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| 155 | .long SYM(_uhoh) | 116: |
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| 156 | .long SYM(_uhoh) | 117: |
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| 157 | .long SYM(_uhoh) | 118: |
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| 158 | .long SYM(_uhoh) | 119: |
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| 159 | .long SYM(_uhoh) | 120: |
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| 160 | .long SYM(_uhoh) | 121: |
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| 161 | .long SYM(_uhoh) | 122: |
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| 162 | .long SYM(_uhoh) | 123: |
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| 163 | .long SYM(_uhoh) | 124: |
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| 164 | .long SYM(_uhoh) | 125: |
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| 165 | .long SYM(_uhoh) | 126: |
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| 166 | .long SYM(_uhoh) | 127: |
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| 167 | .long SYM(_uhoh) | 128: |
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| 168 | .long SYM(_uhoh) | 129: |
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| 169 | .long SYM(_uhoh) | 130: |
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| 170 | .long SYM(_uhoh) | 131: |
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| 171 | .long SYM(_uhoh) | 132: |
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| 172 | .long SYM(_uhoh) | 133: |
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| 173 | .long SYM(_uhoh) | 134: |
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| 174 | .long SYM(_uhoh) | 135: |
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| 175 | .long SYM(_uhoh) | 136: |
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| 176 | .long SYM(_uhoh) | 137: |
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| 177 | .long SYM(_uhoh) | 138: |
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| 178 | .long SYM(_uhoh) | 139: |
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| 179 | .long SYM(_uhoh) | 140: |
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| 180 | .long SYM(_uhoh) | 141: |
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| 181 | .long SYM(_uhoh) | 142: |
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| 182 | .long SYM(_uhoh) | 143: |
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| 183 | .long SYM(_uhoh) | 144: |
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| 184 | .long SYM(_uhoh) | 145: |
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| 185 | .long SYM(_uhoh) | 146: |
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| 186 | .long SYM(_uhoh) | 147: |
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| 187 | .long SYM(_uhoh) | 148: |
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| 188 | .long SYM(_uhoh) | 149: |
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| 189 | .long SYM(_uhoh) | 150: |
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| 190 | .long SYM(_uhoh) | 151: |
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| 191 | .long SYM(_uhoh) | 152: |
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| 192 | .long SYM(_uhoh) | 153: |
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| 193 | .long SYM(_uhoh) | 154: |
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| 194 | .long SYM(_uhoh) | 155: |
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| 195 | .long SYM(_uhoh) | 156: |
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| 196 | .long SYM(_uhoh) | 157: |
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| 197 | .long SYM(_uhoh) | 158: |
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| 198 | .long SYM(_uhoh) | 159: |
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| 199 | .long SYM(_uhoh) | 160: |
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| 200 | .long SYM(_uhoh) | 161: |
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| 201 | .long SYM(_uhoh) | 162: |
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| 202 | .long SYM(_uhoh) | 163: |
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| 203 | .long SYM(_uhoh) | 164: |
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| 204 | .long SYM(_uhoh) | 165: |
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| 205 | .long SYM(_uhoh) | 166: |
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| 206 | .long SYM(_uhoh) | 167: |
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| 207 | .long SYM(_uhoh) | 168: |
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| 208 | .long SYM(_uhoh) | 169: |
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| 209 | .long SYM(_uhoh) | 170: |
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| 210 | .long SYM(_uhoh) | 171: |
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| 211 | .long SYM(_uhoh) | 172: |
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| 212 | .long SYM(_uhoh) | 173: |
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| 213 | .long SYM(_uhoh) | 174: |
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| 214 | .long SYM(_uhoh) | 175: |
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| 215 | .long SYM(_uhoh) | 176: |
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| 216 | .long SYM(_uhoh) | 177: |
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| 217 | .long SYM(_uhoh) | 178: |
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| 218 | .long SYM(_uhoh) | 179: |
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| 219 | .long SYM(_uhoh) | 180: |
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| 220 | .long SYM(_uhoh) | 181: |
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| 221 | .long SYM(_uhoh) | 182: |
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| 222 | .long SYM(_uhoh) | 183: |
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| 223 | .long SYM(_uhoh) | 184: |
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| 224 | .long SYM(_uhoh) | 185: |
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| 225 | .long SYM(_uhoh) | 186: |
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| 226 | .long SYM(_uhoh) | 187: |
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| 227 | .long SYM(_uhoh) | 188: |
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| 228 | .long SYM(_uhoh) | 189: |
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| 229 | .long SYM(_uhoh) | 190: |
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| 230 | .long SYM(_uhoh) | 191: |
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| 231 | .long SYM(_uhoh) | 192: |
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| 232 | .long SYM(_uhoh) | 193: |
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| 233 | .long SYM(_uhoh) | 194: |
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| 234 | .long SYM(_uhoh) | 195: |
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| 235 | .long SYM(_uhoh) | 196: |
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| 236 | .long SYM(_uhoh) | 197: |
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| 237 | .long SYM(_uhoh) | 198: |
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| 238 | .long SYM(_uhoh) | 199: |
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| 239 | .long SYM(_uhoh) | 200: |
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| 240 | .long SYM(_uhoh) | 201: |
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| 241 | .long SYM(_uhoh) | 202: |
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| 242 | .long SYM(_uhoh) | 203: |
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| 243 | .long SYM(_uhoh) | 204: |
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| 244 | .long SYM(_uhoh) | 205: |
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| 245 | .long SYM(_uhoh) | 206: |
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| 246 | .long SYM(_uhoh) | 207: |
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| 247 | .long SYM(_uhoh) | 208: |
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| 248 | .long SYM(_uhoh) | 209: |
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| 249 | .long SYM(_uhoh) | 210: |
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| 250 | .long SYM(_uhoh) | 211: |
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| 251 | .long SYM(_uhoh) | 212: |
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| 252 | .long SYM(_uhoh) | 213: |
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| 253 | .long SYM(_uhoh) | 214: |
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| 254 | .long SYM(_uhoh) | 215: |
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| 255 | .long SYM(_uhoh) | 216: |
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| 256 | .long SYM(_uhoh) | 217: |
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| 257 | .long SYM(_uhoh) | 218: |
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| 258 | .long SYM(_uhoh) | 219: |
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| 259 | .long SYM(_uhoh) | 220: |
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| 260 | .long SYM(_uhoh) | 221: |
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| 261 | .long SYM(_uhoh) | 222: |
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| 262 | .long SYM(_uhoh) | 223: |
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| 263 | .long SYM(_uhoh) | 224: |
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| 264 | .long SYM(_uhoh) | 225: |
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| 265 | .long SYM(_uhoh) | 226: |
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| 266 | .long SYM(_uhoh) | 227: |
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| 267 | .long SYM(_uhoh) | 228: |
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| 268 | .long SYM(_uhoh) | 229: |
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| 269 | .long SYM(_uhoh) | 230: |
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| 270 | .long SYM(_uhoh) | 231: |
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| 271 | .long SYM(_uhoh) | 232: |
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| 272 | .long SYM(_uhoh) | 233: |
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| 273 | .long SYM(_uhoh) | 234: |
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| 274 | .long SYM(_uhoh) | 235: |
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| 275 | .long SYM(_uhoh) | 236: |
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| 276 | .long SYM(_uhoh) | 237: |
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| 277 | .long SYM(_uhoh) | 238: |
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| 278 | .long SYM(_uhoh) | 239: |
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| 279 | .long SYM(_uhoh) | 240: |
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| 280 | .long SYM(_uhoh) | 241: |
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| 281 | .long SYM(_uhoh) | 242: |
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| 282 | .long SYM(_uhoh) | 243: |
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| 283 | .long SYM(_uhoh) | 244: |
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| 284 | .long SYM(_uhoh) | 245: |
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| 285 | .long SYM(_uhoh) | 246: |
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| 286 | .long SYM(_uhoh) | 247: |
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| 287 | .long SYM(_uhoh) | 248: |
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| 288 | .long SYM(_uhoh) | 249: |
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| 289 | .long SYM(_uhoh) | 250: |
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| 290 | .long SYM(_uhoh) | 251: |
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| 291 | .long SYM(_uhoh) | 252: |
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| 292 | .long SYM(_uhoh) | 253: |
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| 293 | .long SYM(_uhoh) | 254: |
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| 294 | .long SYM(_uhoh) | 255: |
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| 295 | |
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| 296 | /* |
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| 297 | * Default trap handler |
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| 298 | * With an oscilloscope you can see AS* stop |
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| 299 | */ |
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| 300 | PUBLIC (_uhoh) |
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| 301 | SYM(_uhoh): nop | Leave spot for breakpoint |
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| 302 | /* stop #0x2700 | Stop with interrupts disabled */ |
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| 303 | move.w #0x2700,sr |
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| 304 | move.w (a7),_boot_panic_registers+4 | SR |
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| 305 | move.l 2(a7),_boot_panic_registers | PC |
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| 306 | move.w 6(a7),_boot_panic_registers+6 | format & vector |
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| 307 | movem.l d0-d7/a0-a7, _boot_panic_registers+8 |
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| 308 | movec sfc, d0 |
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| 309 | movem.l d0, _boot_panic_registers+72 |
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| 310 | movec dfc, d0 |
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| 311 | movem.l d0, _boot_panic_registers+76 |
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| 312 | movec vbr, d0 |
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| 313 | movem.l d0, _boot_panic_registers+80 |
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| 314 | jmp SYM(_dbug_dumpanic) |
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| 315 | bra.s _crt0_cold_start |
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| 316 | |
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| 317 | /* |
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| 318 | * Log, but otherwise ignore, spurious interrupts |
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| 319 | */ |
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| 320 | PUBLIC (_spuriousInterrupt) |
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| 321 | SYM(_spuriousInterrupt): |
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| 322 | addql #1,SYM(_M68kSpuriousInterruptCount) |
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| 323 | rte |
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| 324 | |
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| 325 | /* |
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| 326 | * Place the low-order 3 octets of the board's ethernet address at |
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| 327 | * a `well-known' fixed location relative to the startup location. |
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| 328 | */ |
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| 329 | .align 2 |
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| 330 | .word 0 | Padding |
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| 331 | ethernet_address_buffer: |
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| 332 | .word 0x08F3 | Default address |
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| 333 | .word 0xDEAD |
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| 334 | .word 0xCAFE |
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| 335 | |
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| 336 | BEGIN_DATA |
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| 337 | |
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| 338 | /* equates */ |
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| 339 | |
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| 340 | .equ _CPU340, 0x0 |
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| 341 | .equ _CPU349, 0x31 |
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| 342 | |
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| 343 | #ifdef _OLD_ASTECC /* old addresses for AST68340 only */ |
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| 344 | .equ _EPLD_CS_BASE, 0x1 |
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| 345 | .equ _PROM_Start, 0x01000000 /* CS0 */ |
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| 346 | .equ _FLEX_Start, 0x08000000 /* CS2 */ |
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| 347 | .equ _I2C_Start, 0x0c000000 /* CS3 */ |
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| 348 | |
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| 349 | .equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ |
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| 350 | .equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ |
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| 351 | |
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| 352 | .equ _ExtRam_Start, 0x10000000 /* SRAM */ |
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| 353 | .equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ |
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| 354 | |
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| 355 | .equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ |
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| 356 | .equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ |
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| 357 | |
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| 358 | #else /* new addresses for AST68349 and 68340 */ |
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| 359 | |
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| 360 | .equ _EPLD_CS_BASE, 0x5 |
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| 361 | .equ _PROM_Start, 0x50000000 /* CS0 */ |
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| 362 | .equ _FLEX_Start, 0x08000000 /* CS2 */ |
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| 363 | .equ _I2C_Start, 0x0c000000 /* CS3 */ |
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| 364 | |
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| 365 | .equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ |
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| 366 | .equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ |
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| 367 | |
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| 368 | .equ _ExtRam_Start, 0x80000000 /* DRAM */ |
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| 369 | .equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ |
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| 370 | |
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| 371 | .equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ |
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| 372 | .equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ |
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| 373 | #endif |
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| 374 | |
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| 375 | .equ _SPEED349, 0xD680 /* 24 Mhz */ |
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| 376 | .equ _SPEED340, 0xD700 /* 25 Mhz */ |
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| 377 | /* .equ _SPEED340, 0xCE00 16 Mhz */ |
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| 378 | |
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| 379 | #define crt0_boot_type d0 /* cold/warm start (must be D0) */ |
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| 380 | #define crt0_temp d1 |
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| 381 | #define crt0_cpu_type d2 |
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| 382 | #define crt0_csswitch d3 |
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| 383 | #define crt0_buswidth d4 |
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| 384 | #define crt0_pdcs d5 |
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| 385 | #define crt0_spare6 d6 |
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| 386 | #define crt0_spare7 d7 |
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| 387 | #define crt0_sim_base a0 |
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| 388 | #define crt0_glue a1 |
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| 389 | #define crt0_dram a2 |
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| 390 | #define crt0_ptr3 a3 |
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| 391 | #define crt0_ptr4 a4 |
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| 392 | #define crt0_ptr5 a5 |
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| 393 | #define crt0_ptr6 a6 |
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| 394 | |
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| 395 | /* -- PDCS buffer equates -- */ |
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| 396 | .equ pdcs_mask, 0x1F /* DRAM configuration */ |
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| 397 | .equ pdcs_sw12, 7 /* switch 12 */ |
|---|
| 398 | .equ pdcs_sw11, 6 /* switch 11 */ |
|---|
| 399 | .equ pdcs_sw14, 5 /* switch 14 */ |
|---|
| 400 | |
|---|
| 401 | .equ bit_cache, pdcs_sw12 /* enable cache if on */ |
|---|
| 402 | .equ bit_meminit, pdcs_sw11 /* init memory if on */ |
|---|
| 403 | |
|---|
| 404 | /* -- Initialization stack and vars -- */ |
|---|
| 405 | |
|---|
| 406 | _AsteccBusWidth: ds.b 1 |
|---|
| 407 | _AsteccCsSwitch: ds.b 1 |
|---|
| 408 | _AsteccCpuName: ds.l 1 |
|---|
| 409 | |
|---|
| 410 | .align 4 |
|---|
| 411 | |
|---|
| 412 | _crt0_init_stack: |
|---|
| 413 | ds.l 500 |
|---|
| 414 | _crt0_init_stktop: |
|---|
| 415 | |
|---|
| 416 | /* -- Initialization code -- */ |
|---|
| 417 | BEGIN_CODE |
|---|
| 418 | |
|---|
| 419 | .align 4 |
|---|
| 420 | dc.l _crt0_init_stktop /* reset SP */ |
|---|
| 421 | dc.l _crt0_cold_start /* reset PC */ |
|---|
| 422 | dc.l _crt0_warm_start |
|---|
| 423 | |
|---|
| 424 | .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" |
|---|
| 425 | dc.w 0 |
|---|
| 426 | .align 4 |
|---|
| 427 | |
|---|
| 428 | .globl start |
|---|
| 429 | start: |
|---|
| 430 | |
|---|
| 431 | _crt0_cold_start: |
|---|
| 432 | moveq.l #0,crt0_boot_type | signal cold reset |
|---|
| 433 | bra.s _crt0_common_start |
|---|
| 434 | |
|---|
| 435 | _crt0_warm_start: |
|---|
| 436 | moveq.l #1,crt0_boot_type | signal warm reset |
|---|
| 437 | |
|---|
| 438 | _crt0_common_start: |
|---|
| 439 | move.w #0x2700,sr | disable interrupts and switch to interrupt mode |
|---|
| 440 | movea.l #_crt0_init_stktop,sp | set up initialization stack |
|---|
| 441 | |
|---|
| 442 | move.l #Entry,crt0_temp | VBR initialization |
|---|
| 443 | movec.l crt0_temp,vbr | |
|---|
| 444 | moveq.l #0x07,crt0_temp |
|---|
| 445 | movec.l crt0_temp,dfc | prepare access in CPU space |
|---|
| 446 | move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES |
|---|
| 447 | moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) |
|---|
| 448 | |
|---|
| 449 | movea.l #BASE_SIM,crt0_sim_base |
|---|
| 450 | |
|---|
| 451 | /* -- disable Bus Monitor -- */ |
|---|
| 452 | move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register |
|---|
| 453 | |
|---|
| 454 | /* -- enable A31-A24 -- */ |
|---|
| 455 | clr.b SIM_PPRA1(crt0_sim_base) |
|---|
| 456 | |
|---|
| 457 | /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ |
|---|
| 458 | move.w #0x427F,SIM_MCR(crt0_sim_base) |
|---|
| 459 | |
|---|
| 460 | /* -- enable /IRQ3, 5, 6, 7 -- */ |
|---|
| 461 | move.b #0xE8,SIM_PPRB(crt0_sim_base) |
|---|
| 462 | |
|---|
| 463 | /* -- enable autovector on /IRQ7 -- */ |
|---|
| 464 | move.b #0x80,SIM_AVR(crt0_sim_base) |
|---|
| 465 | |
|---|
| 466 | /* -- test CPU type -- */ |
|---|
| 467 | cmp.b #_CPU349,SIM_IDR(crt0_sim_base) |
|---|
| 468 | bne cpu_is_68340 |
|---|
| 469 | |
|---|
| 470 | /*-------------------------------------------------------------------------------------------*/ |
|---|
| 471 | cpu_is_68349: |
|---|
| 472 | |
|---|
| 473 | /* -- set cpu clock -- */ |
|---|
| 474 | move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock |
|---|
| 475 | |
|---|
| 476 | sync_wait349: |
|---|
| 477 | btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) |
|---|
| 478 | beq sync_wait349 |
|---|
| 479 | |
|---|
| 480 | /* to allow access to the EPLD internal registers, it is necessary |
|---|
| 481 | to disable the global chip-select /CS0 (which decodes every external |
|---|
| 482 | cycles). To do that, we initialize the 68349 internal RAM, |
|---|
| 483 | copy a part of the initialization code in it, and jump there. |
|---|
| 484 | from that moment, /CS0 is not used, therefore it can be initialized |
|---|
| 485 | with its default value. Its width may be incorrect, but it will be |
|---|
| 486 | adjusted later. The goal is to avoid any conflict with |
|---|
| 487 | the accesses to the EPLD registers. |
|---|
| 488 | When this is done, we read the RESET parameters (boot prom width |
|---|
| 489 | and chip-select switch) and proceed with the initialization |
|---|
| 490 | when all is done, we jump back to the boot prom now |
|---|
| 491 | decoded with a properly configured /CS0 */ |
|---|
| 492 | |
|---|
| 493 | /*-------------------------------------*/ |
|---|
| 494 | /* -- configure internal SRAM banks -- */ |
|---|
| 495 | |
|---|
| 496 | move.l #0x00000000,QDMM_MCR(crt0_sim_base) |
|---|
| 497 | move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) |
|---|
| 498 | move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) |
|---|
| 499 | move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) |
|---|
| 500 | move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) |
|---|
| 501 | |
|---|
| 502 | /*--------------------------------------------------------*/ |
|---|
| 503 | /* -- copy to address of the 68349 initialization code -- */ |
|---|
| 504 | |
|---|
| 505 | lea.l _copy_start(%pc),crt0_ptr3 |
|---|
| 506 | lea.l _copy_end(%pc),crt0_ptr4 |
|---|
| 507 | move.l crt0_ptr4,crt0_temp |
|---|
| 508 | sub.l crt0_ptr3,crt0_temp |
|---|
| 509 | add.l #3,crt0_temp | adjust to next long word |
|---|
| 510 | lsr.l #2,crt0_temp |
|---|
| 511 | |
|---|
| 512 | move.l #_FastRam_Start,crt0_ptr4 |
|---|
| 513 | _copy_loop: |
|---|
| 514 | move.l (crt0_ptr3)+,(crt0_ptr4)+ |
|---|
| 515 | subq.l #1,crt0_temp |
|---|
| 516 | bne.s _copy_loop |
|---|
| 517 | bra.l _FastRam_Start | jump to code in internal RAM |
|---|
| 518 | |
|---|
| 519 | /*------------------------------------*/ |
|---|
| 520 | /* -- start of initialization code -- */ |
|---|
| 521 | |
|---|
| 522 | _copy_start: |
|---|
| 523 | bra.l _begin_68349_init |
|---|
| 524 | |
|---|
| 525 | /*----------------------------------------------------------*/ |
|---|
| 526 | /* Astecc 68349 board : chip-select initialization values */ |
|---|
| 527 | |
|---|
| 528 | _table_csepld: |
|---|
| 529 | dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws |
|---|
| 530 | dc.b 0x80 | 16 bits, 0 ws |
|---|
| 531 | dc.b 0x90 | 16 bits, ext /dsack |
|---|
| 532 | dc.b 0x90 | 16 bits, ext /dsack |
|---|
| 533 | |
|---|
| 534 | _table_cs349: |
|---|
| 535 | dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) |
|---|
| 536 | dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 |
|---|
| 537 | dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) |
|---|
| 538 | dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 |
|---|
| 539 | dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) |
|---|
| 540 | dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 |
|---|
| 541 | dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) |
|---|
| 542 | dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 |
|---|
| 543 | |
|---|
| 544 | /*-------------------------------------------------*/ |
|---|
| 545 | _begin_68349_init: |
|---|
| 546 | |
|---|
| 547 | /*-------------------------------------------------*/ |
|---|
| 548 | /* 68349 chip select initialization |
|---|
| 549 | |
|---|
| 550 | at this stage, the width of /CS0 may be incorrect |
|---|
| 551 | it will be corrected later |
|---|
| 552 | */ |
|---|
| 553 | |
|---|
| 554 | _cs68349_init: |
|---|
| 555 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
|---|
| 556 | lea.l _table_cs349(%pc),crt0_ptr3 |
|---|
| 557 | |
|---|
| 558 | moveq.l #0x07,crt0_temp |
|---|
| 559 | _cs349_init2: |
|---|
| 560 | move.l (crt0_ptr3)+,(crt0_ptr4)+ |
|---|
| 561 | dbra crt0_temp,_cs349_init2 |
|---|
| 562 | |
|---|
| 563 | /*-----------------------------------------------*/ |
|---|
| 564 | /* -- prepare access to the internal registers --*/ |
|---|
| 565 | moveq.l #EPLD_SPACE,crt0_temp |
|---|
| 566 | movec.l crt0_temp,dfc |
|---|
| 567 | movec.l crt0_temp,sfc |
|---|
| 568 | move.l #GLUE_EPLD,crt0_glue |
|---|
| 569 | move.l #DRAM_EPLD,crt0_dram |
|---|
| 570 | |
|---|
| 571 | /*-------------------------------------------*/ |
|---|
| 572 | /* EPLD generated /CS[3..0] must be disabled */ |
|---|
| 573 | |
|---|
| 574 | _csepld_clear: |
|---|
| 575 | move.l crt0_glue,crt0_ptr4 |
|---|
| 576 | move.w #3,crt0_spare6 |
|---|
| 577 | clr.b crt0_temp |
|---|
| 578 | |
|---|
| 579 | _csepld_clear1: |
|---|
| 580 | moves.b crt0_temp,(crt0_ptr4)+ |
|---|
| 581 | dbra crt0_spare6,_csepld_clear1 |
|---|
| 582 | |
|---|
| 583 | /*---------------------------------------------------------*/ |
|---|
| 584 | /* -- get width of boot PROM, and active chip-select set --*/ |
|---|
| 585 | moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch |
|---|
| 586 | move.b crt0_csswitch,crt0_buswidth |
|---|
| 587 | |
|---|
| 588 | /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) |
|---|
| 589 | : sel == 1 => EPLD chip_selects (/CS[3..0]) */ |
|---|
| 590 | and.b #1,crt0_csswitch |
|---|
| 591 | |
|---|
| 592 | /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 |
|---|
| 593 | bus width : 32 16 8 ext./dsackx */ |
|---|
| 594 | rol.b #2,crt0_buswidth |
|---|
| 595 | and.b #3,crt0_buswidth |
|---|
| 596 | |
|---|
| 597 | /*----------------------------------------------------*/ |
|---|
| 598 | /* -- configure chip select 0 with boot prom width -- */ |
|---|
| 599 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
|---|
| 600 | lea.l _table_cs349(%pc),crt0_ptr3 |
|---|
| 601 | move.l (crt0_ptr3)+,crt0_temp |
|---|
| 602 | and.b #0xFC,crt0_temp | clear PS0 & PS1 |
|---|
| 603 | or.b crt0_buswidth,crt0_temp | set boot PROM bus width |
|---|
| 604 | move.l crt0_temp,(crt0_ptr4)+ |
|---|
| 605 | |
|---|
| 606 | /*------------------------*/ |
|---|
| 607 | /* -- read PDCS buffer -- */ |
|---|
| 608 | moves.b REG_PDCS(crt0_glue),crt0_pdcs |
|---|
| 609 | /* move.b #0x3F,crt0_pdcs pour test */ |
|---|
| 610 | |
|---|
| 611 | |
|---|
| 612 | /*---------------------------------------*/ |
|---|
| 613 | /* -- EPLD chip-select initialization -- */ |
|---|
| 614 | /*---------------------------------------*/ |
|---|
| 615 | btst.b #0,crt0_csswitch |
|---|
| 616 | beq _cs_init_end |
|---|
| 617 | |
|---|
| 618 | /*--------------------------------------------*/ |
|---|
| 619 | /* 68349 generated /CS[3..0] must be disabled */ |
|---|
| 620 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
|---|
| 621 | lea.l _table_cs349(%pc),crt0_ptr3 |
|---|
| 622 | moveq.l #0x03,crt0_temp |
|---|
| 623 | _cs349_clear: |
|---|
| 624 | move.l (crt0_ptr3)+,(crt0_ptr4)+ |
|---|
| 625 | move.l (crt0_ptr3)+,crt0_spare6 |
|---|
| 626 | and.b #0xFE,crt0_spare6 | disable chip-select |
|---|
| 627 | move.l crt0_spare6,(crt0_ptr4)+ |
|---|
| 628 | dbra crt0_temp,_cs349_clear |
|---|
| 629 | |
|---|
| 630 | /*---------------------------------------------*/ |
|---|
| 631 | /* EPLD generated /CS[3..0] must be configured */ |
|---|
| 632 | _csepld_init: |
|---|
| 633 | move.l crt0_glue,crt0_ptr4 |
|---|
| 634 | lea.l _table_csepld(%pc),crt0_ptr3 |
|---|
| 635 | |
|---|
| 636 | move.b (crt0_ptr3)+,crt0_temp |
|---|
| 637 | or.b #0x20,crt0_temp | default width is 32 bits |
|---|
| 638 | tst.b crt0_buswidth | is boot PROM bus width 32 bits ? |
|---|
| 639 | beq _csepld1 | if not |
|---|
| 640 | and.b #0xDF,crt0_temp | set width to 16 bits |
|---|
| 641 | _csepld1: |
|---|
| 642 | moves.b crt0_temp,(crt0_ptr4)+ |
|---|
| 643 | |
|---|
| 644 | moveq.l #0x02,crt0_spare6 |
|---|
| 645 | _csepld2: |
|---|
| 646 | move.b (crt0_ptr3)+,crt0_temp |
|---|
| 647 | moves.b crt0_temp,(crt0_ptr4)+ |
|---|
| 648 | dbra crt0_spare6,_csepld2 |
|---|
| 649 | |
|---|
| 650 | _cs_init_end: |
|---|
| 651 | |
|---|
| 652 | /*--------------------------------------*/ |
|---|
| 653 | /* -- DRAM controller initialization -- */ |
|---|
| 654 | _dram_init: |
|---|
| 655 | move.w #15,crt0_temp |
|---|
| 656 | move.l #_ExtRam_Start,crt0_ptr3 |
|---|
| 657 | |
|---|
| 658 | _dram_init1: |
|---|
| 659 | clr.l (crt0_ptr3)+ | must access DRAM |
|---|
| 660 | dbra crt0_temp,_dram_init1 | prior to init refresh |
|---|
| 661 | |
|---|
| 662 | _dram_init2: |
|---|
| 663 | move.b #3,crt0_temp |
|---|
| 664 | moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states |
|---|
| 665 | |
|---|
| 666 | move.b #0x81,crt0_temp |
|---|
| 667 | moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs |
|---|
| 668 | |
|---|
| 669 | move.b #0,crt0_temp |
|---|
| 670 | moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes |
|---|
| 671 | |
|---|
| 672 | /*-----------------------*/ |
|---|
| 673 | /* -- configure cache -- */ |
|---|
| 674 | _init_cache: |
|---|
| 675 | move.l #0x000001E0,CACHE_MCR(crt0_sim_base) |
|---|
| 676 | btst.b #bit_cache,crt0_pdcs |
|---|
| 677 | bne _init_cache_end |
|---|
| 678 | or.l #0x00000001,CACHE_MCR(crt0_sim_base) |
|---|
| 679 | |
|---|
| 680 | _init_cache_end: |
|---|
| 681 | |
|---|
| 682 | /*-----------------------------*/ |
|---|
| 683 | /* -- timers initialization -- */ |
|---|
| 684 | |
|---|
| 685 | clr.b crt0_temp |
|---|
| 686 | moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 |
|---|
| 687 | moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 |
|---|
| 688 | |
|---|
| 689 | /*--------------------------*/ |
|---|
| 690 | /* -- I2C initialization -- */ |
|---|
| 691 | move.b #3,crt0_temp |
|---|
| 692 | moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports |
|---|
| 693 | |
|---|
| 694 | /*-----------------------------------------*/ |
|---|
| 695 | /* -- baudrate generator initialization -- */ |
|---|
| 696 | move.b #2,crt0_temp |
|---|
| 697 | moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 |
|---|
| 698 | |
|---|
| 699 | /*-------------------------------*/ |
|---|
| 700 | /* -- IO port initialization -- */ |
|---|
| 701 | clr.b crt0_temp |
|---|
| 702 | moves.b crt0_temp,REG_IO(crt0_glue) | set port as input |
|---|
| 703 | |
|---|
| 704 | /* -- */ |
|---|
| 705 | |
|---|
| 706 | move.l #68349,crt0_cpu_type |
|---|
| 707 | |
|---|
| 708 | |
|---|
| 709 | /* -- jump back to PROM -- */ |
|---|
| 710 | |
|---|
| 711 | jmp.l (_fill_test) | must be absolute long |
|---|
| 712 | |
|---|
| 713 | _copy_end: |
|---|
| 714 | |
|---|
| 715 | /*------------------------------------------------- |
|---|
| 716 | initialization code for the 68340 board |
|---|
| 717 | -------------------------------------------------*/ |
|---|
| 718 | |
|---|
| 719 | /* Astecc 68340 board : chip-select initialization values */ |
|---|
| 720 | _table_cs340: |
|---|
| 721 | dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ |
|---|
| 722 | dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ |
|---|
| 723 | dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ |
|---|
| 724 | dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ |
|---|
| 725 | dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ |
|---|
| 726 | dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ |
|---|
| 727 | dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ |
|---|
| 728 | dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ |
|---|
| 729 | |
|---|
| 730 | cpu_is_68340: |
|---|
| 731 | |
|---|
| 732 | /* -- set cpu clock -- */ |
|---|
| 733 | move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock |
|---|
| 734 | sync_wait340: |
|---|
| 735 | btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) |
|---|
| 736 | beq sync_wait340 |
|---|
| 737 | |
|---|
| 738 | /* -- chip select initialization -- */ |
|---|
| 739 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
|---|
| 740 | lea.l _table_cs340(%pc),crt0_ptr3 |
|---|
| 741 | moveq.l #0x07,crt0_temp |
|---|
| 742 | _b_cs340: |
|---|
| 743 | move.l (crt0_ptr3)+,crt0_ptr5 |
|---|
| 744 | move.l crt0_ptr5,(crt0_ptr4)+ | pour test |
|---|
| 745 | dbra crt0_temp,_b_cs340 |
|---|
| 746 | |
|---|
| 747 | move.l #68340,crt0_cpu_type |
|---|
| 748 | move.b #0,crt0_csswitch | CPU |
|---|
| 749 | move.b #1,crt0_buswidth | 16 bits |
|---|
| 750 | |
|---|
| 751 | |
|---|
| 752 | /*------------------------------------------------- |
|---|
| 753 | fill RAM if COLDSTART |
|---|
| 754 | -------------------------------------------------*/ |
|---|
| 755 | _fill_test: |
|---|
| 756 | |
|---|
| 757 | tst.l crt0_boot_type |
|---|
| 758 | bne _dont_fill |
|---|
| 759 | |
|---|
| 760 | cmp.b #_CPU349,SIM_IDR(crt0_sim_base) |
|---|
| 761 | bne _fill |
|---|
| 762 | btst.b #bit_meminit,crt0_pdcs |
|---|
| 763 | bne _dont_fill |
|---|
| 764 | |
|---|
| 765 | /* fill main memory */ |
|---|
| 766 | _fill: |
|---|
| 767 | move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars |
|---|
| 768 | move.l #_ExtRam_Start,crt0_temp |
|---|
| 769 | sub.l #_crt0_init_stack,crt0_temp |
|---|
| 770 | add.l #_ExtRam_Size,crt0_temp | get size |
|---|
| 771 | lsr.l #2,crt0_temp | ajust for long word |
|---|
| 772 | _fill_loop: |
|---|
| 773 | clr.l (crt0_ptr3)+ |
|---|
| 774 | subq.l #1,crt0_temp |
|---|
| 775 | bne _fill_loop |
|---|
| 776 | |
|---|
| 777 | cmp.b #_CPU349,SIM_IDR(crt0_sim_base) |
|---|
| 778 | bne _fill_bccram |
|---|
| 779 | |
|---|
| 780 | /* fill QDMM memory */ |
|---|
| 781 | movea.l #_FastRam_Start,crt0_ptr3 | get start |
|---|
| 782 | move.l #_FastRam_Size,crt0_temp | get size |
|---|
| 783 | lsr.l #2,crt0_temp | ajust for long word |
|---|
| 784 | |
|---|
| 785 | _QDMMfill_loop: |
|---|
| 786 | clr.l (crt0_ptr3)+ |
|---|
| 787 | subq.l #1,crt0_temp |
|---|
| 788 | bne _QDMMfill_loop |
|---|
| 789 | bra _dont_fill |
|---|
| 790 | |
|---|
| 791 | /* fill BCC memory */ |
|---|
| 792 | _fill_bccram: |
|---|
| 793 | movea.l #_BCCram_Start,crt0_ptr3 | get start |
|---|
| 794 | move.l #_BCCram_Size,crt0_temp | get size |
|---|
| 795 | lsr.l #2,crt0_temp | ajust for long word |
|---|
| 796 | _BCCfill_loop: |
|---|
| 797 | clr.l (crt0_ptr3)+ |
|---|
| 798 | subq.l #1,crt0_temp |
|---|
| 799 | bne _BCCfill_loop |
|---|
| 800 | |
|---|
| 801 | *-------------------------------------------------*/ |
|---|
| 802 | _dont_fill: |
|---|
| 803 | move.b crt0_csswitch,_AsteccCsSwitch |
|---|
| 804 | move.b crt0_buswidth,_AsteccBusWidth |
|---|
| 805 | move.l crt0_cpu_type,_AsteccCpuName |
|---|
| 806 | |
|---|
| 807 | jmp SYM(_Init68340) | Start C code (which never returns) |
|---|
| 808 | |
|---|
| 809 | /* |
|---|
| 810 | * Copy DATA segment, clear BSS segment, set up real stack, |
|---|
| 811 | * initialize heap, start C program. |
|---|
| 812 | * Assume that DATA and BSS sizes are multiples of 4. |
|---|
| 813 | */ |
|---|
| 814 | PUBLIC (_CopyDataClearBSSAndStart) |
|---|
| 815 | SYM(_CopyDataClearBSSAndStart): |
|---|
| 816 | lea copy_start,a0 | Get start of DATA in RAM |
|---|
| 817 | lea SYM(etext),a2 | Get start of DATA in ROM |
|---|
| 818 | cmpl a0,a2 | Are they the same? |
|---|
| 819 | beq.s NOCOPY | Yes, no copy necessary |
|---|
| 820 | lea copy_end,a1 | Get end of DATA in RAM |
|---|
| 821 | bra.s COPYLOOPTEST | Branch into copy loop |
|---|
| 822 | COPYLOOP: |
|---|
| 823 | movel a2@+,a0@+ | Copy word from ROM to RAM |
|---|
| 824 | COPYLOOPTEST: |
|---|
| 825 | cmpl a1,a0 | Done? |
|---|
| 826 | bcs.s COPYLOOP | No, skip |
|---|
| 827 | NOCOPY: |
|---|
| 828 | |
|---|
| 829 | lea clear_start,a0 | Get start of BSS |
|---|
| 830 | lea clear_end,a1 | Get end of BSS |
|---|
| 831 | clrl d0 | Value to set |
|---|
| 832 | bra.s ZEROLOOPTEST | Branch into clear loop |
|---|
| 833 | ZEROLOOP: |
|---|
| 834 | movel d0,a0@+ | Clear a word |
|---|
| 835 | ZEROLOOPTEST: |
|---|
| 836 | cmpl a1,a0 | Done? |
|---|
| 837 | bcs.s ZEROLOOP | No, skip |
|---|
| 838 | |
|---|
| 839 | movel #stack_init,a7 | set master stack pointer |
|---|
| 840 | movel d0,a7@- | environp |
|---|
| 841 | movel d0,a7@- | argv |
|---|
| 842 | movel d0,a7@- | argc |
|---|
| 843 | jsr SYM(boot_card) | Call C main |
|---|
| 844 | |
|---|
| 845 | PUBLIC (_mainDone) |
|---|
| 846 | SYM(_mainDone): |
|---|
| 847 | nop | Leave spot for breakpoint |
|---|
| 848 | movew #1,a7 | Force a double bus error |
|---|
| 849 | movel d0,a7@- | This should cause a RESET |
|---|
| 850 | /* stop #0x2700 | Stop with interrupts disabled */ |
|---|
| 851 | move.w #0x2700,sr |
|---|
| 852 | bra.s SYM(_mainDone) | Stuck forever |
|---|
| 853 | |
|---|
| 854 | .align 2 |
|---|
| 855 | PUBLIC (_HeapSize) |
|---|
| 856 | SYM (_HeapSize): |
|---|
| 857 | .long HeapSize |
|---|
| 858 | PUBLIC (_StackSize) |
|---|
| 859 | SYM (_StackSize): |
|---|
| 860 | .long StackSize |
|---|
| 861 | END_CODE |
|---|
| 862 | |
|---|
| 863 | BEGIN_DATA_DCL |
|---|
| 864 | .align 2 |
|---|
| 865 | PUBLIC (environ) |
|---|
| 866 | SYM (environ): |
|---|
| 867 | .long 0 |
|---|
| 868 | PUBLIC (_M68kSpuriousInterruptCount) |
|---|
| 869 | SYM (_M68kSpuriousInterruptCount): |
|---|
| 870 | .long 0 |
|---|
| 871 | END_DATA_DCL |
|---|
| 872 | |
|---|
| 873 | END |
|---|
| 874 | |
|---|
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