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start.S @ d3fdf89f

4.104.114.84.95

Last change on this file since d3fdf89f was d3fdf89f, checked in by Joel Sherrill <joel.sherrill@…>, on 04/19/04 at 22:08:13

2004-04-19 Joel Sherrill <joel@…>

start/start.S: DWARF on the m68k requires that all objects me a multiple of a 16-bit word in length.

Property mode set to 100644

File size: 24.8 KB

Line
1	/*
2	* This file contains the entry point for the application.
3	* The name of this entry point is compiler dependent.
4	* It jumps to the BSP which is responsible for performing
5	* all initialization.
6	*
7	* COPYRIGHT (c) 1989-1999.
8	* On-Line Applications Research Corporation (OAR).
9	*
10	* The license and distribution terms for this file may in
11	* the file LICENSE in this distribution or at
12	* http://www.rtems.com/license/LICENSE.
13	*
14	* Based on the `gen68360' board support package, and covered by the
15	* original distribution terms.
16	*
17	* Geoffroy Montel
18	* France Telecom - CNET/DSM/TAM/CAT
19	* 4, rue du Clos Courtel
20	* 35512 CESSON-SEVIGNE
21	* FRANCE
22	*
23	* e-mail: g_montel@yahoo.com
24	*
25	* $Id$
26	*/
27
28	#include <rtems/asm.h>
29	#include <m68349.inc>
30
31	#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */
32
33	BEGIN_CODE
34	/*
35	* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
36	*/
37	Entry:
38	.long SYM(m340)+1024 \| 0: Initial SSP
39	.long start \| 1: Initial PC
40	.long SYM(_uhoh) \| 2: Bus error
41	.long SYM(_uhoh) \| 3: Address error
42	.long SYM(_uhoh) \| 4: Illegal instruction
43	.long SYM(_uhoh) \| 5: Zero division
44	.long SYM(_uhoh) \| 6: CHK, CHK2 instruction
45	.long SYM(_uhoh) \| 7: TRAPcc, TRAPV instructions
46	.long SYM(_uhoh) \| 8: Privilege violation
47	.long SYM(_uhoh) \| 9: Trace
48	.long SYM(_uhoh) \| 10: Line 1010 emulator
49	.long SYM(_uhoh) \| 11: Line 1111 emulator
50	.long SYM(_uhoh) \| 12: Hardware breakpoint
51	.long SYM(_uhoh) \| 13: Reserved for coprocessor violation
52	.long SYM(_uhoh) \| 14: Format error
53	.long SYM(_uhoh) \| 15: Uninitialized interrupt
54	.long SYM(_uhoh) \| 16: Unassigned, reserved
55	.long SYM(_uhoh) \| 17:
56	.long SYM(_uhoh) \| 18:
57	.long SYM(_uhoh) \| 19:
58	.long SYM(_uhoh) \| 20:
59	.long SYM(_uhoh) \| 21:
60	.long SYM(_uhoh) \| 22:
61	.long SYM(_uhoh) \| 23:
62	.long SYM(_spuriousInterrupt) \| 24: Spurious interrupt
63	.long SYM(_uhoh) \| 25: Level 1 interrupt autovector
64	.long SYM(_uhoh) \| 26: Level 2 interrupt autovector
65	.long SYM(_uhoh) \| 27: Level 3 interrupt autovector
66	.long SYM(_uhoh) \| 28: Level 4 interrupt autovector
67	.long SYM(_uhoh) \| 29: Level 5 interrupt autovector
68	.long SYM(_uhoh) \| 30: Level 6 interrupt autovector
69	.long SYM(_uhoh) \| 31: Level 7 interrupt autovector
70	.long SYM(_uhoh) \| 32: Trap instruction (0-15)
71	.long SYM(_uhoh) \| 33:
72	.long SYM(_uhoh) \| 34:
73	.long SYM(_uhoh) \| 35:
74	.long SYM(_uhoh) \| 36:
75	.long SYM(_uhoh) \| 37:
76	.long SYM(_uhoh) \| 38:
77	.long SYM(_uhoh) \| 39:
78	.long SYM(_uhoh) \| 40:
79	.long SYM(_uhoh) \| 41:
80	.long SYM(_uhoh) \| 42:
81	.long SYM(_uhoh) \| 43:
82	.long SYM(_uhoh) \| 44:
83	.long SYM(_uhoh) \| 45:
84	.long SYM(_uhoh) \| 46:
85	.long SYM(_uhoh) \| 47:
86	.long SYM(_uhoh) \| 48: Reserved for coprocessor
87	.long SYM(_uhoh) \| 49:
88	.long SYM(_uhoh) \| 50:
89	.long SYM(_uhoh) \| 51:
90	.long SYM(_uhoh) \| 52:
91	.long SYM(_uhoh) \| 53:
92	.long SYM(_uhoh) \| 54:
93	.long SYM(_uhoh) \| 55:
94	.long SYM(_uhoh) \| 56:
95	.long SYM(_uhoh) \| 57:
96	.long SYM(_uhoh) \| 58:
97	.long SYM(_uhoh) \| 59: Unassigned, reserved
98	.long SYM(_uhoh) \| 60:
99	.long SYM(_uhoh) \| 61:
100	.long SYM(_uhoh) \| 62:
101	.long SYM(_uhoh) \| 63:
102	.long SYM(_uhoh) \| 64: User defined vectors (192)
103	.long SYM(_uhoh) \| 65:
104	.long SYM(_uhoh) \| 66:
105	.long SYM(_uhoh) \| 67:
106	.long SYM(_uhoh) \| 68:
107	.long SYM(_uhoh) \| 69:
108	.long SYM(_uhoh) \| 70:
109	.long SYM(_uhoh) \| 71:
110	.long SYM(_uhoh) \| 72:
111	.long SYM(_uhoh) \| 73:
112	.long SYM(_uhoh) \| 74:
113	.long SYM(_uhoh) \| 75:
114	.long SYM(_uhoh) \| 76:
115	.long SYM(_uhoh) \| 77:
116	.long SYM(_uhoh) \| 78:
117	.long SYM(_uhoh) \| 79:
118	.long SYM(_uhoh) \| 80:
119	.long SYM(_uhoh) \| 81:
120	.long SYM(_uhoh) \| 82:
121	.long SYM(_uhoh) \| 83:
122	.long SYM(_uhoh) \| 84:
123	.long SYM(_uhoh) \| 85:
124	.long SYM(_uhoh) \| 86:
125	.long SYM(_uhoh) \| 87:
126	.long SYM(_uhoh) \| 88:
127	.long SYM(_uhoh) \| 89:
128	.long SYM(_uhoh) \| 90:
129	.long SYM(_uhoh) \| 91:
130	.long SYM(_uhoh) \| 92:
131	.long SYM(_uhoh) \| 93:
132	.long SYM(_uhoh) \| 94:
133	.long SYM(_uhoh) \| 95:
134	.long SYM(_uhoh) \| 96:
135	.long SYM(_uhoh) \| 97:
136	.long SYM(_uhoh) \| 98:
137	.long SYM(_uhoh) \| 99:
138	.long SYM(_uhoh) \| 100:
139	.long SYM(_uhoh) \| 101:
140	.long SYM(_uhoh) \| 102:
141	.long SYM(_uhoh) \| 103:
142	.long SYM(_uhoh) \| 104:
143	.long SYM(_uhoh) \| 105:
144	.long SYM(_uhoh) \| 106:
145	.long SYM(_uhoh) \| 107:
146	.long SYM(_uhoh) \| 108:
147	.long SYM(_uhoh) \| 109:
148	.long SYM(_uhoh) \| 110:
149	.long SYM(_uhoh) \| 111:
150	.long SYM(_uhoh) \| 112:
151	.long SYM(_uhoh) \| 113:
152	.long SYM(_uhoh) \| 114:
153	.long SYM(_uhoh) \| 115:
154	.long SYM(_uhoh) \| 116:
155	.long SYM(_uhoh) \| 117:
156	.long SYM(_uhoh) \| 118:
157	.long SYM(_uhoh) \| 119:
158	.long SYM(_uhoh) \| 120:
159	.long SYM(_uhoh) \| 121:
160	.long SYM(_uhoh) \| 122:
161	.long SYM(_uhoh) \| 123:
162	.long SYM(_uhoh) \| 124:
163	.long SYM(_uhoh) \| 125:
164	.long SYM(_uhoh) \| 126:
165	.long SYM(_uhoh) \| 127:
166	.long SYM(_uhoh) \| 128:
167	.long SYM(_uhoh) \| 129:
168	.long SYM(_uhoh) \| 130:
169	.long SYM(_uhoh) \| 131:
170	.long SYM(_uhoh) \| 132:
171	.long SYM(_uhoh) \| 133:
172	.long SYM(_uhoh) \| 134:
173	.long SYM(_uhoh) \| 135:
174	.long SYM(_uhoh) \| 136:
175	.long SYM(_uhoh) \| 137:
176	.long SYM(_uhoh) \| 138:
177	.long SYM(_uhoh) \| 139:
178	.long SYM(_uhoh) \| 140:
179	.long SYM(_uhoh) \| 141:
180	.long SYM(_uhoh) \| 142:
181	.long SYM(_uhoh) \| 143:
182	.long SYM(_uhoh) \| 144:
183	.long SYM(_uhoh) \| 145:
184	.long SYM(_uhoh) \| 146:
185	.long SYM(_uhoh) \| 147:
186	.long SYM(_uhoh) \| 148:
187	.long SYM(_uhoh) \| 149:
188	.long SYM(_uhoh) \| 150:
189	.long SYM(_uhoh) \| 151:
190	.long SYM(_uhoh) \| 152:
191	.long SYM(_uhoh) \| 153:
192	.long SYM(_uhoh) \| 154:
193	.long SYM(_uhoh) \| 155:
194	.long SYM(_uhoh) \| 156:
195	.long SYM(_uhoh) \| 157:
196	.long SYM(_uhoh) \| 158:
197	.long SYM(_uhoh) \| 159:
198	.long SYM(_uhoh) \| 160:
199	.long SYM(_uhoh) \| 161:
200	.long SYM(_uhoh) \| 162:
201	.long SYM(_uhoh) \| 163:
202	.long SYM(_uhoh) \| 164:
203	.long SYM(_uhoh) \| 165:
204	.long SYM(_uhoh) \| 166:
205	.long SYM(_uhoh) \| 167:
206	.long SYM(_uhoh) \| 168:
207	.long SYM(_uhoh) \| 169:
208	.long SYM(_uhoh) \| 170:
209	.long SYM(_uhoh) \| 171:
210	.long SYM(_uhoh) \| 172:
211	.long SYM(_uhoh) \| 173:
212	.long SYM(_uhoh) \| 174:
213	.long SYM(_uhoh) \| 175:
214	.long SYM(_uhoh) \| 176:
215	.long SYM(_uhoh) \| 177:
216	.long SYM(_uhoh) \| 178:
217	.long SYM(_uhoh) \| 179:
218	.long SYM(_uhoh) \| 180:
219	.long SYM(_uhoh) \| 181:
220	.long SYM(_uhoh) \| 182:
221	.long SYM(_uhoh) \| 183:
222	.long SYM(_uhoh) \| 184:
223	.long SYM(_uhoh) \| 185:
224	.long SYM(_uhoh) \| 186:
225	.long SYM(_uhoh) \| 187:
226	.long SYM(_uhoh) \| 188:
227	.long SYM(_uhoh) \| 189:
228	.long SYM(_uhoh) \| 190:
229	.long SYM(_uhoh) \| 191:
230	.long SYM(_uhoh) \| 192:
231	.long SYM(_uhoh) \| 193:
232	.long SYM(_uhoh) \| 194:
233	.long SYM(_uhoh) \| 195:
234	.long SYM(_uhoh) \| 196:
235	.long SYM(_uhoh) \| 197:
236	.long SYM(_uhoh) \| 198:
237	.long SYM(_uhoh) \| 199:
238	.long SYM(_uhoh) \| 200:
239	.long SYM(_uhoh) \| 201:
240	.long SYM(_uhoh) \| 202:
241	.long SYM(_uhoh) \| 203:
242	.long SYM(_uhoh) \| 204:
243	.long SYM(_uhoh) \| 205:
244	.long SYM(_uhoh) \| 206:
245	.long SYM(_uhoh) \| 207:
246	.long SYM(_uhoh) \| 208:
247	.long SYM(_uhoh) \| 209:
248	.long SYM(_uhoh) \| 210:
249	.long SYM(_uhoh) \| 211:
250	.long SYM(_uhoh) \| 212:
251	.long SYM(_uhoh) \| 213:
252	.long SYM(_uhoh) \| 214:
253	.long SYM(_uhoh) \| 215:
254	.long SYM(_uhoh) \| 216:
255	.long SYM(_uhoh) \| 217:
256	.long SYM(_uhoh) \| 218:
257	.long SYM(_uhoh) \| 219:
258	.long SYM(_uhoh) \| 220:
259	.long SYM(_uhoh) \| 221:
260	.long SYM(_uhoh) \| 222:
261	.long SYM(_uhoh) \| 223:
262	.long SYM(_uhoh) \| 224:
263	.long SYM(_uhoh) \| 225:
264	.long SYM(_uhoh) \| 226:
265	.long SYM(_uhoh) \| 227:
266	.long SYM(_uhoh) \| 228:
267	.long SYM(_uhoh) \| 229:
268	.long SYM(_uhoh) \| 230:
269	.long SYM(_uhoh) \| 231:
270	.long SYM(_uhoh) \| 232:
271	.long SYM(_uhoh) \| 233:
272	.long SYM(_uhoh) \| 234:
273	.long SYM(_uhoh) \| 235:
274	.long SYM(_uhoh) \| 236:
275	.long SYM(_uhoh) \| 237:
276	.long SYM(_uhoh) \| 238:
277	.long SYM(_uhoh) \| 239:
278	.long SYM(_uhoh) \| 240:
279	.long SYM(_uhoh) \| 241:
280	.long SYM(_uhoh) \| 242:
281	.long SYM(_uhoh) \| 243:
282	.long SYM(_uhoh) \| 244:
283	.long SYM(_uhoh) \| 245:
284	.long SYM(_uhoh) \| 246:
285	.long SYM(_uhoh) \| 247:
286	.long SYM(_uhoh) \| 248:
287	.long SYM(_uhoh) \| 249:
288	.long SYM(_uhoh) \| 250:
289	.long SYM(_uhoh) \| 251:
290	.long SYM(_uhoh) \| 252:
291	.long SYM(_uhoh) \| 253:
292	.long SYM(_uhoh) \| 254:
293	.long SYM(_uhoh) \| 255:
294
295	/*
296	* Default trap handler
297	* With an oscilloscope you can see AS* stop
298	*/
299	PUBLIC (_uhoh)
300	SYM(_uhoh): nop \| Leave spot for breakpoint
301	/* stop #0x2700 \| Stop with interrupts disabled */
302	move.w #0x2700,sr
303	move.w (a7),_boot_panic_registers+4 \| SR
304	move.l 2(a7),_boot_panic_registers \| PC
305	move.w 6(a7),_boot_panic_registers+6 \| format & vector
306	movem.l d0-d7/a0-a7, _boot_panic_registers+8
307	movec sfc, d0
308	movem.l d0, _boot_panic_registers+72
309	movec dfc, d0
310	movem.l d0, _boot_panic_registers+76
311	movec vbr, d0
312	movem.l d0, _boot_panic_registers+80
313	jmp SYM(_dbug_dumpanic)
314	bra.s _crt0_cold_start
315
316	/*
317	* Log, but otherwise ignore, spurious interrupts
318	*/
319	PUBLIC (_spuriousInterrupt)
320	SYM(_spuriousInterrupt):
321	addql #1,SYM(_M68kSpuriousInterruptCount)
322	rte
323
324	/*
325	* Place the low-order 3 octets of the board's ethernet address at
326	* a `well-known' fixed location relative to the startup location.
327	*/
328	.align 2
329	.word 0 \| Padding
330	ethernet_address_buffer:
331	.word 0x08F3 \| Default address
332	.word 0xDEAD
333	.word 0xCAFE
334
335	BEGIN_DATA
336
337	/* equates */
338
339	.equ _CPU340, 0x0
340	.equ _CPU349, 0x31
341
342	#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
343	.equ _EPLD_CS_BASE, 0x1
344	.equ _PROM_Start, 0x01000000 /* CS0 */
345	.equ _FLEX_Start, 0x08000000 /* CS2 */
346	.equ _I2C_Start, 0x0c000000 /* CS3 */
347
348	.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
349	.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
350
351	.equ _ExtRam_Start, 0x10000000 /* SRAM */
352	.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
353
354	.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
355	.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
356
357	#else /* new addresses for AST68349 and 68340 */
358
359	.equ _EPLD_CS_BASE, 0x5
360	.equ _PROM_Start, 0x50000000 /* CS0 */
361	.equ _FLEX_Start, 0x08000000 /* CS2 */
362	.equ _I2C_Start, 0x0c000000 /* CS3 */
363
364	.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
365	.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
366
367	.equ _ExtRam_Start, 0x80000000 /* DRAM */
368	.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
369
370	.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
371	.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
372	#endif
373
374	.equ _SPEED349, 0xD680 /* 24 Mhz */
375	.equ _SPEED340, 0xD700 /* 25 Mhz */
376	/* .equ _SPEED340, 0xCE00 16 Mhz */
377
378	#define crt0_boot_type d0 /* cold/warm start (must be D0) */
379	#define crt0_temp d1
380	#define crt0_cpu_type d2
381	#define crt0_csswitch d3
382	#define crt0_buswidth d4
383	#define crt0_pdcs d5
384	#define crt0_spare6 d6
385	#define crt0_spare7 d7
386	#define crt0_sim_base a0
387	#define crt0_glue a1
388	#define crt0_dram a2
389	#define crt0_ptr3 a3
390	#define crt0_ptr4 a4
391	#define crt0_ptr5 a5
392	#define crt0_ptr6 a6
393
394	/* -- PDCS buffer equates -- */
395	.equ pdcs_mask, 0x1F /* DRAM configuration */
396	.equ pdcs_sw12, 7 /* switch 12 */
397	.equ pdcs_sw11, 6 /* switch 11 */
398	.equ pdcs_sw14, 5 /* switch 14 */
399
400	.equ bit_cache, pdcs_sw12 /* enable cache if on */
401	.equ bit_meminit, pdcs_sw11 /* init memory if on */
402
403	/* -- Initialization stack and vars -- */
404
405	/* When using DWARF, everything must be a multiple of 16-bits. */
406	#if 1
407	_AsteccBusWidth: ds.w 0x0101
408	_AsteccCsSwitch: ds.w 0x0101
409	#else
410	_AsteccBusWidth: ds.b 1
411	_AsteccCsSwitch: ds.b 1
412	#endif
413	_AsteccCpuName: ds.l 1
414
415	.align 4
416
417	_crt0_init_stack:
418	ds.l 500
419	_crt0_init_stktop:
420
421	/* -- Initialization code -- */
422	BEGIN_CODE
423
424	.align 4
425	dc.l _crt0_init_stktop /* reset SP */
426	dc.l _crt0_cold_start /* reset PC */
427	dc.l _crt0_warm_start
428
429	/* When using DWARF, everything must be a multiple of 16-bits. */
430	.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards "
431	.text
432	dc.w 0
433	.align 4
434
435	.globl start
436	start:
437
438	_crt0_cold_start:
439	moveq.l #0,crt0_boot_type \| signal cold reset
440	bra.s _crt0_common_start
441
442	_crt0_warm_start:
443	moveq.l #1,crt0_boot_type \| signal warm reset
444
445	_crt0_common_start:
446	move.w #0x2700,sr \| disable interrupts and switch to interrupt mode
447	movea.l #_crt0_init_stktop,sp \| set up initialization stack
448
449	move.l #Entry,crt0_temp \| VBR initialization
450	movec.l crt0_temp,vbr \|
451	moveq.l #0x07,crt0_temp
452	movec.l crt0_temp,dfc \| prepare access in CPU space
453	move.l #(BASE_SIM+0x111),crt0_temp \| mask CPU, RESERVED USER SPACES
454	moves.l crt0_temp,BASE_REG \| base initialization (must be MOVES, PCC-130795)
455
456	movea.l #BASE_SIM,crt0_sim_base
457
458	/* -- disable Bus Monitor -- */
459	move.b #0,SIM_SYPCR(crt0_sim_base) \| system protection control register
460
461	/* -- enable A31-A24 -- */
462	clr.b SIM_PPRA1(crt0_sim_base)
463
464	/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
465	move.w #0x427F,SIM_MCR(crt0_sim_base)
466
467	/* -- enable /IRQ3, 5, 6, 7 -- */
468	move.b #0xE8,SIM_PPRB(crt0_sim_base)
469
470	/* -- enable autovector on /IRQ7 -- */
471	move.b #0x80,SIM_AVR(crt0_sim_base)
472
473	/* -- test CPU type -- */
474	cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
475	bne cpu_is_68340
476
477	/-------------------------------------------------------------------------------------------/
478	cpu_is_68349:
479
480	/* -- set cpu clock -- */
481	move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) \| clock
482
483	sync_wait349:
484	btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
485	beq sync_wait349
486
487	/* to allow access to the EPLD internal registers, it is necessary
488	to disable the global chip-select /CS0 (which decodes every external
489	cycles). To do that, we initialize the 68349 internal RAM,
490	copy a part of the initialization code in it, and jump there.
491	from that moment, /CS0 is not used, therefore it can be initialized
492	with its default value. Its width may be incorrect, but it will be
493	adjusted later. The goal is to avoid any conflict with
494	the accesses to the EPLD registers.
495	When this is done, we read the RESET parameters (boot prom width
496	and chip-select switch) and proceed with the initialization
497	when all is done, we jump back to the boot prom now
498	decoded with a properly configured /CS0 */
499
500	/-------------------------------------/
501	/* -- configure internal SRAM banks -- */
502
503	move.l #0x00000000,QDMM_MCR(crt0_sim_base)
504	move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
505	move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
506	move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
507	move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
508
509	/--------------------------------------------------------/
510	/* -- copy to address of the 68349 initialization code -- */
511
512	lea.l _copy_start_code(%pc),crt0_ptr3
513	lea.l _copy_end_code(%pc),crt0_ptr4
514	move.l crt0_ptr4,crt0_temp
515	sub.l crt0_ptr3,crt0_temp
516	add.l #3,crt0_temp \| adjust to next long word
517	lsr.l #2,crt0_temp
518
519	move.l #_FastRam_Start,crt0_ptr4
520	_copy_loop:
521	move.l (crt0_ptr3)+,(crt0_ptr4)+
522	subq.l #1,crt0_temp
523	bne.s _copy_loop
524	bra.l _FastRam_Start \| jump to code in internal RAM
525
526	/------------------------------------/
527	/* -- start of initialization code -- */
528
529	_copy_start_code:
530	bra.l _begin_68349_init
531
532	/----------------------------------------------------------/
533	/* Astecc 68349 board : chip-select initialization values */
534
535	_table_csepld:
536	/* When using DWARF, everything must be a multiple of 16-bits. */
537	#if 1
538	dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) \| 0x80 \| 16 bits, 0ws
539	dc.w 0x9090 \| 16 bits, ext /dsack
540
541	#else
542	dc.b (_EPLD_CS_BASE&0x0F)+0x80 \| 16 bits, 0ws
543	dc.b 0x80 \| 16 bits, 0 ws
544	dc.b 0x90 \| 16 bits, ext /dsack
545	dc.b 0x90 \| 16 bits, ext /dsack
546	#endif
547
548	_table_cs349:
549	dc.l 0x003FFFF4 \| Mask CS0 (4Mbytes PROM, 32bits, 1WS)
550	dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 \| Base CS0
551	dc.l 0x003FFFF1 \| MASK CS1 (4Mbytes RAM, 16bits, 0WS)
552	dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 \| Base CS1
553	dc.l 0x000000FF \| MASK CS2 (FLEX, ext DTACK, 256 bytes)
554	dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 \| Base CS2
555	dc.l 0x000000FF \| Mask CS3 (I2C, ext DTACK, 256 bytes)
556	dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 \| Base CS3
557
558	/-------------------------------------------------/
559	_begin_68349_init:
560
561	/-------------------------------------------------/
562	/* 68349 chip select initialization
563
564	at this stage, the width of /CS0 may be incorrect
565	it will be corrected later
566	*/
567
568	_cs68349_init:
569	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
570	lea.l _table_cs349(%pc),crt0_ptr3
571
572	moveq.l #0x07,crt0_temp
573	_cs349_init2:
574	move.l (crt0_ptr3)+,(crt0_ptr4)+
575	dbra crt0_temp,_cs349_init2
576
577	/-----------------------------------------------/
578	/* -- prepare access to the internal registers --*/
579	moveq.l #EPLD_SPACE,crt0_temp
580	movec.l crt0_temp,dfc
581	movec.l crt0_temp,sfc
582	move.l #GLUE_EPLD,crt0_glue
583	move.l #DRAM_EPLD,crt0_dram
584
585	/-------------------------------------------/
586	/* EPLD generated /CS[3..0] must be disabled */
587
588	_csepld_clear:
589	move.l crt0_glue,crt0_ptr4
590	move.w #3,crt0_spare6
591	clr.b crt0_temp
592
593	_csepld_clear1:
594	moves.b crt0_temp,(crt0_ptr4)+
595	dbra crt0_spare6,_csepld_clear1
596
597	/---------------------------------------------------------/
598	/* -- get width of boot PROM, and active chip-select set --*/
599	moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
600	move.b crt0_csswitch,crt0_buswidth
601
602	/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
603	: sel == 1 => EPLD chip_selects (/CS[3..0]) */
604	and.b #1,crt0_csswitch
605
606	/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
607	bus width : 32 16 8 ext./dsackx */
608	rol.b #2,crt0_buswidth
609	and.b #3,crt0_buswidth
610
611	/----------------------------------------------------/
612	/* -- configure chip select 0 with boot prom width -- */
613	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
614	lea.l _table_cs349(%pc),crt0_ptr3
615	move.l (crt0_ptr3)+,crt0_temp
616	and.b #0xFC,crt0_temp \| clear PS0 & PS1
617	or.b crt0_buswidth,crt0_temp \| set boot PROM bus width
618	move.l crt0_temp,(crt0_ptr4)+
619
620	/------------------------/
621	/* -- read PDCS buffer -- */
622	moves.b REG_PDCS(crt0_glue),crt0_pdcs
623	/* move.b #0x3F,crt0_pdcs pour test */
624
625
626	/---------------------------------------/
627	/* -- EPLD chip-select initialization -- */
628	/---------------------------------------/
629	btst.b #0,crt0_csswitch
630	beq _cs_init_end
631
632	/--------------------------------------------/
633	/* 68349 generated /CS[3..0] must be disabled */
634	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
635	lea.l _table_cs349(%pc),crt0_ptr3
636	moveq.l #0x03,crt0_temp
637	_cs349_clear:
638	move.l (crt0_ptr3)+,(crt0_ptr4)+
639	move.l (crt0_ptr3)+,crt0_spare6
640	and.b #0xFE,crt0_spare6 \| disable chip-select
641	move.l crt0_spare6,(crt0_ptr4)+
642	dbra crt0_temp,_cs349_clear
643
644	/---------------------------------------------/
645	/* EPLD generated /CS[3..0] must be configured */
646	_csepld_init:
647	move.l crt0_glue,crt0_ptr4
648	lea.l _table_csepld(%pc),crt0_ptr3
649
650	move.b (crt0_ptr3)+,crt0_temp
651	or.b #0x20,crt0_temp \| default width is 32 bits
652	tst.b crt0_buswidth \| is boot PROM bus width 32 bits ?
653	beq _csepld1 \| if not
654	and.b #0xDF,crt0_temp \| set width to 16 bits
655	_csepld1:
656	moves.b crt0_temp,(crt0_ptr4)+
657
658	moveq.l #0x02,crt0_spare6
659	_csepld2:
660	move.b (crt0_ptr3)+,crt0_temp
661	moves.b crt0_temp,(crt0_ptr4)+
662	dbra crt0_spare6,_csepld2
663
664	_cs_init_end:
665
666	/--------------------------------------/
667	/* -- DRAM controller initialization -- */
668	_dram_init:
669	move.w #15,crt0_temp
670	move.l #_ExtRam_Start,crt0_ptr3
671
672	_dram_init1:
673	clr.l (crt0_ptr3)+ \| must access DRAM
674	dbra crt0_temp,_dram_init1 \| prior to init refresh
675
676	_dram_init2:
677	move.b #3,crt0_temp
678	moves.b crt0_temp,REG_WS(crt0_dram) \| set 3 wait-states
679
680	move.b #0x81,crt0_temp
681	moves.b crt0_temp,REG_REFRESH(crt0_dram) \| refresh every 10µs
682
683	move.b #0,crt0_temp
684	moves.b crt0_temp,REG_CONFIG(crt0_dram) \| default size = 4Mbytes
685
686	/-----------------------/
687	/* -- configure cache -- */
688	_init_cache:
689	move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
690	btst.b #bit_cache,crt0_pdcs
691	bne _init_cache_end
692	or.l #0x00000001,CACHE_MCR(crt0_sim_base)
693
694	_init_cache_end:
695
696	/-----------------------------/
697	/* -- timers initialization -- */
698
699	clr.b crt0_temp
700	moves.b crt0_temp,REG_TIMER1(crt0_glue) \| disable timer 1
701	moves.b crt0_temp,REG_TIMER2(crt0_glue) \| disable timer 2
702
703	/--------------------------/
704	/* -- I2C initialization -- */
705	move.b #3,crt0_temp
706	moves.b crt0_temp,REG_I2C(crt0_glue) \| tri-states I2C ports
707
708	/-----------------------------------------/
709	/* -- baudrate generator initialization -- */
710	move.b #2,crt0_temp
711	moves.b crt0_temp,REG_BAUDRATE(crt0_glue) \| baudrate = 38400
712
713	/-------------------------------/
714	/* -- IO port initialization -- */
715	clr.b crt0_temp
716	moves.b crt0_temp,REG_IO(crt0_glue) \| set port as input
717
718	/* -- */
719
720	move.l #68349,crt0_cpu_type
721
722
723	/* -- jump back to PROM -- */
724
725	jmp.l (_fill_test) \| must be absolute long
726
727	_copy_end_code:
728
729	/*-------------------------------------------------
730	initialization code for the 68340 board
731	-------------------------------------------------*/
732
733	/* Astecc 68340 board : chip-select initialization values */
734	_table_cs340:
735	dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
736	dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
737	dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
738	dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
739	dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
740	dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
741	dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
742	dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
743
744	cpu_is_68340:
745
746	/* -- set cpu clock -- */
747	move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) \| clock
748	sync_wait340:
749	btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
750	beq sync_wait340
751
752	/* -- chip select initialization -- */
753	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
754	lea.l _table_cs340(%pc),crt0_ptr3
755	moveq.l #0x07,crt0_temp
756	_b_cs340:
757	move.l (crt0_ptr3)+,crt0_ptr5
758	move.l crt0_ptr5,(crt0_ptr4)+ \| pour test
759	dbra crt0_temp,_b_cs340
760
761	move.l #68340,crt0_cpu_type
762	move.b #0,crt0_csswitch \| CPU
763	move.b #1,crt0_buswidth \| 16 bits
764
765
766	/*-------------------------------------------------
767	fill RAM if COLDSTART
768	-------------------------------------------------*/
769	_fill_test:
770
771	tst.l crt0_boot_type
772	bne _dont_fill
773
774	cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
775	bne _fill
776	btst.b #bit_meminit,crt0_pdcs
777	bne _dont_fill
778
779	/* fill main memory */
780	_fill:
781	move.l #_crt0_init_stack,crt0_ptr3 \| skip Astecc vars
782	move.l #_ExtRam_Start,crt0_temp
783	sub.l #_crt0_init_stack,crt0_temp
784	add.l #_ExtRam_Size,crt0_temp \| get size
785	lsr.l #2,crt0_temp \| ajust for long word
786	_fill_loop:
787	clr.l (crt0_ptr3)+
788	subq.l #1,crt0_temp
789	bne _fill_loop
790
791	cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
792	bne _fill_bccram
793
794	/* fill QDMM memory */
795	movea.l #_FastRam_Start,crt0_ptr3 \| get start
796	move.l #_FastRam_Size,crt0_temp \| get size
797	lsr.l #2,crt0_temp \| ajust for long word
798
799	_QDMMfill_loop:
800	clr.l (crt0_ptr3)+
801	subq.l #1,crt0_temp
802	bne _QDMMfill_loop
803	bra _dont_fill
804
805	/* fill BCC memory */
806	_fill_bccram:
807	movea.l #_BCCram_Start,crt0_ptr3 \| get start
808	move.l #_BCCram_Size,crt0_temp \| get size
809	lsr.l #2,crt0_temp \| ajust for long word
810	_BCCfill_loop:
811	clr.l (crt0_ptr3)+
812	subq.l #1,crt0_temp
813	bne _BCCfill_loop
814
815	-------------------------------------------------/
816	_dont_fill:
817	move.b crt0_csswitch,_AsteccCsSwitch
818	move.b crt0_buswidth,_AsteccBusWidth
819	move.l crt0_cpu_type,_AsteccCpuName
820
821	jmp SYM(_Init68340) \| Start C code (which never returns)
822
823	/*
824	* Copy DATA segment, clear BSS segment, set up real stack,
825	* initialize heap, start C program.
826	* Assume that DATA and BSS sizes are multiples of 4.
827	*/
828	PUBLIC (_CopyDataClearBSSAndStart)
829	SYM(_CopyDataClearBSSAndStart):
830	lea SYM(_copy_start),a0 \| Get start of DATA in RAM
831	lea SYM(_etext),a2 \| Get start of DATA in ROM
832	cmpl a0,a2 \| Are they the same?
833	beq.s NOCOPY \| Yes, no copy necessary
834	lea SYM(_copy_end),a1 \| Get end of DATA in RAM
835	bra.s COPYLOOPTEST \| Branch into copy loop
836	COPYLOOP:
837	movel a2@+,a0@+ \| Copy word from ROM to RAM
838	COPYLOOPTEST:
839	cmpl a1,a0 \| Done?
840	bcs.s COPYLOOP \| No, skip
841	NOCOPY:
842
843	lea _clear_start,a0 \| Get start of BSS
844	lea _clear_end,a1 \| Get end of BSS
845	clrl d0 \| Value to set
846	bra.s ZEROLOOPTEST \| Branch into clear loop
847	ZEROLOOP:
848	movel d0,a0@+ \| Clear a word
849	ZEROLOOPTEST:
850	cmpl a1,a0 \| Done?
851	bcs.s ZEROLOOP \| No, skip
852
853	movel #_stack_init,a7 \| set master stack pointer
854	movel d0,a7@- \| environp
855	movel d0,a7@- \| argv
856	movel d0,a7@- \| argc
857	jsr SYM(boot_card) \| Call C main
858
859	PUBLIC (_mainDone)
860	SYM(_mainDone):
861	nop \| Leave spot for breakpoint
862	movew #1,a7 \| Force a double bus error
863	movel d0,a7@- \| This should cause a RESET
864	/* stop #0x2700 \| Stop with interrupts disabled */
865	move.w #0x2700,sr
866	bra.l SYM(_mainDone) \| Stuck forever
867
868	.align 2
869	BEGIN_DATA_DCL
870	.align 2
871	PUBLIC (environ)
872	SYM (environ):
873	.long 0
874	PUBLIC (_M68kSpuriousInterruptCount)
875	SYM (_M68kSpuriousInterruptCount):
876	.long 0
877	END_DATA_DCL
878
879	END

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