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4.115

Last change on this file since c28f503 was c28f503, checked in by Joel Sherrill <joel.sherrill@…>, on 10/14/14 at 14:34:52
m68k/gen68340: Fix warnings
Property mode set to `100644`
File size: 24.8 KB

Line
1	/*
2	* This file contains the entry point for the application.
3	* The name of this entry point is compiler dependent.
4	* It jumps to the BSP which is responsible for performing
5	* all initialization.
6	*/
7
8	/*
9	* COPYRIGHT (c) 1989-1999.
10	* On-Line Applications Research Corporation (OAR).
11	*
12	* The license and distribution terms for this file may in
13	* the file LICENSE in this distribution or at
14	* http://www.rtems.org/license/LICENSE.
15	*
16	* Based on the `gen68360' board support package, and covered by the
17	* original distribution terms.
18	*
19	* Geoffroy Montel
20	* France Telecom - CNET/DSM/TAM/CAT
21	* 4, rue du Clos Courtel
22	* 35512 CESSON-SEVIGNE
23	* FRANCE
24	*
25	* e-mail: g_montel@yahoo.com
26	*/
27
28	#include <rtems/asm.h>
29	#include <m68349.inc>
30
31	#include <bsp.h> /* to indicate dependencies */
32
33	/* old addresses for AST68340 only, undefine for AST68349 */
34	#define _OLD_ASTECC 1
35
36	BEGIN_CODE
37	/*
38	* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
39	*/
40	Entry:
41	.long SYM(m340)+1024 \| 0: Initial SSP
42	.long start \| 1: Initial PC
43	.long SYM(_uhoh) \| 2: Bus error
44	.long SYM(_uhoh) \| 3: Address error
45	.long SYM(_uhoh) \| 4: Illegal instruction
46	.long SYM(_uhoh) \| 5: Zero division
47	.long SYM(_uhoh) \| 6: CHK, CHK2 instruction
48	.long SYM(_uhoh) \| 7: TRAPcc, TRAPV instructions
49	.long SYM(_uhoh) \| 8: Privilege violation
50	.long SYM(_uhoh) \| 9: Trace
51	.long SYM(_uhoh) \| 10: Line 1010 emulator
52	.long SYM(_uhoh) \| 11: Line 1111 emulator
53	.long SYM(_uhoh) \| 12: Hardware breakpoint
54	.long SYM(_uhoh) \| 13: Reserved for coprocessor violation
55	.long SYM(_uhoh) \| 14: Format error
56	.long SYM(_uhoh) \| 15: Uninitialized interrupt
57	.long SYM(_uhoh) \| 16: Unassigned, reserved
58	.long SYM(_uhoh) \| 17:
59	.long SYM(_uhoh) \| 18:
60	.long SYM(_uhoh) \| 19:
61	.long SYM(_uhoh) \| 20:
62	.long SYM(_uhoh) \| 21:
63	.long SYM(_uhoh) \| 22:
64	.long SYM(_uhoh) \| 23:
65	.long SYM(_spuriousInterrupt) \| 24: Spurious interrupt
66	.long SYM(_uhoh) \| 25: Level 1 interrupt autovector
67	.long SYM(_uhoh) \| 26: Level 2 interrupt autovector
68	.long SYM(_uhoh) \| 27: Level 3 interrupt autovector
69	.long SYM(_uhoh) \| 28: Level 4 interrupt autovector
70	.long SYM(_uhoh) \| 29: Level 5 interrupt autovector
71	.long SYM(_uhoh) \| 30: Level 6 interrupt autovector
72	.long SYM(_uhoh) \| 31: Level 7 interrupt autovector
73	.long SYM(_uhoh) \| 32: Trap instruction (0-15)
74	.long SYM(_uhoh) \| 33:
75	.long SYM(_uhoh) \| 34:
76	.long SYM(_uhoh) \| 35:
77	.long SYM(_uhoh) \| 36:
78	.long SYM(_uhoh) \| 37:
79	.long SYM(_uhoh) \| 38:
80	.long SYM(_uhoh) \| 39:
81	.long SYM(_uhoh) \| 40:
82	.long SYM(_uhoh) \| 41:
83	.long SYM(_uhoh) \| 42:
84	.long SYM(_uhoh) \| 43:
85	.long SYM(_uhoh) \| 44:
86	.long SYM(_uhoh) \| 45:
87	.long SYM(_uhoh) \| 46:
88	.long SYM(_uhoh) \| 47:
89	.long SYM(_uhoh) \| 48: Reserved for coprocessor
90	.long SYM(_uhoh) \| 49:
91	.long SYM(_uhoh) \| 50:
92	.long SYM(_uhoh) \| 51:
93	.long SYM(_uhoh) \| 52:
94	.long SYM(_uhoh) \| 53:
95	.long SYM(_uhoh) \| 54:
96	.long SYM(_uhoh) \| 55:
97	.long SYM(_uhoh) \| 56:
98	.long SYM(_uhoh) \| 57:
99	.long SYM(_uhoh) \| 58:
100	.long SYM(_uhoh) \| 59: Unassigned, reserved
101	.long SYM(_uhoh) \| 60:
102	.long SYM(_uhoh) \| 61:
103	.long SYM(_uhoh) \| 62:
104	.long SYM(_uhoh) \| 63:
105	.long SYM(_uhoh) \| 64: User defined vectors (192)
106	.long SYM(_uhoh) \| 65:
107	.long SYM(_uhoh) \| 66:
108	.long SYM(_uhoh) \| 67:
109	.long SYM(_uhoh) \| 68:
110	.long SYM(_uhoh) \| 69:
111	.long SYM(_uhoh) \| 70:
112	.long SYM(_uhoh) \| 71:
113	.long SYM(_uhoh) \| 72:
114	.long SYM(_uhoh) \| 73:
115	.long SYM(_uhoh) \| 74:
116	.long SYM(_uhoh) \| 75:
117	.long SYM(_uhoh) \| 76:
118	.long SYM(_uhoh) \| 77:
119	.long SYM(_uhoh) \| 78:
120	.long SYM(_uhoh) \| 79:
121	.long SYM(_uhoh) \| 80:
122	.long SYM(_uhoh) \| 81:
123	.long SYM(_uhoh) \| 82:
124	.long SYM(_uhoh) \| 83:
125	.long SYM(_uhoh) \| 84:
126	.long SYM(_uhoh) \| 85:
127	.long SYM(_uhoh) \| 86:
128	.long SYM(_uhoh) \| 87:
129	.long SYM(_uhoh) \| 88:
130	.long SYM(_uhoh) \| 89:
131	.long SYM(_uhoh) \| 90:
132	.long SYM(_uhoh) \| 91:
133	.long SYM(_uhoh) \| 92:
134	.long SYM(_uhoh) \| 93:
135	.long SYM(_uhoh) \| 94:
136	.long SYM(_uhoh) \| 95:
137	.long SYM(_uhoh) \| 96:
138	.long SYM(_uhoh) \| 97:
139	.long SYM(_uhoh) \| 98:
140	.long SYM(_uhoh) \| 99:
141	.long SYM(_uhoh) \| 100:
142	.long SYM(_uhoh) \| 101:
143	.long SYM(_uhoh) \| 102:
144	.long SYM(_uhoh) \| 103:
145	.long SYM(_uhoh) \| 104:
146	.long SYM(_uhoh) \| 105:
147	.long SYM(_uhoh) \| 106:
148	.long SYM(_uhoh) \| 107:
149	.long SYM(_uhoh) \| 108:
150	.long SYM(_uhoh) \| 109:
151	.long SYM(_uhoh) \| 110:
152	.long SYM(_uhoh) \| 111:
153	.long SYM(_uhoh) \| 112:
154	.long SYM(_uhoh) \| 113:
155	.long SYM(_uhoh) \| 114:
156	.long SYM(_uhoh) \| 115:
157	.long SYM(_uhoh) \| 116:
158	.long SYM(_uhoh) \| 117:
159	.long SYM(_uhoh) \| 118:
160	.long SYM(_uhoh) \| 119:
161	.long SYM(_uhoh) \| 120:
162	.long SYM(_uhoh) \| 121:
163	.long SYM(_uhoh) \| 122:
164	.long SYM(_uhoh) \| 123:
165	.long SYM(_uhoh) \| 124:
166	.long SYM(_uhoh) \| 125:
167	.long SYM(_uhoh) \| 126:
168	.long SYM(_uhoh) \| 127:
169	.long SYM(_uhoh) \| 128:
170	.long SYM(_uhoh) \| 129:
171	.long SYM(_uhoh) \| 130:
172	.long SYM(_uhoh) \| 131:
173	.long SYM(_uhoh) \| 132:
174	.long SYM(_uhoh) \| 133:
175	.long SYM(_uhoh) \| 134:
176	.long SYM(_uhoh) \| 135:
177	.long SYM(_uhoh) \| 136:
178	.long SYM(_uhoh) \| 137:
179	.long SYM(_uhoh) \| 138:
180	.long SYM(_uhoh) \| 139:
181	.long SYM(_uhoh) \| 140:
182	.long SYM(_uhoh) \| 141:
183	.long SYM(_uhoh) \| 142:
184	.long SYM(_uhoh) \| 143:
185	.long SYM(_uhoh) \| 144:
186	.long SYM(_uhoh) \| 145:
187	.long SYM(_uhoh) \| 146:
188	.long SYM(_uhoh) \| 147:
189	.long SYM(_uhoh) \| 148:
190	.long SYM(_uhoh) \| 149:
191	.long SYM(_uhoh) \| 150:
192	.long SYM(_uhoh) \| 151:
193	.long SYM(_uhoh) \| 152:
194	.long SYM(_uhoh) \| 153:
195	.long SYM(_uhoh) \| 154:
196	.long SYM(_uhoh) \| 155:
197	.long SYM(_uhoh) \| 156:
198	.long SYM(_uhoh) \| 157:
199	.long SYM(_uhoh) \| 158:
200	.long SYM(_uhoh) \| 159:
201	.long SYM(_uhoh) \| 160:
202	.long SYM(_uhoh) \| 161:
203	.long SYM(_uhoh) \| 162:
204	.long SYM(_uhoh) \| 163:
205	.long SYM(_uhoh) \| 164:
206	.long SYM(_uhoh) \| 165:
207	.long SYM(_uhoh) \| 166:
208	.long SYM(_uhoh) \| 167:
209	.long SYM(_uhoh) \| 168:
210	.long SYM(_uhoh) \| 169:
211	.long SYM(_uhoh) \| 170:
212	.long SYM(_uhoh) \| 171:
213	.long SYM(_uhoh) \| 172:
214	.long SYM(_uhoh) \| 173:
215	.long SYM(_uhoh) \| 174:
216	.long SYM(_uhoh) \| 175:
217	.long SYM(_uhoh) \| 176:
218	.long SYM(_uhoh) \| 177:
219	.long SYM(_uhoh) \| 178:
220	.long SYM(_uhoh) \| 179:
221	.long SYM(_uhoh) \| 180:
222	.long SYM(_uhoh) \| 181:
223	.long SYM(_uhoh) \| 182:
224	.long SYM(_uhoh) \| 183:
225	.long SYM(_uhoh) \| 184:
226	.long SYM(_uhoh) \| 185:
227	.long SYM(_uhoh) \| 186:
228	.long SYM(_uhoh) \| 187:
229	.long SYM(_uhoh) \| 188:
230	.long SYM(_uhoh) \| 189:
231	.long SYM(_uhoh) \| 190:
232	.long SYM(_uhoh) \| 191:
233	.long SYM(_uhoh) \| 192:
234	.long SYM(_uhoh) \| 193:
235	.long SYM(_uhoh) \| 194:
236	.long SYM(_uhoh) \| 195:
237	.long SYM(_uhoh) \| 196:
238	.long SYM(_uhoh) \| 197:
239	.long SYM(_uhoh) \| 198:
240	.long SYM(_uhoh) \| 199:
241	.long SYM(_uhoh) \| 200:
242	.long SYM(_uhoh) \| 201:
243	.long SYM(_uhoh) \| 202:
244	.long SYM(_uhoh) \| 203:
245	.long SYM(_uhoh) \| 204:
246	.long SYM(_uhoh) \| 205:
247	.long SYM(_uhoh) \| 206:
248	.long SYM(_uhoh) \| 207:
249	.long SYM(_uhoh) \| 208:
250	.long SYM(_uhoh) \| 209:
251	.long SYM(_uhoh) \| 210:
252	.long SYM(_uhoh) \| 211:
253	.long SYM(_uhoh) \| 212:
254	.long SYM(_uhoh) \| 213:
255	.long SYM(_uhoh) \| 214:
256	.long SYM(_uhoh) \| 215:
257	.long SYM(_uhoh) \| 216:
258	.long SYM(_uhoh) \| 217:
259	.long SYM(_uhoh) \| 218:
260	.long SYM(_uhoh) \| 219:
261	.long SYM(_uhoh) \| 220:
262	.long SYM(_uhoh) \| 221:
263	.long SYM(_uhoh) \| 222:
264	.long SYM(_uhoh) \| 223:
265	.long SYM(_uhoh) \| 224:
266	.long SYM(_uhoh) \| 225:
267	.long SYM(_uhoh) \| 226:
268	.long SYM(_uhoh) \| 227:
269	.long SYM(_uhoh) \| 228:
270	.long SYM(_uhoh) \| 229:
271	.long SYM(_uhoh) \| 230:
272	.long SYM(_uhoh) \| 231:
273	.long SYM(_uhoh) \| 232:
274	.long SYM(_uhoh) \| 233:
275	.long SYM(_uhoh) \| 234:
276	.long SYM(_uhoh) \| 235:
277	.long SYM(_uhoh) \| 236:
278	.long SYM(_uhoh) \| 237:
279	.long SYM(_uhoh) \| 238:
280	.long SYM(_uhoh) \| 239:
281	.long SYM(_uhoh) \| 240:
282	.long SYM(_uhoh) \| 241:
283	.long SYM(_uhoh) \| 242:
284	.long SYM(_uhoh) \| 243:
285	.long SYM(_uhoh) \| 244:
286	.long SYM(_uhoh) \| 245:
287	.long SYM(_uhoh) \| 246:
288	.long SYM(_uhoh) \| 247:
289	.long SYM(_uhoh) \| 248:
290	.long SYM(_uhoh) \| 249:
291	.long SYM(_uhoh) \| 250:
292	.long SYM(_uhoh) \| 251:
293	.long SYM(_uhoh) \| 252:
294	.long SYM(_uhoh) \| 253:
295	.long SYM(_uhoh) \| 254:
296	.long SYM(_uhoh) \| 255:
297
298	/*
299	* Default trap handler
300	* With an oscilloscope you can see AS* stop
301	*/
302	PUBLIC (_uhoh)
303	SYM(_uhoh): nop \| Leave spot for breakpoint
304	/* stop #0x2700 \| Stop with interrupts disabled */
305	move.w #0x2700,sr
306	move.w (a7),_boot_panic_registers+4 \| SR
307	move.l 2(a7),_boot_panic_registers \| PC
308	move.w 6(a7),_boot_panic_registers+6 \| format & vector
309	movem.l d0-d7/a0-a7, _boot_panic_registers+8
310	movec sfc, d0
311	movem.l d0, _boot_panic_registers+72
312	movec dfc, d0
313	movem.l d0, _boot_panic_registers+76
314	movec vbr, d0
315	movem.l d0, _boot_panic_registers+80
316	jmp SYM(_dbug_dumpanic)
317	bra.s _crt0_cold_start
318
319	/*
320	* Log, but otherwise ignore, spurious interrupts
321	*/
322	PUBLIC (_spuriousInterrupt)
323	SYM(_spuriousInterrupt):
324	addql #1,SYM(_M68kSpuriousInterruptCount)
325	rte
326
327	/*
328	* Place the low-order 3 octets of the board's ethernet address at
329	* a `well-known' fixed location relative to the startup location.
330	*/
331	.align 2
332	.word 0 \| Padding
333	ethernet_address_buffer:
334	.word 0x08F3 \| Default address
335	.word 0xDEAD
336	.word 0xCAFE
337
338	BEGIN_DATA
339
340	/* equates */
341
342	.equ _CPU340, 0x0
343	.equ _CPU349, 0x31
344
345	#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
346	.equ _EPLD_CS_BASE, 0x1
347	.equ _PROM_Start, 0x01000000 /* CS0 */
348	.equ _FLEX_Start, 0x08000000 /* CS2 */
349	.equ _I2C_Start, 0x0c000000 /* CS3 */
350
351	.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
352	.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
353
354	.equ _ExtRam_Start, 0x10000000 /* SRAM */
355	.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
356
357	.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
358	.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
359
360	#else /* new addresses for AST68349 and 68340 */
361
362	.equ _EPLD_CS_BASE, 0x5
363	.equ _PROM_Start, 0x50000000 /* CS0 */
364	.equ _FLEX_Start, 0x08000000 /* CS2 */
365	.equ _I2C_Start, 0x0c000000 /* CS3 */
366
367	.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
368	.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
369
370	.equ _ExtRam_Start, 0x80000000 /* DRAM */
371	.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
372
373	.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
374	.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
375	#endif
376
377	.equ _SPEED349, 0xD680 /* 24 Mhz */
378	.equ _SPEED340, 0xD700 /* 25 Mhz */
379	/* .equ _SPEED340, 0xCE00 16 Mhz */
380
381	#define crt0_boot_type d0 /* cold/warm start (must be D0) */
382	#define crt0_temp d1
383	#define crt0_cpu_type d2
384	#define crt0_csswitch d3
385	#define crt0_buswidth d4
386	#define crt0_pdcs d5
387	#define crt0_spare6 d6
388	#define crt0_spare7 d7
389	#define crt0_sim_base a0
390	#define crt0_glue a1
391	#define crt0_dram a2
392	#define crt0_ptr3 a3
393	#define crt0_ptr4 a4
394	#define crt0_ptr5 a5
395	#define crt0_ptr6 a6
396
397	/* -- PDCS buffer equates -- */
398	.equ pdcs_mask, 0x1F /* DRAM configuration */
399	.equ pdcs_sw12, 7 /* switch 12 */
400	.equ pdcs_sw11, 6 /* switch 11 */
401	.equ pdcs_sw14, 5 /* switch 14 */
402
403	.equ bit_cache, pdcs_sw12 /* enable cache if on */
404	.equ bit_meminit, pdcs_sw11 /* init memory if on */
405
406	/* -- Initialization stack and vars -- */
407
408	/* When using DWARF, everything must be a multiple of 16-bits. */
409	#if 1
410	_AsteccBusWidth: ds.w 0x0101
411	_AsteccCsSwitch: ds.w 0x0101
412	#else
413	_AsteccBusWidth: ds.b 1
414	_AsteccCsSwitch: ds.b 1
415	#endif
416	_AsteccCpuName: ds.l 1
417
418	.align 4
419
420	_crt0_init_stack:
421	ds.l 500
422	_crt0_init_stktop:
423
424	/* -- Initialization code -- */
425	BEGIN_CODE
426
427	.align 4
428	dc.l _crt0_init_stktop /* reset SP */
429	dc.l _crt0_cold_start /* reset PC */
430	dc.l _crt0_warm_start
431
432	/* When using DWARF, everything must be a multiple of 16-bits. */
433	.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards "
434	.text
435	dc.w 0
436	.align 4
437
438	.globl start
439	start:
440
441	_crt0_cold_start:
442	moveq.l #0,crt0_boot_type \| signal cold reset
443	bra.s _crt0_common_start
444
445	_crt0_warm_start:
446	moveq.l #1,crt0_boot_type \| signal warm reset
447
448	_crt0_common_start:
449	move.w #0x2700,sr \| disable interrupts and switch to interrupt mode
450	movea.l #_crt0_init_stktop,sp \| set up initialization stack
451
452	move.l #Entry,crt0_temp \| VBR initialization
453	movec.l crt0_temp,vbr \|
454	moveq.l #0x07,crt0_temp
455	movec.l crt0_temp,dfc \| prepare access in CPU space
456	move.l #(BASE_SIM+0x111),crt0_temp \| mask CPU, RESERVED USER SPACES
457	moves.l crt0_temp,BASE_REG \| base initialization (must be MOVES, PCC-130795)
458
459	movea.l #BASE_SIM,crt0_sim_base
460
461	/* -- disable Bus Monitor -- */
462	move.b #0,SIM_SYPCR(crt0_sim_base) \| system protection control register
463
464	/* -- enable A31-A24 -- */
465	clr.b SIM_PPRA1(crt0_sim_base)
466
467	/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
468	move.w #0x427F,SIM_MCR(crt0_sim_base)
469
470	/* -- enable /IRQ3, 5, 6, 7 -- */
471	move.b #0xE8,SIM_PPRB(crt0_sim_base)
472
473	/* -- enable autovector on /IRQ7 -- */
474	move.b #0x80,SIM_AVR(crt0_sim_base)
475
476	/* -- test CPU type -- */
477	cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
478	bne cpu_is_68340
479
480	/-------------------------------------------------------------------------------------------/
481	cpu_is_68349:
482
483	/* -- set cpu clock -- */
484	move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) \| clock
485
486	sync_wait349:
487	btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
488	beq sync_wait349
489
490	/* to allow access to the EPLD internal registers, it is necessary
491	to disable the global chip-select /CS0 (which decodes every external
492	cycles). To do that, we initialize the 68349 internal RAM,
493	copy a part of the initialization code in it, and jump there.
494	from that moment, /CS0 is not used, therefore it can be initialized
495	with its default value. Its width may be incorrect, but it will be
496	adjusted later. The goal is to avoid any conflict with
497	the accesses to the EPLD registers.
498	When this is done, we read the RESET parameters (boot prom width
499	and chip-select switch) and proceed with the initialization
500	when all is done, we jump back to the boot prom now
501	decoded with a properly configured /CS0 */
502
503	/-------------------------------------/
504	/* -- configure internal SRAM banks -- */
505
506	move.l #0x00000000,QDMM_MCR(crt0_sim_base)
507	move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
508	move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
509	move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
510	move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
511
512	/--------------------------------------------------------/
513	/* -- copy to address of the 68349 initialization code -- */
514
515	lea.l _copy_start_code(%pc),crt0_ptr3
516	lea.l _copy_end_code(%pc),crt0_ptr4
517	move.l crt0_ptr4,crt0_temp
518	sub.l crt0_ptr3,crt0_temp
519	add.l #3,crt0_temp \| adjust to next long word
520	lsr.l #2,crt0_temp
521
522	move.l #_FastRam_Start,crt0_ptr4
523	_copy_loop:
524	move.l (crt0_ptr3)+,(crt0_ptr4)+
525	subq.l #1,crt0_temp
526	bne.s _copy_loop
527	bra.l _FastRam_Start \| jump to code in internal RAM
528
529	/------------------------------------/
530	/* -- start of initialization code -- */
531
532	_copy_start_code:
533	bra.l _begin_68349_init
534
535	/----------------------------------------------------------/
536	/* Astecc 68349 board : chip-select initialization values */
537
538	_table_csepld:
539	/* When using DWARF, everything must be a multiple of 16-bits. */
540	#if 1
541	dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) \| 0x80 \| 16 bits, 0ws
542	dc.w 0x9090 \| 16 bits, ext /dsack
543
544	#else
545	dc.b (_EPLD_CS_BASE&0x0F)+0x80 \| 16 bits, 0ws
546	dc.b 0x80 \| 16 bits, 0 ws
547	dc.b 0x90 \| 16 bits, ext /dsack
548	dc.b 0x90 \| 16 bits, ext /dsack
549	#endif
550
551	_table_cs349:
552	dc.l 0x003FFFF4 \| Mask CS0 (4Mbytes PROM, 32bits, 1WS)
553	dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 \| Base CS0
554	dc.l 0x003FFFF1 \| MASK CS1 (4Mbytes RAM, 16bits, 0WS)
555	dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 \| Base CS1
556	dc.l 0x000000FF \| MASK CS2 (FLEX, ext DTACK, 256 bytes)
557	dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 \| Base CS2
558	dc.l 0x000000FF \| Mask CS3 (I2C, ext DTACK, 256 bytes)
559	dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 \| Base CS3
560
561	/-------------------------------------------------/
562	_begin_68349_init:
563
564	/-------------------------------------------------/
565	/* 68349 chip select initialization
566
567	at this stage, the width of /CS0 may be incorrect
568	it will be corrected later
569	*/
570
571	_cs68349_init:
572	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
573	lea.l _table_cs349(%pc),crt0_ptr3
574
575	moveq.l #0x07,crt0_temp
576	_cs349_init2:
577	move.l (crt0_ptr3)+,(crt0_ptr4)+
578	dbra crt0_temp,_cs349_init2
579
580	/-----------------------------------------------/
581	/* -- prepare access to the internal registers --*/
582	moveq.l #EPLD_SPACE,crt0_temp
583	movec.l crt0_temp,dfc
584	movec.l crt0_temp,sfc
585	move.l #GLUE_EPLD,crt0_glue
586	move.l #DRAM_EPLD,crt0_dram
587
588	/-------------------------------------------/
589	/* EPLD generated /CS[3..0] must be disabled */
590
591	_csepld_clear:
592	move.l crt0_glue,crt0_ptr4
593	move.w #3,crt0_spare6
594	clr.b crt0_temp
595
596	_csepld_clear1:
597	moves.b crt0_temp,(crt0_ptr4)+
598	dbra crt0_spare6,_csepld_clear1
599
600	/---------------------------------------------------------/
601	/* -- get width of boot PROM, and active chip-select set --*/
602	moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
603	move.b crt0_csswitch,crt0_buswidth
604
605	/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
606	: sel == 1 => EPLD chip_selects (/CS[3..0]) */
607	and.b #1,crt0_csswitch
608
609	/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
610	bus width : 32 16 8 ext./dsackx */
611	rol.b #2,crt0_buswidth
612	and.b #3,crt0_buswidth
613
614	/----------------------------------------------------/
615	/* -- configure chip select 0 with boot prom width -- */
616	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
617	lea.l _table_cs349(%pc),crt0_ptr3
618	move.l (crt0_ptr3)+,crt0_temp
619	and.b #0xFC,crt0_temp \| clear PS0 & PS1
620	or.b crt0_buswidth,crt0_temp \| set boot PROM bus width
621	move.l crt0_temp,(crt0_ptr4)+
622
623	/------------------------/
624	/* -- read PDCS buffer -- */
625	moves.b REG_PDCS(crt0_glue),crt0_pdcs
626	/* move.b #0x3F,crt0_pdcs pour test */
627
628	/---------------------------------------/
629	/* -- EPLD chip-select initialization -- */
630	/---------------------------------------/
631	btst.b #0,crt0_csswitch
632	beq _cs_init_end
633
634	/--------------------------------------------/
635	/* 68349 generated /CS[3..0] must be disabled */
636	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
637	lea.l _table_cs349(%pc),crt0_ptr3
638	moveq.l #0x03,crt0_temp
639	_cs349_clear:
640	move.l (crt0_ptr3)+,(crt0_ptr4)+
641	move.l (crt0_ptr3)+,crt0_spare6
642	and.b #0xFE,crt0_spare6 \| disable chip-select
643	move.l crt0_spare6,(crt0_ptr4)+
644	dbra crt0_temp,_cs349_clear
645
646	/---------------------------------------------/
647	/* EPLD generated /CS[3..0] must be configured */
648	_csepld_init:
649	move.l crt0_glue,crt0_ptr4
650	lea.l _table_csepld(%pc),crt0_ptr3
651
652	move.b (crt0_ptr3)+,crt0_temp
653	or.b #0x20,crt0_temp \| default width is 32 bits
654	tst.b crt0_buswidth \| is boot PROM bus width 32 bits ?
655	beq _csepld1 \| if not
656	and.b #0xDF,crt0_temp \| set width to 16 bits
657	_csepld1:
658	moves.b crt0_temp,(crt0_ptr4)+
659
660	moveq.l #0x02,crt0_spare6
661	_csepld2:
662	move.b (crt0_ptr3)+,crt0_temp
663	moves.b crt0_temp,(crt0_ptr4)+
664	dbra crt0_spare6,_csepld2
665
666	_cs_init_end:
667
668	/--------------------------------------/
669	/* -- DRAM controller initialization -- */
670	_dram_init:
671	move.w #15,crt0_temp
672	move.l #_ExtRam_Start,crt0_ptr3
673
674	_dram_init1:
675	clr.l (crt0_ptr3)+ \| must access DRAM
676	dbra crt0_temp,_dram_init1 \| prior to init refresh
677
678	_dram_init2:
679	move.b #3,crt0_temp
680	moves.b crt0_temp,REG_WS(crt0_dram) \| set 3 wait-states
681
682	move.b #0x81,crt0_temp
683	moves.b crt0_temp,REG_REFRESH(crt0_dram) \| refresh every 10Âµs
684
685	move.b #0,crt0_temp
686	moves.b crt0_temp,REG_CONFIG(crt0_dram) \| default size = 4Mbytes
687
688	/-----------------------/
689	/* -- configure cache -- */
690	_init_cache:
691	move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
692	btst.b #bit_cache,crt0_pdcs
693	bne _init_cache_end
694	or.l #0x00000001,CACHE_MCR(crt0_sim_base)
695
696	_init_cache_end:
697
698	/-----------------------------/
699	/* -- timers initialization -- */
700
701	clr.b crt0_temp
702	moves.b crt0_temp,REG_TIMER1(crt0_glue) \| disable timer 1
703	moves.b crt0_temp,REG_TIMER2(crt0_glue) \| disable timer 2
704
705	/--------------------------/
706	/* -- I2C initialization -- */
707	move.b #3,crt0_temp
708	moves.b crt0_temp,REG_I2C(crt0_glue) \| tri-states I2C ports
709
710	/-----------------------------------------/
711	/* -- baudrate generator initialization -- */
712	move.b #2,crt0_temp
713	moves.b crt0_temp,REG_BAUDRATE(crt0_glue) \| baudrate = 38400
714
715	/-------------------------------/
716	/* -- IO port initialization -- */
717	clr.b crt0_temp
718	moves.b crt0_temp,REG_IO(crt0_glue) \| set port as input
719
720	/* -- */
721
722	move.l #68349,crt0_cpu_type
723
724	/* -- jump back to PROM -- */
725
726	jmp.l (_fill_test) \| must be absolute long
727
728	_copy_end_code:
729
730	/*-------------------------------------------------
731	initialization code for the 68340 board
732	-------------------------------------------------*/
733
734	/* Astecc 68340 board : chip-select initialization values */
735	_table_cs340:
736	dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
737	dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
738	dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
739	dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
740	dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
741	dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
742	dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
743	dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
744
745	cpu_is_68340:
746
747	/* -- set cpu clock -- */
748	move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) \| clock
749	sync_wait340:
750	btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
751	beq sync_wait340
752
753	/* -- chip select initialization -- */
754	lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
755	lea.l _table_cs340(%pc),crt0_ptr3
756	moveq.l #0x07,crt0_temp
757	_b_cs340:
758	move.l (crt0_ptr3)+,crt0_ptr5
759	move.l crt0_ptr5,(crt0_ptr4)+ \| pour test
760	dbra crt0_temp,_b_cs340
761
762	move.l #68340,crt0_cpu_type
763	move.b #0,crt0_csswitch \| CPU
764	move.b #1,crt0_buswidth \| 16 bits
765
766	/*-------------------------------------------------
767	fill RAM if COLDSTART
768	-------------------------------------------------*/
769	_fill_test:
770
771	tst.l crt0_boot_type
772	bne _dont_fill
773
774	cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
775	bne _fill
776	btst.b #bit_meminit,crt0_pdcs
777	bne _dont_fill
778
779	/* fill main memory */
780	_fill:
781	move.l #_crt0_init_stack,crt0_ptr3 \| skip Astecc vars
782	move.l #_ExtRam_Start,crt0_temp
783	sub.l #_crt0_init_stack,crt0_temp
784	add.l #_ExtRam_Size,crt0_temp \| get size
785	lsr.l #2,crt0_temp \| ajust for long word
786	_fill_loop:
787	clr.l (crt0_ptr3)+
788	subq.l #1,crt0_temp
789	bne _fill_loop
790
791	cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
792	bne _fill_bccram
793
794	/* fill QDMM memory */
795	movea.l #_FastRam_Start,crt0_ptr3 \| get start
796	move.l #_FastRam_Size,crt0_temp \| get size
797	lsr.l #2,crt0_temp \| ajust for long word
798
799	_QDMMfill_loop:
800	clr.l (crt0_ptr3)+
801	subq.l #1,crt0_temp
802	bne _QDMMfill_loop
803	bra _dont_fill
804
805	/* fill BCC memory */
806	_fill_bccram:
807	movea.l #_BCCram_Start,crt0_ptr3 \| get start
808	move.l #_BCCram_Size,crt0_temp \| get size
809	lsr.l #2,crt0_temp \| ajust for long word
810	_BCCfill_loop:
811	clr.l (crt0_ptr3)+
812	subq.l #1,crt0_temp
813	bne _BCCfill_loop
814
815	/-------------------------------------------------/
816	_dont_fill:
817	move.b crt0_csswitch,_AsteccCsSwitch
818	move.b crt0_buswidth,_AsteccBusWidth
819	move.l crt0_cpu_type,_AsteccCpuName
820
821	jmp SYM(_Init68340) \| Start C code (which never returns)
822
823	/*
824	* Copy DATA segment, clear BSS segment, set up real stack,
825	* initialize heap, start C program.
826	* Assume that DATA and BSS sizes are multiples of 4.
827	*/
828	PUBLIC (_CopyDataClearBSSAndStart)
829	SYM(_CopyDataClearBSSAndStart):
830	lea SYM(_copy_start),a0 \| Get start of DATA in RAM
831	lea SYM(_etext),a2 \| Get start of DATA in ROM
832	cmpl a0,a2 \| Are they the same?
833	beq.s NOCOPY \| Yes, no copy necessary
834	lea SYM(_copy_end),a1 \| Get end of DATA in RAM
835	bra.s COPYLOOPTEST \| Branch into copy loop
836	COPYLOOP:
837	movel a2@+,a0@+ \| Copy word from ROM to RAM
838	COPYLOOPTEST:
839	cmpl a1,a0 \| Done?
840	bcs.s COPYLOOP \| No, skip
841	NOCOPY:
842
843	lea _clear_start,a0 \| Get start of BSS
844	lea _clear_end,a1 \| Get end of BSS
845	clrl d0 \| Value to set
846	bra.s ZEROLOOPTEST \| Branch into clear loop
847	ZEROLOOP:
848	movel d0,a0@+ \| Clear a word
849	ZEROLOOPTEST:
850	cmpl a1,a0 \| Done?
851	bcs.s ZEROLOOP \| No, skip
852
853	movel #_stack_init,a7 \| set master stack pointer
854	movel d0,a7@- \| command line
855	jsr SYM(boot_card) \| Call C main
856
857	PUBLIC (_mainDone)
858	SYM(_mainDone):
859	nop \| Leave spot for breakpoint
860	movew #1,a7 \| Force a double bus error
861	movel d0,a7@- \| This should cause a RESET
862	/* stop #0x2700 \| Stop with interrupts disabled */
863	move.w #0x2700,sr
864	bra.l SYM(_mainDone) \| Stuck forever
865
866	.align 2
867	BEGIN_DATA_DCL
868	.align 2
869	PUBLIC (environ)
870	SYM (environ):
871	.long 0
872	PUBLIC (_M68kSpuriousInterruptCount)
873	SYM (_M68kSpuriousInterruptCount):
874	.long 0
875	END_DATA_DCL
876
877	END

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