1 | /* |
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2 | * This file contains the entry point for the application. |
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3 | * The name of this entry point is compiler dependent. |
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4 | * It jumps to the BSP which is responsible for performing |
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5 | * all initialization. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-1999. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may in |
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11 | * the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * Based on the `gen68360' board support package, and covered by the |
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15 | * original distribution terms. |
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16 | * |
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17 | * Geoffroy Montel |
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18 | * France Telecom - CNET/DSM/TAM/CAT |
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19 | * 4, rue du Clos Courtel |
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20 | * 35512 CESSON-SEVIGNE |
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21 | * FRANCE |
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22 | * |
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23 | * e-mail: g_montel@yahoo.com |
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24 | * |
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25 | * $Id$ |
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26 | */ |
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27 | |
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28 | #include <rtems/asm.h> |
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29 | #include <m68349.inc> |
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30 | |
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31 | #define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ |
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32 | |
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33 | BEGIN_CODE |
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34 | /* |
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35 | * Step 1: Decide on Reset Stack Pointer and Initial Program Counter |
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36 | */ |
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37 | Entry: |
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38 | .long SYM(m340)+1024 | 0: Initial SSP |
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39 | .long start | 1: Initial PC |
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40 | .long SYM(_uhoh) | 2: Bus error |
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41 | .long SYM(_uhoh) | 3: Address error |
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42 | .long SYM(_uhoh) | 4: Illegal instruction |
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43 | .long SYM(_uhoh) | 5: Zero division |
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44 | .long SYM(_uhoh) | 6: CHK, CHK2 instruction |
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45 | .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions |
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46 | .long SYM(_uhoh) | 8: Privilege violation |
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47 | .long SYM(_uhoh) | 9: Trace |
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48 | .long SYM(_uhoh) | 10: Line 1010 emulator |
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49 | .long SYM(_uhoh) | 11: Line 1111 emulator |
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50 | .long SYM(_uhoh) | 12: Hardware breakpoint |
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51 | .long SYM(_uhoh) | 13: Reserved for coprocessor violation |
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52 | .long SYM(_uhoh) | 14: Format error |
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53 | .long SYM(_uhoh) | 15: Uninitialized interrupt |
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54 | .long SYM(_uhoh) | 16: Unassigned, reserved |
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55 | .long SYM(_uhoh) | 17: |
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56 | .long SYM(_uhoh) | 18: |
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57 | .long SYM(_uhoh) | 19: |
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58 | .long SYM(_uhoh) | 20: |
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59 | .long SYM(_uhoh) | 21: |
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60 | .long SYM(_uhoh) | 22: |
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61 | .long SYM(_uhoh) | 23: |
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62 | .long SYM(_spuriousInterrupt) | 24: Spurious interrupt |
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63 | .long SYM(_uhoh) | 25: Level 1 interrupt autovector |
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64 | .long SYM(_uhoh) | 26: Level 2 interrupt autovector |
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65 | .long SYM(_uhoh) | 27: Level 3 interrupt autovector |
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66 | .long SYM(_uhoh) | 28: Level 4 interrupt autovector |
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67 | .long SYM(_uhoh) | 29: Level 5 interrupt autovector |
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68 | .long SYM(_uhoh) | 30: Level 6 interrupt autovector |
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69 | .long SYM(_uhoh) | 31: Level 7 interrupt autovector |
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70 | .long SYM(_uhoh) | 32: Trap instruction (0-15) |
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71 | .long SYM(_uhoh) | 33: |
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72 | .long SYM(_uhoh) | 34: |
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73 | .long SYM(_uhoh) | 35: |
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74 | .long SYM(_uhoh) | 36: |
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75 | .long SYM(_uhoh) | 37: |
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76 | .long SYM(_uhoh) | 38: |
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77 | .long SYM(_uhoh) | 39: |
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78 | .long SYM(_uhoh) | 40: |
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79 | .long SYM(_uhoh) | 41: |
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80 | .long SYM(_uhoh) | 42: |
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81 | .long SYM(_uhoh) | 43: |
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82 | .long SYM(_uhoh) | 44: |
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83 | .long SYM(_uhoh) | 45: |
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84 | .long SYM(_uhoh) | 46: |
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85 | .long SYM(_uhoh) | 47: |
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86 | .long SYM(_uhoh) | 48: Reserved for coprocessor |
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87 | .long SYM(_uhoh) | 49: |
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88 | .long SYM(_uhoh) | 50: |
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89 | .long SYM(_uhoh) | 51: |
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90 | .long SYM(_uhoh) | 52: |
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91 | .long SYM(_uhoh) | 53: |
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92 | .long SYM(_uhoh) | 54: |
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93 | .long SYM(_uhoh) | 55: |
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94 | .long SYM(_uhoh) | 56: |
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95 | .long SYM(_uhoh) | 57: |
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96 | .long SYM(_uhoh) | 58: |
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97 | .long SYM(_uhoh) | 59: Unassigned, reserved |
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98 | .long SYM(_uhoh) | 60: |
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99 | .long SYM(_uhoh) | 61: |
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100 | .long SYM(_uhoh) | 62: |
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101 | .long SYM(_uhoh) | 63: |
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102 | .long SYM(_uhoh) | 64: User defined vectors (192) |
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103 | .long SYM(_uhoh) | 65: |
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104 | .long SYM(_uhoh) | 66: |
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105 | .long SYM(_uhoh) | 67: |
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106 | .long SYM(_uhoh) | 68: |
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107 | .long SYM(_uhoh) | 69: |
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108 | .long SYM(_uhoh) | 70: |
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109 | .long SYM(_uhoh) | 71: |
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110 | .long SYM(_uhoh) | 72: |
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111 | .long SYM(_uhoh) | 73: |
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112 | .long SYM(_uhoh) | 74: |
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113 | .long SYM(_uhoh) | 75: |
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114 | .long SYM(_uhoh) | 76: |
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115 | .long SYM(_uhoh) | 77: |
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116 | .long SYM(_uhoh) | 78: |
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117 | .long SYM(_uhoh) | 79: |
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118 | .long SYM(_uhoh) | 80: |
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119 | .long SYM(_uhoh) | 81: |
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120 | .long SYM(_uhoh) | 82: |
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121 | .long SYM(_uhoh) | 83: |
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122 | .long SYM(_uhoh) | 84: |
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123 | .long SYM(_uhoh) | 85: |
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124 | .long SYM(_uhoh) | 86: |
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125 | .long SYM(_uhoh) | 87: |
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126 | .long SYM(_uhoh) | 88: |
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127 | .long SYM(_uhoh) | 89: |
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128 | .long SYM(_uhoh) | 90: |
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129 | .long SYM(_uhoh) | 91: |
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130 | .long SYM(_uhoh) | 92: |
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131 | .long SYM(_uhoh) | 93: |
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132 | .long SYM(_uhoh) | 94: |
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133 | .long SYM(_uhoh) | 95: |
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134 | .long SYM(_uhoh) | 96: |
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135 | .long SYM(_uhoh) | 97: |
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136 | .long SYM(_uhoh) | 98: |
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137 | .long SYM(_uhoh) | 99: |
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138 | .long SYM(_uhoh) | 100: |
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139 | .long SYM(_uhoh) | 101: |
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140 | .long SYM(_uhoh) | 102: |
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141 | .long SYM(_uhoh) | 103: |
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142 | .long SYM(_uhoh) | 104: |
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143 | .long SYM(_uhoh) | 105: |
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144 | .long SYM(_uhoh) | 106: |
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145 | .long SYM(_uhoh) | 107: |
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146 | .long SYM(_uhoh) | 108: |
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147 | .long SYM(_uhoh) | 109: |
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148 | .long SYM(_uhoh) | 110: |
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149 | .long SYM(_uhoh) | 111: |
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150 | .long SYM(_uhoh) | 112: |
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151 | .long SYM(_uhoh) | 113: |
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152 | .long SYM(_uhoh) | 114: |
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153 | .long SYM(_uhoh) | 115: |
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154 | .long SYM(_uhoh) | 116: |
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155 | .long SYM(_uhoh) | 117: |
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156 | .long SYM(_uhoh) | 118: |
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157 | .long SYM(_uhoh) | 119: |
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158 | .long SYM(_uhoh) | 120: |
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159 | .long SYM(_uhoh) | 121: |
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160 | .long SYM(_uhoh) | 122: |
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161 | .long SYM(_uhoh) | 123: |
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162 | .long SYM(_uhoh) | 124: |
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163 | .long SYM(_uhoh) | 125: |
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164 | .long SYM(_uhoh) | 126: |
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165 | .long SYM(_uhoh) | 127: |
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166 | .long SYM(_uhoh) | 128: |
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167 | .long SYM(_uhoh) | 129: |
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168 | .long SYM(_uhoh) | 130: |
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169 | .long SYM(_uhoh) | 131: |
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170 | .long SYM(_uhoh) | 132: |
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171 | .long SYM(_uhoh) | 133: |
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172 | .long SYM(_uhoh) | 134: |
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173 | .long SYM(_uhoh) | 135: |
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174 | .long SYM(_uhoh) | 136: |
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175 | .long SYM(_uhoh) | 137: |
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176 | .long SYM(_uhoh) | 138: |
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177 | .long SYM(_uhoh) | 139: |
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178 | .long SYM(_uhoh) | 140: |
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179 | .long SYM(_uhoh) | 141: |
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180 | .long SYM(_uhoh) | 142: |
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181 | .long SYM(_uhoh) | 143: |
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182 | .long SYM(_uhoh) | 144: |
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183 | .long SYM(_uhoh) | 145: |
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184 | .long SYM(_uhoh) | 146: |
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185 | .long SYM(_uhoh) | 147: |
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186 | .long SYM(_uhoh) | 148: |
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187 | .long SYM(_uhoh) | 149: |
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188 | .long SYM(_uhoh) | 150: |
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189 | .long SYM(_uhoh) | 151: |
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190 | .long SYM(_uhoh) | 152: |
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191 | .long SYM(_uhoh) | 153: |
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192 | .long SYM(_uhoh) | 154: |
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193 | .long SYM(_uhoh) | 155: |
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194 | .long SYM(_uhoh) | 156: |
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195 | .long SYM(_uhoh) | 157: |
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196 | .long SYM(_uhoh) | 158: |
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197 | .long SYM(_uhoh) | 159: |
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198 | .long SYM(_uhoh) | 160: |
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199 | .long SYM(_uhoh) | 161: |
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200 | .long SYM(_uhoh) | 162: |
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201 | .long SYM(_uhoh) | 163: |
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202 | .long SYM(_uhoh) | 164: |
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203 | .long SYM(_uhoh) | 165: |
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204 | .long SYM(_uhoh) | 166: |
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205 | .long SYM(_uhoh) | 167: |
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206 | .long SYM(_uhoh) | 168: |
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207 | .long SYM(_uhoh) | 169: |
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208 | .long SYM(_uhoh) | 170: |
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209 | .long SYM(_uhoh) | 171: |
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210 | .long SYM(_uhoh) | 172: |
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211 | .long SYM(_uhoh) | 173: |
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212 | .long SYM(_uhoh) | 174: |
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213 | .long SYM(_uhoh) | 175: |
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214 | .long SYM(_uhoh) | 176: |
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215 | .long SYM(_uhoh) | 177: |
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216 | .long SYM(_uhoh) | 178: |
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217 | .long SYM(_uhoh) | 179: |
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218 | .long SYM(_uhoh) | 180: |
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219 | .long SYM(_uhoh) | 181: |
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220 | .long SYM(_uhoh) | 182: |
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221 | .long SYM(_uhoh) | 183: |
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222 | .long SYM(_uhoh) | 184: |
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223 | .long SYM(_uhoh) | 185: |
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224 | .long SYM(_uhoh) | 186: |
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225 | .long SYM(_uhoh) | 187: |
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226 | .long SYM(_uhoh) | 188: |
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227 | .long SYM(_uhoh) | 189: |
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228 | .long SYM(_uhoh) | 190: |
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229 | .long SYM(_uhoh) | 191: |
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230 | .long SYM(_uhoh) | 192: |
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231 | .long SYM(_uhoh) | 193: |
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232 | .long SYM(_uhoh) | 194: |
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233 | .long SYM(_uhoh) | 195: |
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234 | .long SYM(_uhoh) | 196: |
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235 | .long SYM(_uhoh) | 197: |
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236 | .long SYM(_uhoh) | 198: |
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237 | .long SYM(_uhoh) | 199: |
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238 | .long SYM(_uhoh) | 200: |
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239 | .long SYM(_uhoh) | 201: |
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240 | .long SYM(_uhoh) | 202: |
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241 | .long SYM(_uhoh) | 203: |
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242 | .long SYM(_uhoh) | 204: |
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243 | .long SYM(_uhoh) | 205: |
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244 | .long SYM(_uhoh) | 206: |
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245 | .long SYM(_uhoh) | 207: |
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246 | .long SYM(_uhoh) | 208: |
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247 | .long SYM(_uhoh) | 209: |
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248 | .long SYM(_uhoh) | 210: |
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249 | .long SYM(_uhoh) | 211: |
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250 | .long SYM(_uhoh) | 212: |
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251 | .long SYM(_uhoh) | 213: |
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252 | .long SYM(_uhoh) | 214: |
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253 | .long SYM(_uhoh) | 215: |
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254 | .long SYM(_uhoh) | 216: |
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255 | .long SYM(_uhoh) | 217: |
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256 | .long SYM(_uhoh) | 218: |
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257 | .long SYM(_uhoh) | 219: |
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258 | .long SYM(_uhoh) | 220: |
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259 | .long SYM(_uhoh) | 221: |
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260 | .long SYM(_uhoh) | 222: |
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261 | .long SYM(_uhoh) | 223: |
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262 | .long SYM(_uhoh) | 224: |
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263 | .long SYM(_uhoh) | 225: |
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264 | .long SYM(_uhoh) | 226: |
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265 | .long SYM(_uhoh) | 227: |
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266 | .long SYM(_uhoh) | 228: |
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267 | .long SYM(_uhoh) | 229: |
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268 | .long SYM(_uhoh) | 230: |
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269 | .long SYM(_uhoh) | 231: |
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270 | .long SYM(_uhoh) | 232: |
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271 | .long SYM(_uhoh) | 233: |
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272 | .long SYM(_uhoh) | 234: |
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273 | .long SYM(_uhoh) | 235: |
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274 | .long SYM(_uhoh) | 236: |
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275 | .long SYM(_uhoh) | 237: |
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276 | .long SYM(_uhoh) | 238: |
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277 | .long SYM(_uhoh) | 239: |
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278 | .long SYM(_uhoh) | 240: |
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279 | .long SYM(_uhoh) | 241: |
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280 | .long SYM(_uhoh) | 242: |
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281 | .long SYM(_uhoh) | 243: |
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282 | .long SYM(_uhoh) | 244: |
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283 | .long SYM(_uhoh) | 245: |
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284 | .long SYM(_uhoh) | 246: |
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285 | .long SYM(_uhoh) | 247: |
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286 | .long SYM(_uhoh) | 248: |
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287 | .long SYM(_uhoh) | 249: |
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288 | .long SYM(_uhoh) | 250: |
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289 | .long SYM(_uhoh) | 251: |
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290 | .long SYM(_uhoh) | 252: |
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291 | .long SYM(_uhoh) | 253: |
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292 | .long SYM(_uhoh) | 254: |
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293 | .long SYM(_uhoh) | 255: |
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294 | |
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295 | /* |
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296 | * Default trap handler |
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297 | * With an oscilloscope you can see AS* stop |
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298 | */ |
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299 | PUBLIC (_uhoh) |
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300 | SYM(_uhoh): nop | Leave spot for breakpoint |
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301 | /* stop #0x2700 | Stop with interrupts disabled */ |
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302 | move.w #0x2700,sr |
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303 | move.w (a7),_boot_panic_registers+4 | SR |
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304 | move.l 2(a7),_boot_panic_registers | PC |
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305 | move.w 6(a7),_boot_panic_registers+6 | format & vector |
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306 | movem.l d0-d7/a0-a7, _boot_panic_registers+8 |
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307 | movec sfc, d0 |
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308 | movem.l d0, _boot_panic_registers+72 |
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309 | movec dfc, d0 |
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310 | movem.l d0, _boot_panic_registers+76 |
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311 | movec vbr, d0 |
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312 | movem.l d0, _boot_panic_registers+80 |
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313 | jmp SYM(_dbug_dumpanic) |
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314 | bra.s _crt0_cold_start |
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315 | |
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316 | /* |
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317 | * Log, but otherwise ignore, spurious interrupts |
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318 | */ |
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319 | PUBLIC (_spuriousInterrupt) |
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320 | SYM(_spuriousInterrupt): |
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321 | addql #1,SYM(_M68kSpuriousInterruptCount) |
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322 | rte |
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323 | |
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324 | /* |
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325 | * Place the low-order 3 octets of the board's ethernet address at |
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326 | * a `well-known' fixed location relative to the startup location. |
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327 | */ |
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328 | .align 2 |
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329 | .word 0 | Padding |
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330 | ethernet_address_buffer: |
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331 | .word 0x08F3 | Default address |
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332 | .word 0xDEAD |
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333 | .word 0xCAFE |
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334 | |
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335 | BEGIN_DATA |
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336 | |
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337 | /* equates */ |
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338 | |
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339 | .equ _CPU340, 0x0 |
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340 | .equ _CPU349, 0x31 |
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341 | |
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342 | #ifdef _OLD_ASTECC /* old addresses for AST68340 only */ |
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343 | .equ _EPLD_CS_BASE, 0x1 |
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344 | .equ _PROM_Start, 0x01000000 /* CS0 */ |
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345 | .equ _FLEX_Start, 0x08000000 /* CS2 */ |
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346 | .equ _I2C_Start, 0x0c000000 /* CS3 */ |
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347 | |
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348 | .equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ |
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349 | .equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ |
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350 | |
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351 | .equ _ExtRam_Start, 0x10000000 /* SRAM */ |
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352 | .equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ |
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353 | |
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354 | .equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ |
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355 | .equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ |
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356 | |
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357 | #else /* new addresses for AST68349 and 68340 */ |
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358 | |
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359 | .equ _EPLD_CS_BASE, 0x5 |
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360 | .equ _PROM_Start, 0x50000000 /* CS0 */ |
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361 | .equ _FLEX_Start, 0x08000000 /* CS2 */ |
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362 | .equ _I2C_Start, 0x0c000000 /* CS3 */ |
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363 | |
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364 | .equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ |
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365 | .equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ |
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366 | |
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367 | .equ _ExtRam_Start, 0x80000000 /* DRAM */ |
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368 | .equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ |
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369 | |
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370 | .equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ |
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371 | .equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ |
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372 | #endif |
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373 | |
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374 | .equ _SPEED349, 0xD680 /* 24 Mhz */ |
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375 | .equ _SPEED340, 0xD700 /* 25 Mhz */ |
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376 | /* .equ _SPEED340, 0xCE00 16 Mhz */ |
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377 | |
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378 | #define crt0_boot_type d0 /* cold/warm start (must be D0) */ |
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379 | #define crt0_temp d1 |
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380 | #define crt0_cpu_type d2 |
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381 | #define crt0_csswitch d3 |
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382 | #define crt0_buswidth d4 |
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383 | #define crt0_pdcs d5 |
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384 | #define crt0_spare6 d6 |
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385 | #define crt0_spare7 d7 |
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386 | #define crt0_sim_base a0 |
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387 | #define crt0_glue a1 |
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388 | #define crt0_dram a2 |
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389 | #define crt0_ptr3 a3 |
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390 | #define crt0_ptr4 a4 |
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391 | #define crt0_ptr5 a5 |
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392 | #define crt0_ptr6 a6 |
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393 | |
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394 | /* -- PDCS buffer equates -- */ |
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395 | .equ pdcs_mask, 0x1F /* DRAM configuration */ |
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396 | .equ pdcs_sw12, 7 /* switch 12 */ |
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397 | .equ pdcs_sw11, 6 /* switch 11 */ |
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398 | .equ pdcs_sw14, 5 /* switch 14 */ |
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399 | |
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400 | .equ bit_cache, pdcs_sw12 /* enable cache if on */ |
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401 | .equ bit_meminit, pdcs_sw11 /* init memory if on */ |
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402 | |
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403 | /* -- Initialization stack and vars -- */ |
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404 | |
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405 | /* When using DWARF, everything must be a multiple of 16-bits. */ |
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406 | #if 1 |
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407 | _AsteccBusWidth: ds.w 0x0101 |
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408 | _AsteccCsSwitch: ds.w 0x0101 |
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409 | #else |
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410 | _AsteccBusWidth: ds.b 1 |
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411 | _AsteccCsSwitch: ds.b 1 |
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412 | #endif |
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413 | _AsteccCpuName: ds.l 1 |
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414 | |
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415 | .align 4 |
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416 | |
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417 | _crt0_init_stack: |
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418 | ds.l 500 |
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419 | _crt0_init_stktop: |
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420 | |
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421 | /* -- Initialization code -- */ |
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422 | BEGIN_CODE |
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423 | |
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424 | .align 4 |
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425 | dc.l _crt0_init_stktop /* reset SP */ |
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426 | dc.l _crt0_cold_start /* reset PC */ |
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427 | dc.l _crt0_warm_start |
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428 | |
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429 | /* When using DWARF, everything must be a multiple of 16-bits. */ |
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430 | .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards " |
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431 | .text |
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432 | dc.w 0 |
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433 | .align 4 |
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434 | |
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435 | .globl start |
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436 | start: |
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437 | |
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438 | _crt0_cold_start: |
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439 | moveq.l #0,crt0_boot_type | signal cold reset |
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440 | bra.s _crt0_common_start |
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441 | |
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442 | _crt0_warm_start: |
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443 | moveq.l #1,crt0_boot_type | signal warm reset |
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444 | |
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445 | _crt0_common_start: |
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446 | move.w #0x2700,sr | disable interrupts and switch to interrupt mode |
---|
447 | movea.l #_crt0_init_stktop,sp | set up initialization stack |
---|
448 | |
---|
449 | move.l #Entry,crt0_temp | VBR initialization |
---|
450 | movec.l crt0_temp,vbr | |
---|
451 | moveq.l #0x07,crt0_temp |
---|
452 | movec.l crt0_temp,dfc | prepare access in CPU space |
---|
453 | move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES |
---|
454 | moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) |
---|
455 | |
---|
456 | movea.l #BASE_SIM,crt0_sim_base |
---|
457 | |
---|
458 | /* -- disable Bus Monitor -- */ |
---|
459 | move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register |
---|
460 | |
---|
461 | /* -- enable A31-A24 -- */ |
---|
462 | clr.b SIM_PPRA1(crt0_sim_base) |
---|
463 | |
---|
464 | /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ |
---|
465 | move.w #0x427F,SIM_MCR(crt0_sim_base) |
---|
466 | |
---|
467 | /* -- enable /IRQ3, 5, 6, 7 -- */ |
---|
468 | move.b #0xE8,SIM_PPRB(crt0_sim_base) |
---|
469 | |
---|
470 | /* -- enable autovector on /IRQ7 -- */ |
---|
471 | move.b #0x80,SIM_AVR(crt0_sim_base) |
---|
472 | |
---|
473 | /* -- test CPU type -- */ |
---|
474 | cmp.b #_CPU349,SIM_IDR(crt0_sim_base) |
---|
475 | bne cpu_is_68340 |
---|
476 | |
---|
477 | /*-------------------------------------------------------------------------------------------*/ |
---|
478 | cpu_is_68349: |
---|
479 | |
---|
480 | /* -- set cpu clock -- */ |
---|
481 | move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock |
---|
482 | |
---|
483 | sync_wait349: |
---|
484 | btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) |
---|
485 | beq sync_wait349 |
---|
486 | |
---|
487 | /* to allow access to the EPLD internal registers, it is necessary |
---|
488 | to disable the global chip-select /CS0 (which decodes every external |
---|
489 | cycles). To do that, we initialize the 68349 internal RAM, |
---|
490 | copy a part of the initialization code in it, and jump there. |
---|
491 | from that moment, /CS0 is not used, therefore it can be initialized |
---|
492 | with its default value. Its width may be incorrect, but it will be |
---|
493 | adjusted later. The goal is to avoid any conflict with |
---|
494 | the accesses to the EPLD registers. |
---|
495 | When this is done, we read the RESET parameters (boot prom width |
---|
496 | and chip-select switch) and proceed with the initialization |
---|
497 | when all is done, we jump back to the boot prom now |
---|
498 | decoded with a properly configured /CS0 */ |
---|
499 | |
---|
500 | /*-------------------------------------*/ |
---|
501 | /* -- configure internal SRAM banks -- */ |
---|
502 | |
---|
503 | move.l #0x00000000,QDMM_MCR(crt0_sim_base) |
---|
504 | move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) |
---|
505 | move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) |
---|
506 | move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) |
---|
507 | move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) |
---|
508 | |
---|
509 | /*--------------------------------------------------------*/ |
---|
510 | /* -- copy to address of the 68349 initialization code -- */ |
---|
511 | |
---|
512 | lea.l _copy_start_code(%pc),crt0_ptr3 |
---|
513 | lea.l _copy_end_code(%pc),crt0_ptr4 |
---|
514 | move.l crt0_ptr4,crt0_temp |
---|
515 | sub.l crt0_ptr3,crt0_temp |
---|
516 | add.l #3,crt0_temp | adjust to next long word |
---|
517 | lsr.l #2,crt0_temp |
---|
518 | |
---|
519 | move.l #_FastRam_Start,crt0_ptr4 |
---|
520 | _copy_loop: |
---|
521 | move.l (crt0_ptr3)+,(crt0_ptr4)+ |
---|
522 | subq.l #1,crt0_temp |
---|
523 | bne.s _copy_loop |
---|
524 | bra.l _FastRam_Start | jump to code in internal RAM |
---|
525 | |
---|
526 | /*------------------------------------*/ |
---|
527 | /* -- start of initialization code -- */ |
---|
528 | |
---|
529 | _copy_start_code: |
---|
530 | bra.l _begin_68349_init |
---|
531 | |
---|
532 | /*----------------------------------------------------------*/ |
---|
533 | /* Astecc 68349 board : chip-select initialization values */ |
---|
534 | |
---|
535 | _table_csepld: |
---|
536 | /* When using DWARF, everything must be a multiple of 16-bits. */ |
---|
537 | #if 1 |
---|
538 | dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) | 0x80 | 16 bits, 0ws |
---|
539 | dc.w 0x9090 | 16 bits, ext /dsack |
---|
540 | |
---|
541 | #else |
---|
542 | dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws |
---|
543 | dc.b 0x80 | 16 bits, 0 ws |
---|
544 | dc.b 0x90 | 16 bits, ext /dsack |
---|
545 | dc.b 0x90 | 16 bits, ext /dsack |
---|
546 | #endif |
---|
547 | |
---|
548 | _table_cs349: |
---|
549 | dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) |
---|
550 | dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 |
---|
551 | dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) |
---|
552 | dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 |
---|
553 | dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) |
---|
554 | dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 |
---|
555 | dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) |
---|
556 | dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 |
---|
557 | |
---|
558 | /*-------------------------------------------------*/ |
---|
559 | _begin_68349_init: |
---|
560 | |
---|
561 | /*-------------------------------------------------*/ |
---|
562 | /* 68349 chip select initialization |
---|
563 | |
---|
564 | at this stage, the width of /CS0 may be incorrect |
---|
565 | it will be corrected later |
---|
566 | */ |
---|
567 | |
---|
568 | _cs68349_init: |
---|
569 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
---|
570 | lea.l _table_cs349(%pc),crt0_ptr3 |
---|
571 | |
---|
572 | moveq.l #0x07,crt0_temp |
---|
573 | _cs349_init2: |
---|
574 | move.l (crt0_ptr3)+,(crt0_ptr4)+ |
---|
575 | dbra crt0_temp,_cs349_init2 |
---|
576 | |
---|
577 | /*-----------------------------------------------*/ |
---|
578 | /* -- prepare access to the internal registers --*/ |
---|
579 | moveq.l #EPLD_SPACE,crt0_temp |
---|
580 | movec.l crt0_temp,dfc |
---|
581 | movec.l crt0_temp,sfc |
---|
582 | move.l #GLUE_EPLD,crt0_glue |
---|
583 | move.l #DRAM_EPLD,crt0_dram |
---|
584 | |
---|
585 | /*-------------------------------------------*/ |
---|
586 | /* EPLD generated /CS[3..0] must be disabled */ |
---|
587 | |
---|
588 | _csepld_clear: |
---|
589 | move.l crt0_glue,crt0_ptr4 |
---|
590 | move.w #3,crt0_spare6 |
---|
591 | clr.b crt0_temp |
---|
592 | |
---|
593 | _csepld_clear1: |
---|
594 | moves.b crt0_temp,(crt0_ptr4)+ |
---|
595 | dbra crt0_spare6,_csepld_clear1 |
---|
596 | |
---|
597 | /*---------------------------------------------------------*/ |
---|
598 | /* -- get width of boot PROM, and active chip-select set --*/ |
---|
599 | moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch |
---|
600 | move.b crt0_csswitch,crt0_buswidth |
---|
601 | |
---|
602 | /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) |
---|
603 | : sel == 1 => EPLD chip_selects (/CS[3..0]) */ |
---|
604 | and.b #1,crt0_csswitch |
---|
605 | |
---|
606 | /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 |
---|
607 | bus width : 32 16 8 ext./dsackx */ |
---|
608 | rol.b #2,crt0_buswidth |
---|
609 | and.b #3,crt0_buswidth |
---|
610 | |
---|
611 | /*----------------------------------------------------*/ |
---|
612 | /* -- configure chip select 0 with boot prom width -- */ |
---|
613 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
---|
614 | lea.l _table_cs349(%pc),crt0_ptr3 |
---|
615 | move.l (crt0_ptr3)+,crt0_temp |
---|
616 | and.b #0xFC,crt0_temp | clear PS0 & PS1 |
---|
617 | or.b crt0_buswidth,crt0_temp | set boot PROM bus width |
---|
618 | move.l crt0_temp,(crt0_ptr4)+ |
---|
619 | |
---|
620 | /*------------------------*/ |
---|
621 | /* -- read PDCS buffer -- */ |
---|
622 | moves.b REG_PDCS(crt0_glue),crt0_pdcs |
---|
623 | /* move.b #0x3F,crt0_pdcs pour test */ |
---|
624 | |
---|
625 | /*---------------------------------------*/ |
---|
626 | /* -- EPLD chip-select initialization -- */ |
---|
627 | /*---------------------------------------*/ |
---|
628 | btst.b #0,crt0_csswitch |
---|
629 | beq _cs_init_end |
---|
630 | |
---|
631 | /*--------------------------------------------*/ |
---|
632 | /* 68349 generated /CS[3..0] must be disabled */ |
---|
633 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
---|
634 | lea.l _table_cs349(%pc),crt0_ptr3 |
---|
635 | moveq.l #0x03,crt0_temp |
---|
636 | _cs349_clear: |
---|
637 | move.l (crt0_ptr3)+,(crt0_ptr4)+ |
---|
638 | move.l (crt0_ptr3)+,crt0_spare6 |
---|
639 | and.b #0xFE,crt0_spare6 | disable chip-select |
---|
640 | move.l crt0_spare6,(crt0_ptr4)+ |
---|
641 | dbra crt0_temp,_cs349_clear |
---|
642 | |
---|
643 | /*---------------------------------------------*/ |
---|
644 | /* EPLD generated /CS[3..0] must be configured */ |
---|
645 | _csepld_init: |
---|
646 | move.l crt0_glue,crt0_ptr4 |
---|
647 | lea.l _table_csepld(%pc),crt0_ptr3 |
---|
648 | |
---|
649 | move.b (crt0_ptr3)+,crt0_temp |
---|
650 | or.b #0x20,crt0_temp | default width is 32 bits |
---|
651 | tst.b crt0_buswidth | is boot PROM bus width 32 bits ? |
---|
652 | beq _csepld1 | if not |
---|
653 | and.b #0xDF,crt0_temp | set width to 16 bits |
---|
654 | _csepld1: |
---|
655 | moves.b crt0_temp,(crt0_ptr4)+ |
---|
656 | |
---|
657 | moveq.l #0x02,crt0_spare6 |
---|
658 | _csepld2: |
---|
659 | move.b (crt0_ptr3)+,crt0_temp |
---|
660 | moves.b crt0_temp,(crt0_ptr4)+ |
---|
661 | dbra crt0_spare6,_csepld2 |
---|
662 | |
---|
663 | _cs_init_end: |
---|
664 | |
---|
665 | /*--------------------------------------*/ |
---|
666 | /* -- DRAM controller initialization -- */ |
---|
667 | _dram_init: |
---|
668 | move.w #15,crt0_temp |
---|
669 | move.l #_ExtRam_Start,crt0_ptr3 |
---|
670 | |
---|
671 | _dram_init1: |
---|
672 | clr.l (crt0_ptr3)+ | must access DRAM |
---|
673 | dbra crt0_temp,_dram_init1 | prior to init refresh |
---|
674 | |
---|
675 | _dram_init2: |
---|
676 | move.b #3,crt0_temp |
---|
677 | moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states |
---|
678 | |
---|
679 | move.b #0x81,crt0_temp |
---|
680 | moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs |
---|
681 | |
---|
682 | move.b #0,crt0_temp |
---|
683 | moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes |
---|
684 | |
---|
685 | /*-----------------------*/ |
---|
686 | /* -- configure cache -- */ |
---|
687 | _init_cache: |
---|
688 | move.l #0x000001E0,CACHE_MCR(crt0_sim_base) |
---|
689 | btst.b #bit_cache,crt0_pdcs |
---|
690 | bne _init_cache_end |
---|
691 | or.l #0x00000001,CACHE_MCR(crt0_sim_base) |
---|
692 | |
---|
693 | _init_cache_end: |
---|
694 | |
---|
695 | /*-----------------------------*/ |
---|
696 | /* -- timers initialization -- */ |
---|
697 | |
---|
698 | clr.b crt0_temp |
---|
699 | moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 |
---|
700 | moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 |
---|
701 | |
---|
702 | /*--------------------------*/ |
---|
703 | /* -- I2C initialization -- */ |
---|
704 | move.b #3,crt0_temp |
---|
705 | moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports |
---|
706 | |
---|
707 | /*-----------------------------------------*/ |
---|
708 | /* -- baudrate generator initialization -- */ |
---|
709 | move.b #2,crt0_temp |
---|
710 | moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 |
---|
711 | |
---|
712 | /*-------------------------------*/ |
---|
713 | /* -- IO port initialization -- */ |
---|
714 | clr.b crt0_temp |
---|
715 | moves.b crt0_temp,REG_IO(crt0_glue) | set port as input |
---|
716 | |
---|
717 | /* -- */ |
---|
718 | |
---|
719 | move.l #68349,crt0_cpu_type |
---|
720 | |
---|
721 | /* -- jump back to PROM -- */ |
---|
722 | |
---|
723 | jmp.l (_fill_test) | must be absolute long |
---|
724 | |
---|
725 | _copy_end_code: |
---|
726 | |
---|
727 | /*------------------------------------------------- |
---|
728 | initialization code for the 68340 board |
---|
729 | -------------------------------------------------*/ |
---|
730 | |
---|
731 | /* Astecc 68340 board : chip-select initialization values */ |
---|
732 | _table_cs340: |
---|
733 | dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ |
---|
734 | dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ |
---|
735 | dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ |
---|
736 | dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ |
---|
737 | dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ |
---|
738 | dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ |
---|
739 | dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ |
---|
740 | dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ |
---|
741 | |
---|
742 | cpu_is_68340: |
---|
743 | |
---|
744 | /* -- set cpu clock -- */ |
---|
745 | move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock |
---|
746 | sync_wait340: |
---|
747 | btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) |
---|
748 | beq sync_wait340 |
---|
749 | |
---|
750 | /* -- chip select initialization -- */ |
---|
751 | lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 |
---|
752 | lea.l _table_cs340(%pc),crt0_ptr3 |
---|
753 | moveq.l #0x07,crt0_temp |
---|
754 | _b_cs340: |
---|
755 | move.l (crt0_ptr3)+,crt0_ptr5 |
---|
756 | move.l crt0_ptr5,(crt0_ptr4)+ | pour test |
---|
757 | dbra crt0_temp,_b_cs340 |
---|
758 | |
---|
759 | move.l #68340,crt0_cpu_type |
---|
760 | move.b #0,crt0_csswitch | CPU |
---|
761 | move.b #1,crt0_buswidth | 16 bits |
---|
762 | |
---|
763 | /*------------------------------------------------- |
---|
764 | fill RAM if COLDSTART |
---|
765 | -------------------------------------------------*/ |
---|
766 | _fill_test: |
---|
767 | |
---|
768 | tst.l crt0_boot_type |
---|
769 | bne _dont_fill |
---|
770 | |
---|
771 | cmp.b #_CPU349,SIM_IDR(crt0_sim_base) |
---|
772 | bne _fill |
---|
773 | btst.b #bit_meminit,crt0_pdcs |
---|
774 | bne _dont_fill |
---|
775 | |
---|
776 | /* fill main memory */ |
---|
777 | _fill: |
---|
778 | move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars |
---|
779 | move.l #_ExtRam_Start,crt0_temp |
---|
780 | sub.l #_crt0_init_stack,crt0_temp |
---|
781 | add.l #_ExtRam_Size,crt0_temp | get size |
---|
782 | lsr.l #2,crt0_temp | ajust for long word |
---|
783 | _fill_loop: |
---|
784 | clr.l (crt0_ptr3)+ |
---|
785 | subq.l #1,crt0_temp |
---|
786 | bne _fill_loop |
---|
787 | |
---|
788 | cmp.b #_CPU349,SIM_IDR(crt0_sim_base) |
---|
789 | bne _fill_bccram |
---|
790 | |
---|
791 | /* fill QDMM memory */ |
---|
792 | movea.l #_FastRam_Start,crt0_ptr3 | get start |
---|
793 | move.l #_FastRam_Size,crt0_temp | get size |
---|
794 | lsr.l #2,crt0_temp | ajust for long word |
---|
795 | |
---|
796 | _QDMMfill_loop: |
---|
797 | clr.l (crt0_ptr3)+ |
---|
798 | subq.l #1,crt0_temp |
---|
799 | bne _QDMMfill_loop |
---|
800 | bra _dont_fill |
---|
801 | |
---|
802 | /* fill BCC memory */ |
---|
803 | _fill_bccram: |
---|
804 | movea.l #_BCCram_Start,crt0_ptr3 | get start |
---|
805 | move.l #_BCCram_Size,crt0_temp | get size |
---|
806 | lsr.l #2,crt0_temp | ajust for long word |
---|
807 | _BCCfill_loop: |
---|
808 | clr.l (crt0_ptr3)+ |
---|
809 | subq.l #1,crt0_temp |
---|
810 | bne _BCCfill_loop |
---|
811 | |
---|
812 | *-------------------------------------------------*/ |
---|
813 | _dont_fill: |
---|
814 | move.b crt0_csswitch,_AsteccCsSwitch |
---|
815 | move.b crt0_buswidth,_AsteccBusWidth |
---|
816 | move.l crt0_cpu_type,_AsteccCpuName |
---|
817 | |
---|
818 | jmp SYM(_Init68340) | Start C code (which never returns) |
---|
819 | |
---|
820 | /* |
---|
821 | * Copy DATA segment, clear BSS segment, set up real stack, |
---|
822 | * initialize heap, start C program. |
---|
823 | * Assume that DATA and BSS sizes are multiples of 4. |
---|
824 | */ |
---|
825 | PUBLIC (_CopyDataClearBSSAndStart) |
---|
826 | SYM(_CopyDataClearBSSAndStart): |
---|
827 | lea SYM(_copy_start),a0 | Get start of DATA in RAM |
---|
828 | lea SYM(_etext),a2 | Get start of DATA in ROM |
---|
829 | cmpl a0,a2 | Are they the same? |
---|
830 | beq.s NOCOPY | Yes, no copy necessary |
---|
831 | lea SYM(_copy_end),a1 | Get end of DATA in RAM |
---|
832 | bra.s COPYLOOPTEST | Branch into copy loop |
---|
833 | COPYLOOP: |
---|
834 | movel a2@+,a0@+ | Copy word from ROM to RAM |
---|
835 | COPYLOOPTEST: |
---|
836 | cmpl a1,a0 | Done? |
---|
837 | bcs.s COPYLOOP | No, skip |
---|
838 | NOCOPY: |
---|
839 | |
---|
840 | lea _clear_start,a0 | Get start of BSS |
---|
841 | lea _clear_end,a1 | Get end of BSS |
---|
842 | clrl d0 | Value to set |
---|
843 | bra.s ZEROLOOPTEST | Branch into clear loop |
---|
844 | ZEROLOOP: |
---|
845 | movel d0,a0@+ | Clear a word |
---|
846 | ZEROLOOPTEST: |
---|
847 | cmpl a1,a0 | Done? |
---|
848 | bcs.s ZEROLOOP | No, skip |
---|
849 | |
---|
850 | movel #_stack_init,a7 | set master stack pointer |
---|
851 | movel d0,a7@- | command line |
---|
852 | jsr SYM(boot_card) | Call C main |
---|
853 | |
---|
854 | PUBLIC (_mainDone) |
---|
855 | SYM(_mainDone): |
---|
856 | nop | Leave spot for breakpoint |
---|
857 | movew #1,a7 | Force a double bus error |
---|
858 | movel d0,a7@- | This should cause a RESET |
---|
859 | /* stop #0x2700 | Stop with interrupts disabled */ |
---|
860 | move.w #0x2700,sr |
---|
861 | bra.l SYM(_mainDone) | Stuck forever |
---|
862 | |
---|
863 | .align 2 |
---|
864 | BEGIN_DATA_DCL |
---|
865 | .align 2 |
---|
866 | PUBLIC (environ) |
---|
867 | SYM (environ): |
---|
868 | .long 0 |
---|
869 | PUBLIC (_M68kSpuriousInterruptCount) |
---|
870 | SYM (_M68kSpuriousInterruptCount): |
---|
871 | .long 0 |
---|
872 | END_DATA_DCL |
---|
873 | |
---|
874 | END |
---|