| 1 | /*---------------------------------------------------------------------------- |
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| 2 | * file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT |
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| 3 | * |
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| 4 | * MC68349 BCC Board Support Package |
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| 5 | * |
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| 6 | * date: 31/07/97 |
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| 7 | * |
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| 8 | * Description: EQUATES FOR 68349 DEVICES |
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| 9 | * |
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| 10 | * Modifications: |
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| 11 | * - adapted for GNU CC by G.Montel 26/05/98 |
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| 12 | *----------------------------------------------------------------------------*/ |
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| 13 | |
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| 14 | | -- SIM equates -- |
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| 15 | |
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| 16 | .equ BASE_REG, 0x3FF00 |
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| 17 | .equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK |
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| 18 | |
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| 19 | .equ SIM_MCR, 0x000 | module configuration register |
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| 20 | .equ SIM_IDR, 0x002 | processor identification register |
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| 21 | .equ SIM_SYNCR, 0x004 | clock synthesizer control register |
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| 22 | .equ SIM_AVR, 0x006 | autovector register |
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| 23 | .equ SIM_RSR, 0x007 | reset status register |
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| 24 | |
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| 25 | | -- Port A |
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| 26 | .equ SIM_PORTA, 0x011 | port A data |
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| 27 | .equ SIM_DDRA, 0x013 | port A direction data |
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| 28 | .equ SIM_PPRA1, 0x015 | Port A pin assignement 1 |
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| 29 | .equ SIM_PPRA2, 0x017 | Port A pin assignement 2 |
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| 30 | |
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| 31 | | -- Port B |
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| 32 | .equ SIM_PORTB, 0x019 | port B data |
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| 33 | .equ SIM_PORTB1, 0x01B | port B data auxiliary |
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| 34 | .equ SIM_DDRB, 0x01D | port B direction data |
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| 35 | .equ SIM_PPRB, 0x01F | Port B pin assignement |
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| 36 | |
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| 37 | .equ SIM_SWIV, 0x020 | SW interrupt vector |
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| 38 | .equ SIM_SYPCR, 0x021 | System protection control register |
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| 39 | .equ SIM_PICR, 0x022 | Periodic interrupt control register |
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| 40 | .equ SIM_PITR, 0x024 | Periodic interrupt timing register |
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| 41 | .equ SIM_SWSR, 0x027 | Sofware service |
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| 42 | |
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| 43 | | -- Chip select |
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| 44 | .equ SIM_MASKH0, 0x040 | mask register CS0 |
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| 45 | .equ SIM_MASKL0, 0x042 | mask register CS0 |
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| 46 | .equ SIM_ADDRH0, 0x044 | base address CS0 |
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| 47 | .equ SIM_ADDRL0, 0x046 | base address CS0 |
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| 48 | |
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| 49 | .equ SIM_MASKH1, 0x048 | mask register CS1 |
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| 50 | .equ SIM_MASKL1, 0x04A | mask register CS1 |
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| 51 | .equ SIM_ADDRH1, 0x04C | base address CS1 |
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| 52 | .equ SIM_ADDRL1, 0x04E | base address CS1 |
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| 53 | |
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| 54 | .equ SIM_MASKH2, 0x050 | mask register CS2 |
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| 55 | .equ SIM_MASKL2, 0x052 | mask register CS2 |
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| 56 | .equ SIM_ADDRH2, 0x054 | base address CS2 |
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| 57 | .equ SIM_ADDRL2, 0x056 | base address CS2 |
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| 58 | |
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| 59 | .equ SIM_MASKH3, 0x058 | mask register CS3 |
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| 60 | .equ SIM_MASKL3, 0x05A | mask register CS3 |
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| 61 | .equ SIM_ADDRH3, 0x05C | base address CS3 |
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| 62 | .equ SIM_ADDRL3, 0x05E | base address CS3 |
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| 63 | |
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| 64 | | -- TIMERS equates -- |
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| 65 | |
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| 66 | | __ TIMER 0 |
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| 67 | |
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| 68 | .equ TIM_MCR0, 0x600 | Module configuration register |
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| 69 | .equ TIM_IR0, 0x604 | interrupt register |
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| 70 | .equ TIM_CR0, 0x606 | controle register |
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| 71 | .equ TIM_SR0, 0x608 | Status/prescaler register |
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| 72 | .equ TIM_CNTR0, 0x60A | counter register |
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| 73 | .equ TIM_PREL10, 0x60C | Preload register 1 |
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| 74 | .equ TIM_PREL20, 0x60E | Preload register 2 |
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| 75 | .equ TIM_COM0, 0x610 | Compare register |
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| 76 | |
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| 77 | | __ TIMER 1 |
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| 78 | |
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| 79 | .equ TIM_MCR1, 0x640 | Module configuration register |
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| 80 | .equ TIM_IR1, 0x644 | interrupt register |
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| 81 | .equ TIM_CR1, 0x646 | controle register |
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| 82 | .equ TIM_SR1, 0x648 | Status/prescaler register |
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| 83 | .equ TIM_CNTR1, 0x64A | counter register |
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| 84 | .equ TIM_PREL11, 0x64C | Preload register 1 |
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| 85 | .equ TIM_PREL21, 0x64E | Preload register 2 |
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| 86 | .equ TIM_COM1, 0x650 | Compare register |
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| 87 | |
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| 88 | | -- U.A.R.T. equates -- |
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| 89 | |
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| 90 | .equ UA_MCRH, 0x700 | module configuration register |
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| 91 | .equ UA_MCRL, 0x701 | module configuration register |
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| 92 | .equ UA_ILR, 0x704 | Interrupt level |
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| 93 | .equ UA_IVR, 0x705 | Interrupt vector |
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| 94 | |
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| 95 | .equ UA_MR1A, 0x710 | Mode register 1 A |
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| 96 | .equ UA_MR2A, 0x720 | Mode register 2 A |
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| 97 | .equ UA_CSRA, 0x711 | Clock_select regiter A |
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| 98 | .equ UA_SRA, 0x711 | status register A |
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| 99 | .equ UA_CRA, 0x712 | command register A |
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| 100 | .equ UA_RBA, 0x713 | receive buffer A |
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| 101 | .equ UA_TBA, 0x713 | transmit buffer A |
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| 102 | |
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| 103 | .equ UA_IPCR, 0x714 | input port change register |
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| 104 | .equ UA_ACR, 0x714 | auxiliary control register |
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| 105 | .equ UA_ISR, 0x715 | interrupt status register |
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| 106 | .equ UA_IER, 0x715 | interrupt enable register |
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| 107 | |
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| 108 | .equ UA_MR1B, 0x718 | Mode register 1 B |
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| 109 | .equ UA_MR2B, 0x721 | Mode register 2 B |
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| 110 | .equ UA_CSRB, 0x719 | Clock_select regiter B |
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| 111 | .equ UA_SRB, 0x719 | status register B |
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| 112 | .equ UA_CRB, 0x71A | command register A |
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| 113 | .equ UA_RBB, 0x71B | receive buffer A |
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| 114 | .equ UA_TBB, 0x71B | transmit buffer A |
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| 115 | |
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| 116 | .equ UA_IP, 0x71D | Input port register |
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| 117 | .equ UA_OPCR, 0x71D | output port control register |
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| 118 | .equ UA_OPS, 0x71E | output port bit set |
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| 119 | .equ UA_OPR, 0x71F | output port bit reset |
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| 120 | .equ TX_A_EN, 0x01 | Tx A irq enable |
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| 121 | .equ TX_B_EN, 0x10 | Tx B irq enable |
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| 122 | .equ TX_A_DIS, 0xFE | Tx A irq enable |
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| 123 | .equ TX_B_DIS, 0xEF | Tx B irq enable |
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| 124 | .equ TX_AB_DIS, 0x22 |
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| 125 | |
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| 126 | |
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| 127 | | -- DMA equates |
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| 128 | .equ DMA_MCR0, 0x780 | module configuration register |
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| 129 | .equ DMA_IR0, 0x784 | Interrupt register |
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| 130 | .equ DMA_CCR0, 0x788 | Channel control register |
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| 131 | .equ DMA_CSR0, 0x78A | Channel status register |
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| 132 | .equ DMA_FCR0, 0x78B | Function code register |
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| 133 | .equ DMA_SARH0, 0x78C | Source adresse register |
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| 134 | .equ DMA_SARL0, 0x78E | Source adresse register |
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| 135 | .equ DMA_DARH0, 0x790 | destination adresse register |
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| 136 | .equ DMA_DARL0, 0x792 | destination adresse register |
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| 137 | .equ DMA_BTCH0, 0x794 | byte transfer register |
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| 138 | .equ DMA_BTCL0, 0x796 | byte transfer register |
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| 139 | |
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| 140 | .equ DMA_MCR1, 0x7A0 | module configuration register |
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| 141 | .equ DMA_IR1, 0x7A4 | Interrupt register |
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| 142 | .equ DMA_CCR1, 0x7A8 | Channel control register |
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| 143 | .equ DMA_CSR1, 0x7AA | Channel status register |
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| 144 | .equ DMA_FCR1, 0x7AB | Function code register |
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| 145 | .equ DMA_SARH1, 0x7AC | Source adresse register |
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| 146 | .equ DMA_SARL1, 0x7AE | Source adresse register |
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| 147 | .equ DMA_DARH1, 0x7B0 | destination adresse register |
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| 148 | .equ DMA_DARL1, 0x7B2 | destination adresse register |
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| 149 | .equ DMA_BTCH1, 0x7B4 | byte transfer register |
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| 150 | .equ DMA_BTCL1, 0x7B6 | byte transfer register |
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| 151 | |
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| 152 | | -- cache equates |
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| 153 | .equ CACHE_MCR, 0xFC0 | cache config reg. (long) |
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| 154 | |
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| 155 | | -- quad data memory module (QDMM) equates |
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| 156 | .equ QDMM_MCR, 0xC00 | QDMM config reg (long) |
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| 157 | .equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long) |
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| 158 | .equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long) |
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| 159 | .equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long) |
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| 160 | .equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long) |
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| 161 | |
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| 162 | |
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| 163 | |
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| 164 | |----------------------------------------------------- |
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| 165 | | AST68349 internal registers |
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| 166 | |----------------------------------------------------- |
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| 167 | .equ EPLD_SPACE, 3 | "reserved user" space |
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| 168 | .equ CPU_SPACE, 7 | "CPU" space |
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| 169 | |
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| 170 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |
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| 171 | | GLUE EPLD |
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| 172 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |
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| 173 | |
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| 174 | .equ GLUE_EPLD, 0xB0000000 |
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| 175 | |
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| 176 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 177 | | configuration of /CS0 : |
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| 178 | | |
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| 179 | | 7 6 5 4 3 2 1 0 |
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| 180 | | +---+---+---+---+---+---+---+---+ |
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| 181 | | |ena|val|wid| ws|b31|b30|b29|b28| |
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| 182 | | +---+---+---+---+---+---+---+---+ |
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| 183 | | |
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| 184 | | b[31..28] : base address for decoding /CS[3..0] |
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| 185 | | the decoding is as follow : |
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| 186 | | |
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| 187 | | +----------+------------+------+ |
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| 188 | | | a[31..28] | a[27..26] | /CS | |
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| 189 | | +-----------+-----------+------+ |
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| 190 | | | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes |
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| 191 | | | b[31..28] | 01 | /CS1 | |
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| 192 | | | b[31..28] | 10 | /CS2 | |
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| 193 | | | b[31..28] | 11 | /CS3 | |
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| 194 | | +-----------------------+------+ |
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| 195 | | |
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| 196 | | after /RESET, /CS0 is validated for every cycle, until programmed |
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| 197 | | |
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| 198 | | ws : number of wait-states : 0 => 0 ws |
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| 199 | | 1 => external /dsackx |
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| 200 | | wid : width of chip-select : 0 => 16 bits |
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| 201 | | 1 => 32 bits |
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| 202 | | ena : enable chip-select : 0 => disabled |
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| 203 | | 1 => enabled |
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| 204 | | |
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| 205 | | val : automatic validation. set after reset |
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| 206 | | cleared when /CS0 is configured |
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| 207 | | |
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| 208 | .equ REG_CS0, 0 |
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| 209 | |
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| 210 | |
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| 211 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 212 | | configuration of /CS1 to /CS3: |
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| 213 | | |
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| 214 | | 7 6 5 4 3 2 1 0 |
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| 215 | | +---+---+---+---+---+---+---+---+ |
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| 216 | | |ena| x |wid| ws| x | x | x | x | |
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| 217 | | +---+---+---+---+---+---+---+---+ |
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| 218 | | |
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| 219 | | ws : number of wait-states : 0 => 0 ws |
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| 220 | | 1 => external /dsackx |
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| 221 | | wid : width of chip-select : 0 => 16 bits |
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| 222 | | 1 => 32 bits |
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| 223 | | ena : enable chip-select : 0 => disabled |
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| 224 | | 1 => enabled |
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| 225 | .equ REG_CS1, 1 |
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| 226 | .equ REG_CS2, 2 |
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| 227 | .equ REG_CS3, 3 |
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| 228 | |
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| 229 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 230 | | I2C register |
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| 231 | | |
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| 232 | | 7 6 5 4 3 2 1 0 |
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| 233 | | +---+---+---+---+---+---+---+----+ |
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| 234 | | | x | x | x | x | x | x |clk|data| |
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| 235 | | +---+---+---+---+---+---+---+----+ |
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| 236 | | bidirecionnal pin, open drain output. |
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| 237 | | set bit to 1 to read external state of pin |
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| 238 | | |
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| 239 | .equ REG_I2C, 4 |
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| 240 | |
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| 241 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 242 | | PDCS register |
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| 243 | | |
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| 244 | | 7 6 5 4 3 2 1 0 |
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| 245 | | +---+---+---+---+---+---+---+---+ |
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| 246 | | |s12|s11|s14|pd5|pd4|pd3|pd2|pd1| |
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| 247 | | +---+---+---+---+---+---+---+---+ |
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| 248 | | pd[5..1] : value read on the DRAM module |
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| 249 | | S12, S11 and S14 : "user reserved" configuration switch |
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| 250 | | |
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| 251 | .equ REG_PDCS, 5 |
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| 252 | |
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| 253 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 254 | | timer1 register |
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| 255 | | |
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| 256 | | 7 6 5 4 3 2 1 0 |
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| 257 | | +---+---+---+---+---+---+---+---+ |
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| 258 | | |ena| x | x | x | x | x | d1| d0| |
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| 259 | | +---+---+---+---+---+---+---+---+ |
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| 260 | | |
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| 261 | | the timer clock is the 1000Hz clock of the ASTECC platform |
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| 262 | | the timer is reloaded on each write to the register, or if the input |
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| 263 | | TIN1 is set to 0. |
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| 264 | | on overflow, the open drain output TOUT1 is set to 0 |
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| 265 | | the timer must be disabled to return TOUT1 to the inactive state |
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| 266 | | |
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| 267 | .equ REG_TIMER1, 6 |
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| 268 | |
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| 269 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 270 | | timer2 register |
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| 271 | | |
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| 272 | | 7 6 5 4 3 2 1 0 |
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| 273 | | +---+---+---+---+---+---+---+---+ |
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| 274 | | |ena| x | x | x | x | x | d1| d0| |
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| 275 | | +---+---+---+---+---+---+---+---+ |
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| 276 | | the timer clock is the 1000Hz clock of the ASTECC platform |
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| 277 | | the timer is reloaded on each write to the register, or if the input |
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| 278 | | TIN2 is set to 0. |
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| 279 | | on overflow, the open drain output TOUT2 is set to 0 |
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| 280 | | the timer must be disabled to return TOUT2 to the inactive state |
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| 281 | | |
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| 282 | .equ REG_TIMER2, 7 |
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| 283 | |
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| 284 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 285 | | baudrate generator register |
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| 286 | | |
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| 287 | | 7 6 5 4 3 2 1 0 |
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| 288 | | +---+---+---+---+---+---+---+---+ |
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| 289 | | | x | x | x | x | x | d2| d1| d0| |
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| 290 | | +---+---+---+---+---+---+---+---+ |
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| 291 | | |
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| 292 | | d[2..0] : divider of a 3.6864 Mhz clock |
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| 293 | | |
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| 294 | | d[2..0] : 0 1 2 3 4 5 6 7 |
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| 295 | | divides by : 2 4 6 8 10 12 14 16 |
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| 296 | | SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304 |
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| 297 | | baudrate : 115200 57600 38400 28800 x 19200 x 14400 |
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| 298 | | |
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| 299 | .equ REG_BAUDRATE, 8 |
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| 300 | |
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| 301 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 302 | | IO register |
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| 303 | | |
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| 304 | | 7 6 5 4 3 2 1 0 |
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| 305 | | +---+---+---+---+---+---+---+---+ |
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| 306 | | | x | x | x |io4|io3|io2|io1|io0| |
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| 307 | | +---+---+---+---+---+---+---+---+ |
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| 308 | | |
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| 309 | | io[4..0] : data written to port |
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| 310 | | |
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| 311 | | maximum current load is about 5 mA per pin |
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| 312 | | |
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| 313 | .equ REG_IO, 9 |
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| 314 | |
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| 315 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 316 | | IO port |
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| 317 | | |
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| 318 | | 7 6 5 4 3 2 1 0 |
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| 319 | | +---+---+---+---+---+---+---+---+ |
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| 320 | | | x | x | x |io4|io3|io2|io1|io0| |
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| 321 | | +---+---+---+---+---+---+---+---+ |
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| 322 | | |
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| 323 | | io[4..0] : data read from port |
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| 324 | | |
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| 325 | .equ REG_IO_PORT, 10 |
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| 326 | |
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| 327 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 328 | | IO direction register |
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| 329 | | |
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| 330 | | 7 6 5 4 3 2 1 0 |
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| 331 | | +---+---+---+---+---+---+---+---+ |
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| 332 | | | x | x | x | x | x |dr2|dr1|dr0| |
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| 333 | | +---+---+---+---+---+---+---+---+ |
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| 334 | | |
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| 335 | | dr0 : 0 => io port 0 is configured as input (default after /RESET) |
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| 336 | | 1 => io port 0 is configured as output |
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| 337 | | |
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| 338 | | dr1 : 0 => io port 1 is configured as input (default after /RESET) |
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| 339 | | 1 => io port 1 is configured as output |
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| 340 | | |
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| 341 | | dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET) |
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| 342 | | 1 => io ports 2 to 4 are configured as output |
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| 343 | | |
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| 344 | .equ REG_DIR_IO, 11 |
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| 345 | |
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| 346 | |
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| 347 | |
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| 348 | |
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| 349 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |
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| 350 | | DRAM EPLD |
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| 351 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |
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| 352 | |
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| 353 | .equ DRAM_EPLD, 0xA0000000 |
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| 354 | |
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| 355 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 356 | | number of wait-state for DRAM |
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| 357 | | |
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| 358 | | 7 6 5 4 3 2 1 0 |
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| 359 | | +---+---+---+---+---+---+---+---+ |
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| 360 | | | x | x | x | x | x | x |ws1|ws0| |
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| 361 | | +---+---+---+---+---+---+---+---+ |
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| 362 | | |
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| 363 | | ws[1..0] : 0 1 2 3 |
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| 364 | | wait states : 0 1 2 3 |
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| 365 | | |
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| 366 | .equ REG_WS, 0 |
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| 367 | |
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| 368 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 369 | | configuration of refresh for DRAM |
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| 370 | | |
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| 371 | | 7 6 5 4 3 2 1 0 |
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| 372 | | +---+---+---+---+---+---+---+---+ |
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| 373 | | |ena| x | x | x | x | x |rf1|rf0| |
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| 374 | | +---+---+---+---+---+---+---+---+ |
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| 375 | | |
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| 376 | | rf[1..0] : 0 1 2 3 |
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| 377 | | refresh : 5µs 10µs 15µs 20µs |
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| 378 | | |
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| 379 | | ena == 0 : refresh disabled |
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| 380 | | ena == 1 : refresh enabled |
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| 381 | | |
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| 382 | .equ REG_REFRESH, 1 |
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| 383 | |
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| 384 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 385 | | configuration of DRAM module size |
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| 386 | | |
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| 387 | | 7 6 5 4 3 2 1 0 |
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| 388 | | +---+---+---+---+---+---+---+---+ |
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| 389 | | | x | x | x | x | x |sz2|sz1|sz0| |
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| 390 | | +---+---+---+---+---+---+---+---+ |
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| 391 | | |
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| 392 | | sz[2..0] : 0 1 2 3 4 5 6 7 |
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| 393 | | size (Mbytes): 4 8 16 32 64 128 0 0 |
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| 394 | | |
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| 395 | .equ REG_CONFIG, 2 |
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| 396 | |
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| 397 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 398 | | bus width of /CS0 during reset bw[1..0] : 0 1 2 3 |
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| 399 | | bus width : 32 16 8 ext. /dsackx |
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| 400 | | |
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| 401 | | state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) |
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| 402 | | : sel == 1 => EPLD chip_selects (/CS[3..0]) |
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| 403 | | |
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| 404 | | 7 6 5 4 3 2 1 0 |
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| 405 | | +---+---+---+---+---+---+---+---+ |
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| 406 | | |bw1|bw0| x | x | x | x | x |sel| |
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| 407 | | +---+---+---+---+---+---+---+---+ |
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| 408 | | |
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| 409 | .equ REG_BUSWIDTH, 3 |
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| 410 | |
|---|
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