1 | /* |
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2 | * Header file for console driver |
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3 | * defines for accessing M68340/68349 UART registers |
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4 | * |
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5 | * Author: |
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6 | * Geoffroy Montel |
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7 | * France Telecom - CNET/DSM/TAM/CAT |
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8 | * 4, rue du Clos Courtel |
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9 | * 35512 CESSON-SEVIGNE |
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10 | * FRANCE |
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11 | * |
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12 | * e-mail: g_montel@yahoo.com |
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13 | * |
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14 | * |
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15 | * COPYRIGHT (c) 1989-2008. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef __m340uart_H__ |
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24 | #define __m340uart_H__ |
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25 | |
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26 | /* UART initialisation */ |
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27 | #define UART_CHANNEL_A 0 |
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28 | #define UART_CHANNEL_B 1 |
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29 | #define UART_NUMBER_OF_CHANNELS 2 |
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30 | #define UART_CONSOLE_NAME "/dev/console" |
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31 | #define UART_RAW_IO_NAME "/dev/tty1" |
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32 | #define UART_FIFO_FULL 0 |
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33 | #define UART_CRR 1 |
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34 | #define UART_INTERRUPTS 0 |
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35 | #define UART_POLLING 1 |
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36 | #define UART_TERMIOS_CONSOLE 0 |
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37 | #define UART_TERMIOS_RAW 1 |
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38 | #define UART_TERMIOS_MIN_DEFAULT 1 |
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39 | #define UART_TERMIOS_TIME_DEFAULT 0 |
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40 | |
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41 | void Init_UART_Table(void); |
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42 | |
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43 | typedef struct { |
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44 | uint8_t enable; |
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45 | uint16_t rx_buffer_size; /* NOT IMPLEMENTED */ |
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46 | uint16_t tx_buffer_size; /* NOT IMPLEMENTED */ |
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47 | } uart_termios_config; |
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48 | |
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49 | typedef struct { /* for one channel */ |
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50 | uint8_t enable; /* use this channel */ |
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51 | char name[64]; /* use UART_CONSOLE_NAME for console purpose */ |
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52 | uint8_t parity_mode; /* parity mode, see MR1 section for defines */ |
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53 | uint8_t bits_per_char; /* bits per character, see MR1 section for defines */ |
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54 | float rx_baudrate; /* Rx baudrate */ |
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55 | float tx_baudrate; /* Tx baudrate */ |
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56 | uint8_t rx_mode; /* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */ |
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57 | uint8_t mode; /* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */ |
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58 | uart_termios_config termios; |
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59 | } uart_channel_config; |
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60 | |
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61 | extern uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS]; |
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62 | |
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63 | typedef struct { |
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64 | int set; /* number of the m340 baud speed set */ |
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65 | int rcs; /* RCS for the needed baud set */ |
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66 | int tcs; /* TCS for the needed baud set */ |
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67 | } t_baud_speed; |
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68 | |
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69 | typedef struct { |
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70 | t_baud_speed baud_speed_table[2]; |
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71 | short nb; |
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72 | } t_baud_speed_table; |
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73 | |
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74 | extern t_baud_speed_table |
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75 | Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, uint8_t enableA, |
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76 | float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, uint8_t enableB); |
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77 | |
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78 | extern rtems_isr InterruptHandler (rtems_vector_number v); |
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79 | |
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80 | extern int dbugRead (int minor); |
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81 | extern ssize_t dbugWrite (int minor, const char *buf, size_t len); |
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82 | |
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83 | extern float m340_Baud_Rates_Table[16][2]; |
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84 | |
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85 | /* SR */ |
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86 | #define m340_Rx_RDY 1 |
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87 | #define m340_FFULL (1<<1) |
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88 | #define m340_Tx_RDY (1<<2) |
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89 | #define m340_TxEMP (1<<3) |
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90 | #define m340_OE (1<<4) |
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91 | #define m340_PE (1<<5) |
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92 | #define m340_FE (1<<6) |
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93 | #define m340_RB (1<<7) |
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94 | |
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95 | /* IER */ |
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96 | #define m340_TxRDYA 1 |
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97 | #define m340_RxRDYA (1<<1) |
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98 | #define m340_TxRxRDYA 0x3 |
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99 | #define m340_TxRDYB (1<<4) |
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100 | #define m340_RxRDYB (1<<5) |
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101 | #define m340_TxRxRDYB 0x30 |
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102 | |
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103 | /* CR */ |
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104 | #define m340_Reset_Error_Status 0x40 |
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105 | #define m340_Reset_Receiver 0x20 |
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106 | #define m340_Reset_Transmitter 0x30 |
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107 | #define m340_Transmitter_Enable (1<<2) |
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108 | #define m340_Receiver_Enable 1 |
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109 | #define m340_Transmitter_Disable (2<<2) |
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110 | #define m340_Receiver_Disable 2 |
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111 | |
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112 | /* ACR */ |
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113 | #define m340_BRG_Set1 0 |
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114 | #define m340_BRG_Set2 (1<<7) |
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115 | |
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116 | /* OPCR */ |
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117 | #define m340_OPCR_Gal 0x0 |
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118 | #define m340_OPCR_Aux 0xFF |
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119 | |
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120 | /* ISR */ |
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121 | #define m340_COS (1<<7) |
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122 | #define m340_DBB (1<<6) |
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123 | #define m340_XTAL_RDY (1<<3) |
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124 | #define m340_DBA (1<<2) |
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125 | |
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126 | /* MR1 */ |
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127 | #define m340_RxRTS (1<<7) |
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128 | #define m340_R_F (1<<6) /* character or block mode */ |
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129 | #define m340_ERR (1<<5) |
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130 | #define m340_RxRTX (1<<7) |
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131 | #define m340_Even_Parity 0 |
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132 | #define m340_Odd_Parity (1<<2) |
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133 | #define m340_Low_Parity (2<<2) |
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134 | #define m340_High_Parity (3<<2) |
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135 | #define m340_No_Parity (4<<2) |
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136 | #define m340_Data_Character (6<<2) |
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137 | #define m340_Address_Character (7<<2) |
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138 | #define m340_5bpc 0x0 |
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139 | #define m340_6bpc 0x1 |
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140 | #define m340_7bpc 0x2 |
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141 | #define m340_8bpc 0x3 |
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142 | |
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143 | /* MR2 */ |
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144 | #define m340_normal (0<<6) |
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145 | #define m340_automatic_echo (1<<6) |
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146 | #define m340_local_loopback (2<<6) |
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147 | #define m340_remote_loopback (3<<6) |
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148 | #define m340_TxRTS (1<<5) |
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149 | #define m340_TxCTS (1<<4) |
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150 | |
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151 | /* Baud rates for Transmitter/Receiver */ |
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152 | #define SCLK 1 /* put your own SCLK value here */ |
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153 | |
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154 | #endif |
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