[56ac38e] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup m68k_gen68340 |
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| 5 | * |
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| 6 | * @brief Time driver definitions. |
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| 7 | */ |
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| 8 | |
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[132f194] | 9 | /* |
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| 10 | * Header file for timer driver |
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| 11 | * defines for accessing M68340 timer registers |
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| 12 | * |
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| 13 | * Author: |
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| 14 | * Geoffroy Montel |
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| 15 | * France Telecom - CNET/DSM/TAM/CAT |
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| 16 | * 4, rue du Clos Courtel |
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| 17 | * 35512 CESSON-SEVIGNE |
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| 18 | * FRANCE |
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[6128a4a] | 19 | * |
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| 20 | * e-mail: g_montel@yahoo.com |
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[132f194] | 21 | * |
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[08311cc3] | 22 | * COPYRIGHT (c) 1989-1999. |
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[132f194] | 23 | * On-Line Applications Research Corporation (OAR). |
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| 24 | * |
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| 25 | * The license and distribution terms for this file may be |
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| 26 | * found in the file LICENSE in this distribution or at |
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[c499856] | 27 | * http://www.rtems.org/license/LICENSE. |
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[132f194] | 28 | */ |
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| 29 | |
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| 30 | #ifndef __m340timer_H__ |
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| 31 | #define __m340timer_H__ |
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| 32 | |
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[722ab6d] | 33 | extern void Fifo_Full_benchmark_timer_initialize (void); |
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[132f194] | 34 | |
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| 35 | extern void (*Restart_Fifo_Full_A_Timer)(); |
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| 36 | extern void (*Restart_Check_A_Timer)(); |
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| 37 | extern void (*Restart_Fifo_Full_B_Timer)(); |
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| 38 | extern void (*Restart_Check_B_Timer)(); |
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| 39 | |
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| 40 | /* CR */ |
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| 41 | #define m340_SWR (1<<15) |
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| 42 | #define m340_Polling_Mode (0<<12) |
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| 43 | #define m340_TC_Enabled (1<<12) |
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| 44 | #define m340_TG_Enabled (2<<12) |
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| 45 | #define m340_TG_TC_Enabled (3<<12) |
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| 46 | #define m340_TO_Enabled (4<<12) |
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| 47 | #define m340_TO_TC_Enabled (5<<12) |
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| 48 | #define m340_TG_TG_Enabled (6<<12) |
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| 49 | #define m340_TO_TG_TG_Enabled (7<<12) |
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| 50 | #define m340_TGE (1<<11) |
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| 51 | #define m340_PSE (1<<10) |
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| 52 | #define m340_CPE (1<<9) |
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| 53 | #define m340_CLK (1<<8) |
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| 54 | #define m340_Divide_by_2 (1<<5) |
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| 55 | #define m340_Divide_by_4 (2<<5) |
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| 56 | #define m340_Divide_by_8 (3<<5) |
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| 57 | #define m340_Divide_by_16 (4<<5) |
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| 58 | #define m340_Divide_by_32 (5<<5) |
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| 59 | #define m340_Divide_by_64 (6<<5) |
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| 60 | #define m340_Divide_by_128 (7<<5) |
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| 61 | #define m340_Divide_by_256 (0<<5) |
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| 62 | #define m340_ICOC (0<<2) |
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| 63 | #define m340_SWG (1<<2) |
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| 64 | #define m340_VDCSWG (2<<2) |
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| 65 | #define m340_VWSSPG (3<<2) |
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| 66 | #define m340_PWM (4<<2) |
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| 67 | #define m340_PM (5<<2) |
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| 68 | #define m340_EC (6<<2) |
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| 69 | #define m340_TB (7<<2) |
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| 70 | #define m340_Disabled 0 |
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| 71 | #define m340_Toggle_Mode 1 |
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| 72 | #define m340_Zero_Mode 2 |
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| 73 | #define m340_One_Mode 3 |
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| 74 | |
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| 75 | /* SR */ |
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| 76 | #define m340_IRQ (1<<15) |
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| 77 | #define m340_TO (1<<14) |
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| 78 | #define m340_TG (1<<13) |
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| 79 | #define m340_TC (1<<12) |
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| 80 | #define m340_TGL (1<<11) |
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| 81 | #define m340_ON (1<<10) |
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| 82 | #define m340_OUT (1<<9) |
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| 83 | #define m340_COM (1<<8) |
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| 84 | |
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| 85 | #endif |
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