1 | /* cpu_asm.s |
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2 | * |
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3 | * This file contains all assembly code for the MC68020 implementation |
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4 | * of RTEMS. |
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5 | * |
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6 | * ATTENTION: Modified for benchmarks |
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7 | * |
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8 | * COPYRIGHT (c) 1989-1999. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | |
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19 | #include <asm.h> |
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20 | |
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21 | .text |
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22 | |
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23 | /*PAGE |
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24 | * void _Debug_ISR_Handler_Console() |
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25 | * |
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26 | * This routine provides the RTEMS interrupt management. |
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27 | * |
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28 | * NOTE: |
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29 | * Upon entry, the master stack will contain an interrupt stack frame |
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30 | * back to the interrupted thread and the interrupt stack will contain |
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31 | * a throwaway interrupt stack frame. If dispatching is enabled, this |
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32 | * is the outer most interrupt, and (a context switch is necessary or |
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33 | * the current thread has signals), then set up the master stack to |
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34 | * transfer control to the interrupt dispatcher. |
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35 | * NOTE: |
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36 | * USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE |
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37 | * CS5 - CS8 are linked to an oscilloscope so that you can mesure |
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38 | * RTEMS overhead (BTW it's very short :) ) |
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39 | */ |
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40 | |
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41 | /* |
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42 | * With this approach, lower priority interrupts may |
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43 | * execute twice if a higher priority interrupt is |
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44 | * acknowledged before _Thread_Dispatch_disable is |
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45 | * increamented and the higher priority interrupt |
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46 | * preforms a context switch after executing. The lower |
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47 | * priority intterrupt will execute (1) at the end of the |
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48 | * higher priority interrupt in the new context if |
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49 | * permitted by the new interrupt level mask, and (2) when |
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50 | * the original context regains the cpu. |
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51 | */ |
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52 | |
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53 | #if ( M68K_HAS_VBR == 1) |
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54 | .set SR_OFFSET, 0 | Status register offset |
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55 | .set PC_OFFSET, 2 | Program Counter offset |
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56 | .set FVO_OFFSET, 6 | Format/vector offset |
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57 | #else |
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58 | .set SR_OFFSET, 2 | Status register offset |
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59 | .set PC_OFFSET, 4 | Program Counter offset |
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60 | .set FVO_OFFSET, 0 | Format/vector offset placed in the stack |
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61 | #endif /* M68K_HAS_VBR */ |
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62 | |
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63 | .set SAVED, 16 | space for saved registers |
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64 | |
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65 | .align 4 |
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66 | .global SYM (_Debug_ISR_Handler_Console) |
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67 | |
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68 | SYM (_Debug_ISR_Handler_Console): |
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69 | |
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70 | | |
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71 | tst.w 0x14000000 | ALLUME CS5 |
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72 | | |
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73 | |
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74 | addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking |
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75 | moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 |
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76 | movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO |
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77 | andl #0x0fff,d0 | d0 = vector offset in vbr |
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78 | |
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79 | |
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80 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) |
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81 | movew sr,d1 | Save status register |
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82 | oriw #0x700,sr | Disable interrupts |
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83 | tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler? |
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84 | bne 1f | Yes, just skip over stack switch code |
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85 | movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack |
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86 | movel a7,a0@- | Save task stack pointer |
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87 | movel a0,a7 | Switch to interrupt stack |
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88 | 1: |
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89 | addql #1,SYM(_ISR_Nest_level) | one nest level deeper |
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90 | movew d1,sr | Restore status register |
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91 | #else |
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92 | addql #1,SYM (_ISR_Nest_level) | one nest level deeper |
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93 | #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ |
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94 | |
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95 | #if ( M68K_HAS_PREINDEXING == 1 ) |
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96 | movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR |
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97 | #else |
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98 | movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table |
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99 | addal d0,a0 | a0 = address of vector |
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100 | movel (a0),a0 | a0 = address of user routine |
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101 | #endif |
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102 | |
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103 | lsrl #2,d0 | d0 = vector number |
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104 | movel d0,a7@- | push vector number |
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105 | |
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106 | | |
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107 | tst.w 0x18000000 | ALLUME CS6 |
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108 | | |
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109 | |
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110 | jbsr a0@ | invoke the user ISR |
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111 | |
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112 | | |
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113 | tst.w 0x18000000 | ALLUME CS6 |
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114 | | |
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115 | |
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116 | addql #4,a7 | remove vector number |
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117 | |
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118 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) |
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119 | movew sr,d0 | Save status register |
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120 | oriw #0x700,sr | Disable interrupts |
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121 | subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count |
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122 | bne 1f | Skip if return to interrupt |
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123 | movel (a7),a7 | Restore task stack pointer |
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124 | 1: |
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125 | movew d0,sr | Restore status register |
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126 | #else |
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127 | subql #1,SYM (_ISR_Nest_level) | one less nest level |
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128 | #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ |
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129 | |
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130 | subql #1,SYM (_Thread_Dispatch_disable_level) |
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131 | | unnest multitasking |
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132 | bne Debug_exit | If dispatch disabled, Debug_exit |
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133 | |
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134 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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135 | movew #0xf000,d0 | isolate format nibble |
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136 | andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO |
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137 | cmpiw #0x1000,d0 | is it a throwaway isf? |
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138 | bne Debug_exit | NOT outer level, so branch |
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139 | #endif |
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140 | |
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141 | tstl SYM (_Context_Switch_necessary) |
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142 | | Is thread switch necessary? |
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143 | bne bframe | Yes, invoke dispatcher |
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144 | |
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145 | tstl SYM (_ISR_Signals_to_thread_executing) |
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146 | | signals sent to Run_thread |
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147 | | while in interrupt handler? |
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148 | beq Debug_exit | No, then Debug_exit |
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149 | |
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150 | |
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151 | bframe: clrl SYM (_ISR_Signals_to_thread_executing) |
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152 | | If sent, will be processed |
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153 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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154 | movec msp,a0 | a0 = master stack pointer |
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155 | movew #0,a0@- | push format word |
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156 | movel # SYM (_ISR_Dispatch),a0@- | push return addr |
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157 | | filter out the trace bit to stop single step debugging breaking |
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158 | movew a0@(6+SR_OFFSET),d0 |
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159 | andw #0x7FFF,d0 |
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160 | movew d0,a0@- | push thread sr |
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161 | movec a0,msp | set master stack pointer |
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162 | #else |
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163 | |
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164 | | filter out the trace bit to stop single step debugging breaking |
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165 | movew a7@(16+SR_OFFSET),d0 |
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166 | andw #0x7FFF,d0 |
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167 | movew d0,sr |
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168 | jsr SYM (_Thread_Dispatch) |
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169 | #endif |
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170 | |
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171 | Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 |
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172 | #if ( M68K_HAS_VBR == 0 ) |
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173 | addql #2,a7 | pop format/id |
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174 | #endif /* M68K_HAS_VBR */ |
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175 | |
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176 | | |
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177 | tst.w 0x1C000000 | ALLUME CS7 |
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178 | | |
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179 | |
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180 | rte | return to thread |
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181 | | OR _Isr_dispatch |
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182 | |
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183 | |
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