source: rtems/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S @ 08b5f55

4.104.114.84.95
Last change on this file since 08b5f55 was 0162910, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 14, 1998 at 11:15:38 PM

Patch from Ralf Corsepius <corsepiu@…> to rename all
.s files to .S in conformance with GNU conventions. This is a
minor step along the way to supporting automake.

  • Property mode set to 100644
File size: 6.4 KB
Line 
1/*  cpu_asm.s
2 *
3 *  This file contains all assembly code for the MC68020 implementation
4 *  of RTEMS.
5 *
6 *  ATTENTION: Modified for benchmarks
7 *
8 *  COPYRIGHT (c) 1989-1998.
9 *  On-Line Applications Research Corporation (OAR).
10 *  Copyright assigned to U.S. Government, 1994.
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.OARcorp.com/rtems/license.html.
15 *
16 *  $Id$
17 */
18
19
20#include <asm.h>
21
22        .text
23
24/*PAGE
25 *  void _Debug_ISR_Handler_Console()
26 *
27 *  This routine provides the RTEMS interrupt management.
28 *
29 *  NOTE:
30 *    Upon entry, the master stack will contain an interrupt stack frame
31 *    back to the interrupted thread and the interrupt stack will contain
32 *    a throwaway interrupt stack frame.  If dispatching is enabled, this
33 *    is the outer most interrupt, and (a context switch is necessary or
34 *    the current thread has signals), then set up the master stack to
35 *    transfer control to the interrupt dispatcher.
36 *  NOTE:
37 *    USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE
38 *    CS5 - CS8 are linked to an oscilloscope so that you can mesure
39 *    RTEMS overhead (BTW it's very short :) )
40 */
41
42/*
43 *  With this approach, lower priority interrupts may
44 *  execute twice if a higher priority interrupt is
45 *  acknowledged before _Thread_Dispatch_disable is
46 *  increamented and the higher priority interrupt
47 *  preforms a context switch after executing. The lower
48 *  priority intterrupt will execute (1) at the end of the
49 *  higher priority interrupt in the new context if
50 *  permitted by the new interrupt level mask, and (2) when
51 *  the original context regains the cpu.
52 */
53 
54#if ( M68K_HAS_VBR == 1)
55.set SR_OFFSET,    0                     | Status register offset
56.set PC_OFFSET,    2                     | Program Counter offset
57.set FVO_OFFSET,   6                     | Format/vector offset
58#else
59.set SR_OFFSET,    2                     | Status register offset
60.set PC_OFFSET,    4                     | Program Counter offset
61.set FVO_OFFSET,   0                     | Format/vector offset placed in the stack
62#endif /* M68K_HAS_VBR */
63 
64.set SAVED,        16                    | space for saved registers
65
66        .align  4
67        .global SYM (_Debug_ISR_Handler_Console)
68
69SYM (_Debug_ISR_Handler_Console):
70
71                                         |
72        tst.w   0x14000000               | ALLUME CS5
73                                         |
74
75        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
76        moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
77        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
78        andl    #0x0fff,d0               | d0 = vector offset in vbr
79
80
81#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
82        movew   sr,d1                   | Save status register
83        oriw    #0x700,sr               | Disable interrupts
84        tstl    SYM (_ISR_Nest_level)   | Interrupting an interrupt handler?
85        bne     1f                      | Yes, just skip over stack switch code
86        movel   SYM(_CPU_Interrupt_stack_high),a0       | End of interrupt stack
87        movel   a7,a0@-                 | Save task stack pointer
88        movel   a0,a7                   | Switch to interrupt stack
891:
90        addql   #1,SYM(_ISR_Nest_level) | one nest level deeper
91        movew   d1,sr                   | Restore status register
92#else
93        addql   #1,SYM (_ISR_Nest_level) | one nest level deeper
94#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
95
96#if ( M68K_HAS_PREINDEXING == 1 )
97        movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
98#else
99        movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
100        addal   d0,a0                    | a0 = address of vector
101        movel   (a0),a0                  | a0 = address of user routine
102#endif
103
104        lsrl    #2,d0                    | d0 = vector number
105        movel   d0,a7@-                  | push vector number
106
107                                         |
108        tst.w   0x18000000               | ALLUME CS6
109                                         |
110
111        jbsr    a0@                      | invoke the user ISR
112
113                                         |
114        tst.w   0x18000000               | ALLUME CS6
115                                         |
116
117        addql   #4,a7                    | remove vector number
118
119#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
120        movew   sr,d0                   | Save status register
121        oriw    #0x700,sr               | Disable interrupts
122        subql   #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count
123        bne     1f                      | Skip if return to interrupt
124        movel   (a7),a7                 | Restore task stack pointer
1251:
126        movew   d0,sr                   | Restore status register
127#else
128        subql   #1,SYM (_ISR_Nest_level) | one less nest level
129#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
130
131        subql   #1,SYM (_Thread_Dispatch_disable_level)
132                                         | unnest multitasking
133        bne     Debug_exit                     | If dispatch disabled, Debug_exit
134
135#if ( M68K_HAS_SEPARATE_STACKS == 1 )
136        movew   #0xf000,d0               | isolate format nibble
137        andw    a7@(SAVED+FVO_OFFSET),d0 | get F/VO
138        cmpiw   #0x1000,d0               | is it a throwaway isf?
139        bne     Debug_exit                     | NOT outer level, so branch
140#endif
141
142        tstl    SYM (_Context_Switch_necessary)
143                                         | Is thread switch necessary?
144        bne     bframe                   | Yes, invoke dispatcher
145
146        tstl    SYM (_ISR_Signals_to_thread_executing)
147                                         | signals sent to Run_thread
148                                         |   while in interrupt handler?
149        beq     Debug_exit               | No, then Debug_exit
150
151
152bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
153                                         | If sent, will be processed
154#if ( M68K_HAS_SEPARATE_STACKS == 1 )
155        movec   msp,a0                   | a0 = master stack pointer
156        movew   #0,a0@-                  | push format word
157        movel   # SYM (_ISR_Dispatch),a0@- | push return addr
158        | filter out the trace bit to stop single step debugging breaking
159        movew   a0@(6+SR_OFFSET),d0
160        andw    #0x7FFF,d0
161        movew   d0,a0@-                  | push thread sr
162        movec   a0,msp                   | set master stack pointer
163#else
164
165        | filter out the trace bit to stop single step debugging breaking
166        movew   a7@(16+SR_OFFSET),d0
167        andw    #0x7FFF,d0
168        movew   d0,sr
169        jsr SYM (_Thread_Dispatch)
170#endif
171
172Debug_exit:   moveml  a7@+,d0-d1/a0-a1         | restore d0-d1,a0-a1
173#if ( M68K_HAS_VBR == 0 )
174        addql   #2,a7                    | pop format/id
175#endif /* M68K_HAS_VBR */
176
177                                         |
178        tst.w   0x1C000000               | ALLUME CS7
179                                         |
180
181        rte                              | return to thread
182                                         |   OR _Isr_dispatch
183
184
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