source: rtems/c/src/lib/libbsp/m68k/gen68302/start/start302.s @ 3a4ae6c

4.104.114.84.95
Last change on this file since 3a4ae6c was 3a4ae6c, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 11, 1995 at 7:35:39 PM

The word "RTEMS" almost completely removed from the core.

Configuration Table Template file added and all tests
modified to use this. All gvar.h and conftbl.h files
removed from test directories.

Configuration parameter maximum_devices added.

Core semaphore and mutex handlers added and RTEMS API Semaphore
Manager updated to reflect this.

Initialization sequence changed to invoke API specific initialization
routines. Initialization tasks table now owned by RTEMS Tasks Manager.

Added user extension for post-switch.

Utilized user extensions to implement API specific functionality
like signal dispatching.

Added extensions to the System Initialization Thread so that an
API can register a function to be invoked while the system
is being initialized. These are largely equivalent to the
pre-driver and post-driver hooks.

Added the Modules file oar-go32_p5, modified oar-go32, and modified
the file make/custom/go32.cfg to look at an environment varable which
determines what CPU model is being used.

All BSPs updated to reflect named devices and clock driver's IOCTL
used by the Shared Memory Driver. Also merged clock isr into
main file and removed ckisr.c where possible.

Updated spsize to reflect new and moved variables.

Makefiles for the executive source and include files updated to show
break down of files into Core, RTEMS API, and Neither.

Header and inline files installed into subdirectory based on whether
logically in the Core or a part of the RTEMS API.

  • Property mode set to 100644
File size: 8.0 KB
Line 
1/*  entry.s
2 *
3 *  This file contains the entry point for the application.
4 *  The name of this entry point is compiler dependent.
5 *  It jumps to the BSP which is responsible for performing
6 *  all initialization.
7 *
8 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
9 *  On-Line Applications Research Corporation (OAR).
10 *  All rights assigned to U.S. Government, 1994.
11 *
12 *  This material may be reproduced by or for the U.S. Government pursuant
13 *  to the copyright license under the clause at DFARS 252.227-7013.  This
14 *  notice must appear in all copies of this file and its derivatives.
15 *
16 *  $Id$
17 */
18
19#include "asm.h"
20
21  .set  BAR,            0xF2            | Base Address Register location
22  .set  SCR,            0xF4            | System Control Register location
23  .set  BAR_VAL,        0x0f7f          | BAR value
24  .set  SCR_VAL,        0x00080f00      | SCR value
25  .set  GIMR_VAL,       0x8780          |Global Interrupt Mode Register. (MUST BE WRITTEN).
26  .set  BaseAddr,(BAR_VAL&0x0fff)<<12   | MC68302 internal base address
27
28  .set  oSYSRAM,        0x000           | 576 bytes of internal system RAM
29
30  .set  oGIMR,          0x812
31
32  .set  oCS0_Base,      0x830           | 16 bits, Chip Sel 0 Base Reg
33  .set  oCS0_Option,    0x832           | 16 bits, Chip Sel 0 Option Reg
34  .set  oCS1_Base,      0x834           | 16 bits, Chip Sel 1 Base Reg
35  .set  oCS1_Option,    0x836           | 16 bits, Chip Sel 1 Option Reg
36  .set  oCS2_Base,      0x838           | 16 bits, Chip Sel 2 Base Reg
37  .set  oCS2_Option,    0x83a           | 16 bits, Chip Sel 2 Option Reg
38  .set  oCS3_Base,      0x83c           | 16 bits, Chip Sel 3 Base Reg
39  .set  oCS3_Option,    0x83e           | 16 bits, Chip Sel 3 Option Reg
40
41  .set  tmpSRAM_BASE,   0x400000        | start of temporary SRAM
42  .set  FLASH_BASE,     0xc00000        | start of FLASH''s normal location
43
44
45BEGIN_CODE
46         PUBLIC (M68Kvec)               | Vector Table
47SYM (M68Kvec):                          | standard location for vectors
48V___ISSP: .long 0x00001000              |00  0 Reset: Initial SSP
49V____IPC: .long SYM(start)-V___ISSP     |04  1 Reset: Initial PC
50V_BUSERR: .long Bad-V___ISSP            |08  2 Bus Error
51V_ADRERR: .long Bad-V___ISSP            |0c  3 Address Error
52        .space  240                     | reserve space for reset of vectors
53
54#if ( M68K_HAS_SEPARATE_STACKS == 1 )
55SYM (lowintstack):
56        .space   4092                   | reserve for interrupt stack
57SYM (hiintstack):
58        .space   4                      | end of interrupt stack
59#endif
60
61        PUBLIC (start)                 | Default entry point for GNU
62SYM (start):
63        move.w  #0x2700,sr              | Disable all interrupts
64        move.w  #BAR_VAL,BAR            | Set Base Address Register
65        move.l  #SCR_VAL,SCR            | Set System Control Register
66        lea     BaseAddr,a5
67        move.w  #GIMR_VAL,a5@(oGIMR)    | Set Global Interrupt Mode Register
68
69|
70| Set up chip select registers for the remapping process.
71|
72
73|
74|      0      X      x    x    x    x
75| 0  000 0  0-- -  --- ---- ---- ----
76| x  xxx x  xxx x  xx
77|
78        move.w  #0xc001,a5@(oCS0_Base)   | Expand CS0 to full size (FLASH)
79        move.w  #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS
80
81|
82|      X      x      x    x    x    x
83| 0  100 0  0-- -  --- ---- ---- ----
84| x  xxx x  xxx x  xx
85|
86        move.w  #0xa801,a5@(oCS1_Base)   | Set up and enable CS1 (SRAM)
87        move.w  #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS
88
89|
90| Copy the initial boot FLASH area to the temporary SRAM location.
91|
92                moveq   #0,d0
93                movea.l d0,a0                   | a0 -> start of FLASH
94                lea     tmpSRAM_BASE,a1         | a1 -> start of tmp SRAM
95|               moveq   #(endPreBoot-V___ISSP)/4,d0     | # longs to copy
96                moveq   #127,d0
97cpy_flash:      move.l  (a0)+,(a1)+             | copy
98                subq.l  #1,d0
99                bne     cpy_flash
100
101|
102| Copy remap code to 68302''s internal system RAM.
103|
104                movea.w #begRemap-V___ISSP,a0   | a0 -> remap code
105                lea     a5@(oSYSRAM),a1 | a1 -> internal system RAM
106|               moveq   #(endRemap-begRemap)/2-1,d0     | d0 = # words to copy
107                moveq   #11,d0
108cpy_remap:      move.w  (a0)+,(a1)+             | copy
109                dbra    d0,cpy_remap
110
111|
112| Jump to the remap code in the 68302''s internal system RAM.
113|
114                jmp     a5@(oSYSRAM)            | (effectively a jmp begRemap)
115
116|
117| This remap code, when executed from the 68302''s internal system RAM
118| will 1) remap CS1 so that SRAM is at 0
119|      2) remap CS0 so that FLASH is at FLASH_BASE
120|  and 3) jump to executable code in the remapped FLASH.
121|
122begRemap:       move.w  #0xa001,a5@(oCS1_Base)  | Move CS1 (SRAM)
123                move.w  #0xd801,a5@(oCS0_Base)  | Move CS0 (FLASH)
124                lea     FLASH_BASE,a0
125                jmp     a0@(endRemap-V___ISSP.w)        | Jump back to FLASH
126endRemap:
127|
128| Now set up the remaining chip select registers.
129|
130
131|
132|      4      0      x    x    x    x
133| 1  000 1  111 0  000 0--- ---- ----
134| x  xxx x  xxx x  xx
135|
136        move.w  #0xb1e1,a5@(oCS2_Base)          | Set up and enable CS2 (dpRAM)
137        move.w  #0x1ff0,a5@(oCS2_Option)        | 8f0000-8f07ff, RW, 0 WS
138
139|
140|      8      X      x    x    x    x
141| 1  000 0  0-- -  --- ---- ---- ----
142| x  xxx x  xxx x  xx
143|
144        move.w  #0xd001,a5@(oCS3_Base)          | Set up and enable CS3 (IO)
145        move.w  #0x1f80,a5@(oCS3_Option)        | 800000-83ffff, RW, 0 WS
146
147endPreBoot:
148
149        move.b  #0x30,0x800001                  | set status LED amber
150
151 .set   oPIOB_Ctrl,     0x824
152 .set   oPIOB_DDR,      0x826
153 .set   oPIOB_Data,     0x828
154
155 .set   oPIOA_Ctrl,     0x81e
156 .set   oPIOA_DDR,      0x820
157 .set   oPIOA_Data,     0x822
158
159        move.w  #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors.
160        move.w  #0x00ff,a5@(oPIOB_DDR)          | Set up PB7-PB0 for output.
161        move.w  #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated
162                                                | peripheral pins.
163
164        move.w  #0x1fff,a5@(oPIOA_Data) | Make output follow resistors.
165        move.w  #0xea2a,a5@(oPIOA_DDR)          | Set up PA15-PA0 for in/output.
166        move.w  #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated
167                                                | peripheral pins.
168
169|
170| Place "Bad" in all vectors from 010 thru 0ec.  Vectors 0f0 and 0f4
171| are not set because they are the 68302''s BAR and SCR.
172|
173                movea.w #0x010,a0
174                moveq   #(0x0f0-0x010)/4-1,d0
175                move.l  #Bad,d1
176cpy_Bad:        move.l  d1,(a0)+
177                dbra    d0,cpy_Bad
178
179 .set   vbase,  0x0200
180
181                lea     vbase,a0
182                moveq   #31,d0
183cpy_Bad1:       move.l  d1,(a0)+
184                dbra    d0,cpy_Bad1
185
186|
187| Fill in special locations to configure OS
188|
189                move.l  #Bad,0x008              | Bus Error
190                move.l  #Bad,0x00c              | Address Error
191                move.l  #Bad,0x024              | Trace
192|               move.l  #KE_IRET,$0b4           | pSOS+ RET_I Call
193
194|               move.l  #_cnsl_isr,vbase+0x028  | SCC2
195                move.l  #timerisr,vbase+0x018   | Timer ISR
196                move.l  #RTC_ISR,vbase+0x024    | Real Time Clock ISR
197
198        |
199        | zero out uninitialized data area
200        |
201zerobss:
202        moveal  # SYM (end),a0                | find end of .bss
203        moveal  # SYM (bss_start),a1          | find beginning of .bss
204        moveq   #0,d0
205
206loop:   movel   d0,a1@+                | to zero out uninitialized
207        cmpal   a0,a1
208        jlt     loop                    | loop until _end reached
209
210        movel   # SYM (end),d0               | d0 = end of bss/start of heap
211        addl    # SYM (heap_size),d0          | d0 = end of heap
212        movel   d0, SYM (stack_start)  | Save for brk() routine
213        addl    # SYM (stack_size),d0         | make room for stack
214        andl    #0xffffffc0,d0         | align it on 16 byte boundary
215        movw    #0x3700,sr             | SUPV MODE,INTERRUPTS OFF!!!
216        movel   d0,a7                 | set master stack pointer
217        movel   d0,a6                 | set base pointer
218
219      /*
220       *  RTEMS should maintiain a separate interrupt stack on CPUs
221       *  without one in hardware.  This is currently not supported
222       *  on versions of the m68k without a HW intr stack.
223       */
224
225#if ( M68K_HAS_SEPARATE_STACKS == 1 )
226        lea     SYM (hiintstack),a0          | a0 = high end of intr stack
227        movec   a0,isp                | set interrupt stack
228#endif
229
230        move.l  #0,a7@-               | environp
231        move.l  #0,a7@-               | argv
232        move.l  #0,a7@-               | argc
233        jsr     SYM (main)
234
235        nop
236Bad:    bra     Bad
237
238        nop
239RTC_ISR:
240        movem.l  d0-d1/a0-a1,a7@-    | save d0-d1,a0-a1
241        addql   #1,_ISR_Nest_level       | one nest level deeper
242        addql   #1,_Thread_Dispatch_disable_level
243                                         | disable multitasking
244
245        jbsr    Clock_isr               | invoke the user ISR
246        jmp     _ISR_Exit
247END_CODE
248
249
250BEGIN_DATA
251
252        PUBLIC (start_frame)
253SYM (start_frame):
254        .space  4,0
255
256        PUBLIC (stack_start)
257SYM (stack_start):
258        .space  4,0
259END_DATA
260
261BEGIN_BSS
262
263        PUBLIC (environ)
264        .align 2
265SYM (environ):
266        .long  0
267
268        PUBLIC (heap_size)
269        .set   SYM (heap_size),0x2000
270
271        PUBLIC (stack_size)
272        .set   SYM (stack_size),0x1000
273
274
275END_DATA
276END
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