| 1 | /* entry.s |
|---|
| 2 | * |
|---|
| 3 | * This file contains the entry point for the application. |
|---|
| 4 | * The name of this entry point is compiler dependent. |
|---|
| 5 | * It jumps to the BSP which is responsible for performing |
|---|
| 6 | * all initialization. |
|---|
| 7 | * |
|---|
| 8 | * COPYRIGHT (c) 1989-1999. |
|---|
| 9 | * On-Line Applications Research Corporation (OAR). |
|---|
| 10 | * |
|---|
| 11 | * The license and distribution terms for this file may be |
|---|
| 12 | * found in the file LICENSE in this distribution or at |
|---|
| 13 | * http://www.rtems.org/license/LICENSE. |
|---|
| 14 | */ |
|---|
| 15 | |
|---|
| 16 | #include <rtems/asm.h> |
|---|
| 17 | |
|---|
| 18 | .set BAR, 0xF2 | Base Address Register location |
|---|
| 19 | .set SCR, 0xF4 | System Control Register location |
|---|
| 20 | .set BAR_VAL, 0x0f7f | BAR value |
|---|
| 21 | .set SCR_VAL, 0x00080f00 | SCR value |
|---|
| 22 | .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). |
|---|
| 23 | .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address |
|---|
| 24 | |
|---|
| 25 | .set oSYSRAM, 0x000 | 576 bytes of internal system RAM |
|---|
| 26 | |
|---|
| 27 | .set oGIMR, 0x812 |
|---|
| 28 | |
|---|
| 29 | .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg |
|---|
| 30 | .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg |
|---|
| 31 | .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg |
|---|
| 32 | .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg |
|---|
| 33 | .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg |
|---|
| 34 | .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg |
|---|
| 35 | .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg |
|---|
| 36 | .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg |
|---|
| 37 | |
|---|
| 38 | .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM |
|---|
| 39 | .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location |
|---|
| 40 | |
|---|
| 41 | BEGIN_CODE |
|---|
| 42 | PUBLIC (M68Kvec) | Vector Table |
|---|
| 43 | SYM (M68Kvec): | standard location for vectors |
|---|
| 44 | V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP |
|---|
| 45 | V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC |
|---|
| 46 | V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error |
|---|
| 47 | V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error |
|---|
| 48 | .space 240 | reserve space for reset of vectors |
|---|
| 49 | |
|---|
| 50 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
|---|
| 51 | SYM (lowintstack): |
|---|
| 52 | .space 4092 | reserve for interrupt stack |
|---|
| 53 | SYM (hiintstack): |
|---|
| 54 | .space 4 | end of interrupt stack |
|---|
| 55 | #endif |
|---|
| 56 | |
|---|
| 57 | PUBLIC (start) | Default entry point for GNU |
|---|
| 58 | SYM (start): |
|---|
| 59 | move.w #0x2700,sr | Disable all interrupts |
|---|
| 60 | move.w #BAR_VAL,BAR | Set Base Address Register |
|---|
| 61 | move.l #SCR_VAL,SCR | Set System Control Register |
|---|
| 62 | lea BaseAddr,a5 |
|---|
| 63 | move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register |
|---|
| 64 | |
|---|
| 65 | | |
|---|
| 66 | | Set up chip select registers for the remapping process. |
|---|
| 67 | | |
|---|
| 68 | |
|---|
| 69 | | |
|---|
| 70 | | 0 X x x x x |
|---|
| 71 | | 0 000 0 0-- - --- ---- ---- ---- |
|---|
| 72 | | x xxx x xxx x xx |
|---|
| 73 | | |
|---|
| 74 | move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) |
|---|
| 75 | move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS |
|---|
| 76 | |
|---|
| 77 | | |
|---|
| 78 | | X x x x x x |
|---|
| 79 | | 0 100 0 0-- - --- ---- ---- ---- |
|---|
| 80 | | x xxx x xxx x xx |
|---|
| 81 | | |
|---|
| 82 | move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) |
|---|
| 83 | move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS |
|---|
| 84 | |
|---|
| 85 | | |
|---|
| 86 | | Copy the initial boot FLASH area to the temporary SRAM location. |
|---|
| 87 | | |
|---|
| 88 | moveq #0,d0 |
|---|
| 89 | movea.l d0,a0 | a0 -> start of FLASH |
|---|
| 90 | lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM |
|---|
| 91 | | moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy |
|---|
| 92 | moveq #127,d0 |
|---|
| 93 | cpy_flash: move.l (a0)+,(a1)+ | copy |
|---|
| 94 | subq.l #1,d0 |
|---|
| 95 | bne cpy_flash |
|---|
| 96 | |
|---|
| 97 | | |
|---|
| 98 | | Copy remap code to 68302''s internal system RAM. |
|---|
| 99 | | |
|---|
| 100 | movea.w #begRemap-V___ISSP,a0 | a0 -> remap code |
|---|
| 101 | lea a5@(oSYSRAM),a1 | a1 -> internal system RAM |
|---|
| 102 | | moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy |
|---|
| 103 | moveq #11,d0 |
|---|
| 104 | cpy_remap: move.w (a0)+,(a1)+ | copy |
|---|
| 105 | dbra d0,cpy_remap |
|---|
| 106 | |
|---|
| 107 | | |
|---|
| 108 | | Jump to the remap code in the 68302''s internal system RAM. |
|---|
| 109 | | |
|---|
| 110 | jmp a5@(oSYSRAM) | (effectively a jmp begRemap) |
|---|
| 111 | |
|---|
| 112 | | |
|---|
| 113 | | This remap code, when executed from the 68302''s internal system RAM |
|---|
| 114 | | will 1) remap CS1 so that SRAM is at 0 |
|---|
| 115 | | 2) remap CS0 so that FLASH is at FLASH_BASE |
|---|
| 116 | | and 3) jump to executable code in the remapped FLASH. |
|---|
| 117 | | |
|---|
| 118 | begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) |
|---|
| 119 | move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) |
|---|
| 120 | lea FLASH_BASE,a0 |
|---|
| 121 | jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH |
|---|
| 122 | endRemap: |
|---|
| 123 | | |
|---|
| 124 | | Now set up the remaining chip select registers. |
|---|
| 125 | | |
|---|
| 126 | |
|---|
| 127 | | |
|---|
| 128 | | 4 0 x x x x |
|---|
| 129 | | 1 000 1 111 0 000 0--- ---- ---- |
|---|
| 130 | | x xxx x xxx x xx |
|---|
| 131 | | |
|---|
| 132 | move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) |
|---|
| 133 | move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS |
|---|
| 134 | |
|---|
| 135 | | |
|---|
| 136 | | 8 X x x x x |
|---|
| 137 | | 1 000 0 0-- - --- ---- ---- ---- |
|---|
| 138 | | x xxx x xxx x xx |
|---|
| 139 | | |
|---|
| 140 | move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) |
|---|
| 141 | move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS |
|---|
| 142 | |
|---|
| 143 | endPreBoot: |
|---|
| 144 | |
|---|
| 145 | move.b #0x30,0x800001 | set status LED amber |
|---|
| 146 | |
|---|
| 147 | .set oPIOB_Ctrl, 0x824 |
|---|
| 148 | .set oPIOB_DDR, 0x826 |
|---|
| 149 | .set oPIOB_Data, 0x828 |
|---|
| 150 | |
|---|
| 151 | .set oPIOA_Ctrl, 0x81e |
|---|
| 152 | .set oPIOA_DDR, 0x820 |
|---|
| 153 | .set oPIOA_Data, 0x822 |
|---|
| 154 | |
|---|
| 155 | move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. |
|---|
| 156 | move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. |
|---|
| 157 | move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated |
|---|
| 158 | | peripheral pins. |
|---|
| 159 | |
|---|
| 160 | move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. |
|---|
| 161 | move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. |
|---|
| 162 | move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated |
|---|
| 163 | | peripheral pins. |
|---|
| 164 | |
|---|
| 165 | | |
|---|
| 166 | | Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 |
|---|
| 167 | | are not set because they are the 68302''s BAR and SCR. |
|---|
| 168 | | |
|---|
| 169 | movea.w #0x010,a0 |
|---|
| 170 | moveq #(0x0f0-0x010)/4-1,d0 |
|---|
| 171 | move.l #Bad,d1 |
|---|
| 172 | cpy_Bad: move.l d1,(a0)+ |
|---|
| 173 | dbra d0,cpy_Bad |
|---|
| 174 | |
|---|
| 175 | .set vbase, 0x0200 |
|---|
| 176 | |
|---|
| 177 | lea vbase,a0 |
|---|
| 178 | moveq #31,d0 |
|---|
| 179 | cpy_Bad1: move.l d1,(a0)+ |
|---|
| 180 | dbra d0,cpy_Bad1 |
|---|
| 181 | |
|---|
| 182 | | |
|---|
| 183 | | Fill in special locations to configure OS |
|---|
| 184 | | |
|---|
| 185 | move.l #Bad,0x008 | Bus Error |
|---|
| 186 | move.l #Bad,0x00c | Address Error |
|---|
| 187 | move.l #Bad,0x024 | Trace |
|---|
| 188 | | move.l #KE_IRET,$0b4 | pSOS+ RET_I Call |
|---|
| 189 | |
|---|
| 190 | | move.l #_cnsl_isr,vbase+0x028 | SCC2 |
|---|
| 191 | move.l #timerisr,vbase+0x018 | Timer ISR |
|---|
| 192 | |
|---|
| 193 | | |
|---|
| 194 | | zero out uninitialized data area |
|---|
| 195 | | |
|---|
| 196 | zerobss: |
|---|
| 197 | moveal # SYM (_clear_end),a0 | find end of .bss |
|---|
| 198 | moveal # SYM (_clear_start),a1 | find beginning of .bss |
|---|
| 199 | moveq #0,d0 |
|---|
| 200 | |
|---|
| 201 | loop: movel d0,a1@+ | to zero out uninitialized |
|---|
| 202 | cmpal a0,a1 |
|---|
| 203 | jlt loop | loop until _clear_end reached |
|---|
| 204 | |
|---|
| 205 | movel d0, SYM (_stack_init) | Set Stack pointer |
|---|
| 206 | movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! |
|---|
| 207 | movel d0,a7 | set master stack pointer |
|---|
| 208 | movel d0,a6 | set base pointer |
|---|
| 209 | |
|---|
| 210 | /* |
|---|
| 211 | * RTEMS should maintain a separate interrupt stack on CPUs |
|---|
| 212 | * without one in hardware. This is currently not supported |
|---|
| 213 | * on versions of the m68k without a HW intr stack. |
|---|
| 214 | */ |
|---|
| 215 | |
|---|
| 216 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
|---|
| 217 | lea SYM (hiintstack),a0 | a0 = high end of intr stack |
|---|
| 218 | movec a0,isp | set interrupt stack |
|---|
| 219 | #endif |
|---|
| 220 | |
|---|
| 221 | move.l #0,a7@- | command line |
|---|
| 222 | jsr SYM (boot_card) |
|---|
| 223 | |
|---|
| 224 | nop |
|---|
| 225 | Bad: bra Bad |
|---|
| 226 | |
|---|
| 227 | nop |
|---|
| 228 | END_CODE |
|---|
| 229 | |
|---|
| 230 | BEGIN_DATA |
|---|
| 231 | |
|---|
| 232 | PUBLIC (start_frame) |
|---|
| 233 | SYM (start_frame): |
|---|
| 234 | .space 4,0 |
|---|
| 235 | |
|---|
| 236 | PUBLIC (stack_start) |
|---|
| 237 | SYM (stack_start): |
|---|
| 238 | .space 4,0 |
|---|
| 239 | END_DATA |
|---|
| 240 | |
|---|
| 241 | BEGIN_BSS |
|---|
| 242 | |
|---|
| 243 | PUBLIC (environ) |
|---|
| 244 | .align 2 |
|---|
| 245 | SYM (environ): |
|---|
| 246 | .long 0 |
|---|
| 247 | |
|---|
| 248 | PUBLIC (heap_size) |
|---|
| 249 | .set SYM (heap_size),0x2000 |
|---|
| 250 | |
|---|
| 251 | PUBLIC (stack_size) |
|---|
| 252 | .set SYM (stack_size),0x1000 |
|---|
| 253 | |
|---|
| 254 | END_DATA |
|---|
| 255 | END |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
